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Digital System Design Assignment Tasks

The document outlines 10 assignments for a digital system design course. The assignments include: 1. Designing Mealy and Moore machines that change output from 0 to 1 when the input sequence "011" is detected, and back to 0 when detected again. 2. Designing Mealy and Moore machines that output 1 when the input sequence "1100" is detected. 3. Designing a finite state machine that functions as a parity checker, maintaining an even/odd count of 1s in the input stream. 4. Designing an asynchronous sequential circuit with two inputs and one output that changes state based on the inputs. 5. Designing Mealy and Moore machines that change output from

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139 views2 pages

Digital System Design Assignment Tasks

The document outlines 10 assignments for a digital system design course. The assignments include: 1. Designing Mealy and Moore machines that change output from 0 to 1 when the input sequence "011" is detected, and back to 0 when detected again. 2. Designing Mealy and Moore machines that output 1 when the input sequence "1100" is detected. 3. Designing a finite state machine that functions as a parity checker, maintaining an even/odd count of 1s in the input stream. 4. Designing an asynchronous sequential circuit with two inputs and one output that changes state based on the inputs. 5. Designing Mealy and Moore machines that change output from

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ASSIGNMENT -1 EEPE17 DEGITAL SYSTEM DESIGN AND

HDLS

1. Design both a Mealy machine and a Moore machine that operate in a way
that the output changes from 0 to 1 when the sequence "011" is detected
and then changes back to 0 when the same sequence is detected
again.(use T flip-flop). For both Overlapping and Non- Overlapping
cases.

2. Using Melay and Moore model design FSM Which gives an output 1,
when 1100 is detected. For both Overlapping and Non- Overlapping
cases. (use D flip-flop).

3. Design a finite state machine that functions as a parity checker for a


binary input stream. The machine should maintain an even parity count of
the number of "1"s encountered so far. If the input stream has an even
number of "1"s, the machine should remain in State A; if the count is odd,
it should transition to State B. The machine should reset the count upon
encountering a "0". Provide the state transition diagram and the state
transition table.

4. It is necessary to design an asynchronous sequential circuit with two


inputs, x, and x2, and one output, z. Initially, both inputs and output are
equal to 0. When x1 or x2 becomes 1, z becomes 1. When the second
input also becomes 1, the output changes to 0. The output stays at 0 until
the circuit goes back to the initial state.
a. Obtain a primitive flow table for the circuit and show that it can be
reduced to the flow table shown in Fig. 1
b. Complete the design of the circuit.

c. Fig. 1
5. Design both a Mealy machine and a Moore machine that operate in a way
that the output changes from 1 to 0 when the sequence "101" is detected
and then changes back to 1 when the same sequence is detected
again.(use D flip-flop). For both Overlapping and Non- Overlapping
cases.

Minimum 4 test cases in testbench code

6. write a verilog code for all logic gates (and, or, not, nand,nor,exor,exnor)
in data flow and gate level modeling ?
7. write a verilog code for 2 bit comparator in data flow and gate level
modeling?
8. write a verilog code BCD to grey and BCD to excess 3 data flow and
gate level modeling?
9. Make structural modeling of 1-to-8 demultiplexer, using behavioral
modeling of 1-to-2 demultiplexer.
10. Make structural modeling of 16-bit ripple carry adder, using behavioral
modeling of 4 bit full adder.

For code verification send code links to [email protected], with


subject as ASSIGNMENT-1
LINK (https://edaplayground.com/x/MBwg) ------ TITLE ( AND GATE )

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