LTC1250

Very Low Noise

Zero-Drift Bridge Amplifier
U
FEATURES DESCRIPTIO
■ Very Low Noise: 0.75µVP-P Typ, 0.1Hz to 10Hz The LTC®1250 is a high performance, very low noise zero-
■ DC to 1Hz Noise Lower Than OP-07 drift operational amplifier. The LTC1250’s combination of
■ Full Output Swing into 1k Load low front-end noise and DC precision makes it ideal for use
■ Offset Voltage: 10µV Max with low impedance bridge transducers. The LTC1250
■ Offset Voltage Drift: 50nV/°C Max features typical input noise of 0.75µVP-P from 0.1Hz to
■ Common-Mode Rejection Ratio: 110dB Min 10Hz, and 0.2µVP-P from 0.1Hz to 1Hz. The LTC1250 has
■ Power Supply Rejection Ratio: 115dB Min DC to 1Hz noise of 0.35µVP-P, surpassing that of low noise
■ No External Components Required bipolar parts including the OP-07, OP-77, and LT1012.
■ Pin-Compatible with Standard 8-Pin Op Amps The LTC1250 uses the industry-standard single op amp
pinout, and requires no external components or nulling
UO signals, allowing it to be a plug-in replacement for bipolar
APPLICATI S op amps.
■ Electronic Scales The LTC1250 incorporates an improved output stage
■ Strain Gauge Amplifiers capable of driving 4.3V into a 1k load with a single 5V
■ Thermocouple Amplifiers supply; it will swing ±4.9V into 5k with ±5V supplies. The
■ High Resolution Data Acquisition input common mode range includes ground with single
■ Low Noise Transducers power supply voltages above 12V. Supply current is 3mA
■ Instrumentation Amplifiers with a ±5V supply, and overload recovery times from
positive and negative saturation are 0.5ms and 1.5ms,
respectively. The internal nulling clock is set at 5kHz for
optimum low frequency noise and offset drift; no external
connections are necessary.
The LTC1250 is available in standard 8-pin ceramic and
and LTC are registered trademarks and LT is a trademark of Linear Technology Corporation. plastic DIPs, as well as an 8-pin SOIC package.

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TYPICAL APPLICATI
Differential Bridge Amplifier Input Referred Noise 0.1Hz to 10Hz
2
5V 5V
VS = ±5V
AV = 10k
50Ω 1000pF
GAIN 0.1µF 1
TRIM

18.2k
µV

0
350Ω 2 7
STRAIN –
GAUGE 6
LTC1250 AV = 100 –1
3
+
4

1000pF 18.2k –2
0 2 4 6 8 10
–5V –5V 1250 TA01 TIME (s)
LT1250 TA02

1
LTC1250
W W W U U W U
ABSOLUTE AXI U RATI GS PACKAGE/ORDER I FOR ATIO
Total Supply Voltage (V + to V –) ............................. 18V TOP VIEW ORDER PART
Input Voltage ........................ (V + + 0.3V) to (V – – 0.3V) NC 1 8 NC NUMBER
Output Short Circuit Duration ......................... Indefinite –IN 2 7 V+
Operating Temperature Range LTC1250MJ8
+IN 3 6 OUT
LTC1250M..................................... – 55°C to 125°C LTC1250CJ8
V– 4 5 NC
LTC1250C .......................................... 0°C TO 70°C LTC1250CN8
J8 PACKAGE N8 PACKAGE LTC1250CS8
Storage Temperature Range ................ – 65°C to 150°C 8-LEAD CERAMIC DIP 8-LEAD PLASTIC DIP
Lead Temperature (Soldering, 10 sec.)................ 300°C S8 PACKAGE
8-LEAD PLASTIC SOIC S8 PART MARKING
TJMAX = 150°C, θJA = 100°CW (J8)
TJMAX = 110°C, θJA = 130°CW (N8) 1250
TJMAX = 110°C, θJA = 200°CW (S8)

ELECTRICAL CHARACTERISTICS VIN = ±5V, TA = Operating Temperature Range, unless otherwise noted.
LTC1250M LTC1250C
SYMBOL PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX UNITS
VOS Input Offset Voltage TA = 25°C (Note 1) ±5 ±10 ±5 ±10 µV
∆VOS Average Input Offset Drift (Note 1) ● ±0.01 ±0.05 ±0.01 ±0.05 µV/°C
Long Term Offset Drift 50 50 nV/√Mo
en Input Noise Voltage (Note 2) TA = 25°C, 0.1Hz to 10Hz 0.75 1.0 0.75 1.0 µVP-P
TA = 25°C, 0.1Hz to 1Hz 0.2 0.2 µVP-P
in Input Noise Current f = 10Hz 4.0 4.0 fA/√Hz
IB Input Bias Current TA = 25°C (Note 3) ±50 ±150 ±50 ±200 pA
● ±950 ±450 pA
IOS Input Offset Current TA = 25°C (Note 3) ±100 ±300 ±100 ±400 pA
● ±500 ±500 pA
CMRR Common-Mode Rejection Ratio VCM = – 4V to 3V ● 110 130 110 130 dB
PSRR Power Supply Rejection Ratio VS = ±2.375V to ±8V ● 115 130 115 130 dB
AVOL Large-Signal Voltage Gain RL = 10k, VOUT = ±4V ● 125 170 125 170 dB
Maximum Output Voltage Swing RL = 1k ● ±4.0 4.3/–4.7 ±4.0 4.3 /–4.7 V
RL = 100k ±4.92 ±4.95 V
SR Slew Rate RL = 10k, CL = 50pF 10 10 V/µs
GBW Gain-Bandwidth Product 1.5 1.5 MHz
IS Supply Current No Load, TA = 25°C 3.0 4.0 3.0 4.0 mA
● 7.0 5.0 mA
fS Internal Sampling Frequency TA = 25°C 4.75 4.75 kHz

VIN = 5V, TA = Operating Temperature Range, unless otherwise noted.

LTC1250M LTC1250C
SYMBOL PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX UNITS
VOS Input Offset Voltage TA = 25°C (Note 1) ±2 ±5 ±2 ±5 µV
∆VOS Average Input Offset Drift (Note 1) ● ±0.01 ±0.05 ±0.01 ±0.05 µV/°C
en Input Noise Voltage (Note 2) TA = 25°C, 0.1Hz to 10Hz 1.0 1.0 µVP-P
TA = 25°C, 0.1Hz to 1Hz 0.3 0.3 µVP-P
IB Input Bias Current TA = 25°C (Note 3) ±20 ±100 ±20 ±100 pA
IOS Input Offset Current TA = 25°C (Note 3) ±40 ±200 ±40 ±200 pA

2
 LTC1250
ELECTRICAL CHARACTERISTICS VIN = 5V, TA = Operating Temperature Range, unless otherwise noted.

LTC1250M LTC1250C
SYMBOL PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX UNITS
Maximum Output Voltage Swing RL = 1k 4.0 4.3 4.0 4.3 V
RL = 100k 4.95 4.95 V
IS Supply Current TA = 25°C 1.8 2.5 1.8 2.5 mA
fS Sampling Frequency TA = 25°C 3 3 kHz
The ● denotes specifications which apply over the full operating filter at 0.1Hz. The LTC1250 is sample tested for noise; for 100% tested
temperature range. parts contact LTC Marketing Dept.
Note 1: These parametes are guaranteed by design. Thermocouple effects Note 3: At T ≤ 0°C these parameters are guaranteed by design and not
preclude measurement of these voltage levels during automated testing. tested.
Note 2: 0.1Hz to 10Hz noise is specified DC coupled in a 10s window;
0.1Hz to 1Hz noise is specified in a 100s window with an RC high-pass

U W
TYPICAL PERFOR A CE CHARACTERISTICS
Sampling Frequency vs Supply
Input Noise vs Supply Voltage Supply Current vs Supply Voltage Voltage
1.6 4.0 6
TA = 25°C TA = 25°C TA = 25°C
1.4 3.5

SAMPLING FREQUENCY (kHz)

1.2 3.0 5
SUPPLY CURRENT (mA)
INPUT NOISE (µVP-P)

1.0 2.5

0.8 0.1Hz TO 10Hz 2.0 4

0.6 1.5

0.4 1.0 3
0.1Hz TO 1Hz
0.2 0.5

0 0 2
4 6 8 10 12 14 16 4 6 8 10 12 14 16 4 6 8 10 12 14 16
TOTAL SUPPLY VOLTAGE, V + TO V – (V) TOTAL SUPPLY VOLTAGE, V + TO V – (V) TOTAL SUPPLY VOLTAGE, V + TO V – (V)
LTC1250 G01 LTC1250 G02 LTC1250 G03

Sampling Frequency vs
Input Noise vs Temperature Supply Current vs Temperature Temperature
1.2 4.5 8
VS = ±5V VS = ±5V VS = ±5V
7
1.0 4.0
SAMPLING FREQUENCY (kHz)

6
SUPPLY CURRENT (mA)
INPUT NOISE (µVP-P)

0.8
3.5 5
0.1Hz TO 10Hz
0.6 4
3.0
3
0.4
0.1Hz TO 1Hz 2
2.5
0.2
1

0 2.0 0
–50 –25 0 25 50 75 100 125 –50 –25 0 25 50 75 100 125 –50 –25 0 25 50 75 100 150
TEMPERATURE (°C) TEMPERATURE (°C) TEMPERATURE (°C)
LTC1250 G04 LTC1250 G05 LTC1250 G06

3
 LTC1250
U W
TYPICAL PERFOR A CE CHARACTERISTICS
Bias Current (Magnitude) vs
Voltage Noise vs Frequency Gain/Phase vs Frequency Temperature
80 100 100 1000
VS = ±5V VS = ±5V
70 RS = 10Ω
80 80
VOLTAGE NOISE (nV/√Hz)

60

BIAS CURRENT (|pA|)

PHASE MARGIN (DEG)
60 60
50 GAIN PHASE:

GAIN (dB)
RL = 100k
40 40 40 100

30
20 PHASE: 20
RL = 1k
20 VS = ±5V OR
SINGLE 5V
0 0
10 TA = 25°C
CL = 100pF
0 –20 –20 10
1 10 100 1k 10k 1k 10k 100k 1M 10M –50 –25 0 25 50 75 100 125
FREQUENCY (Hz) FREQUENCY (Hz) TEMPERATURE (°C)
LTC1250 G11 LTC1250 G10
LTC1250 G14

Common-Mode Input Range Common-Mode Rejection Ratio

Overload Recovery vs Supply Voltage vs Frequency
8 140
TA = 25°C VS = ±5V
0.2 VCM = 1VRMS
INPUT (V)

6
INPUT COMMON MODE RANGE (V)

120

4
0 100
2
CMRR (dB)
0
OUTPUT (V)

80
0
60
–5 –2
40
–4

500µs/DIV 20
–6

AV = 100, RL = 100k, CL = 50pF, VS = ±5V –8 0

2 3 4 5 6 7 8 1 10 100 1k 10k 100k
SUPPLY VOLTAGE (±V) FREQUENCY (Hz)
LTC1250 G07 LTC1250 G12

Output Swing vs Load Output Voltage Swing vs Load

Transient Response Resistance, Dual Supplies Resistance, Single Supply
10 18
RL TO GND VS = 16V
9 16
VS = ±8V
8 14
OUTPUT SWING (±V)
2V/DIV

7
OUTPUT SWING (V)

12
6 VS = 10V
VS = ±5V 10
5
8
4
6 VS = 5V
3 VS = ±2.5V

2 4
1µs/DIV NEGATIVE SWING 2 V – = GND
1 POSITIVE SWING RL TO GND
AV = 1, RL = 100k, CL = 50pF, VS = ±5V
0 0
0 1 2 3 4 5 6 7 8 9 10 0 1 2 3 4 5 6 7 8 9 10
LOAD RESISTANCE (kΩ) LOAD RESISTANCE (kΩ)
LTC1250 G08 LTC1250 G09

4
 LTC1250
U W
TYPICAL PERFOR A CE CHARACTERISTICS
Output Swing vs Output Current, Output Swing vs Output Current, Short-Circuit Current
±5V Supply Single 5V Supply vs Temperature
5 6 40
VS = ±5V VS = SINGLE 5V VS = ±15V
4 30
5

SHORT-CIRCUIT CURRENT (mA)

3 VOUT = V –
20

OUTPUT VOLTAGE (V)

OUTPUT VOLTAGE (V)

2
4
1 10

0 3 0
–1 –10
2
–2
–20
–3 VOUT = V +
1
–30
–4
–5 0 –40
0.01 0.1 1 10 0.01 0.1 1 10 –50 –25 0 25 50 75 100 125
OUTPUT CURRENT (mA) OUTPUT CURRENT (mA) TEMPERATURE (°C)
LTC1250 G16 LTC1250 G17 LTC1250 G18

TEST CIRCUITS
Offset Test Circuit DC to 10Hz Noise Test Circuit
100pF (for DC to 1Hz Multiply All Capacitor Values by 10)
100pF
100k

100k 5V 5V

5V 2 7 2 8 0.04µF 6
– – –
10Ω 6 1 1/2 7
2 7 LTC1250 1/2 OUTPUT
– 800k LT1057 800k 800k LT1057
10Ω 6 3 3 5
LTC1250 OUTPUT + +4 +
4
3
+ 4 0.02µF 0.01µF
–5V –5V
–5V 1250 TC01
1250 TC02

UO U W U
APPLICATI S I FOR ATIO
80
Input Noise VS = ±5V
70 RS = 10Ω
The LTC1250, like all CMOS amplifiers, exhibits two types OP-27 OP-07
VOLTAGE NOISE (nV/√Hz)

60
of low frequency noise: thermal noise and 1/f noise. The
LTC1250 uses several design modifications to minimize 50
LTC1250
these noise sources. Thermal noise is minimized by rais- 40

ing the gM of the front-end transistors by running them at 30

high bias levels and using large transistor geometries. 1/f 20
noise is combated by optimizing the zero-drift nulling loop
10
to run at twice the 1/f corner frequency, allowing it to
0
reduce the inherently high CMOS 1/f noise to near thermal 0.01 0.1 1
levels at low frequencies. The resultant noise spectrum is FREQUENCY (Hz)
LTC1250 F01
quite low at frequencies below the internal 5kHz clock
Figure 1. Voltage Noise vs Frequency

5
LTC1250
UO U W U
APPLICATI S I FOR ATIO
frequency, approaching the best bipolar op amps at 10Hz fully cancel the 1/f noise spectrum and the low frequency
and surpassing them below 1Hz (Figure 1). All this is noise of the part will rise. If the loop is underdamped (large
accomplished in an industry-standard pinout; the LTC1250 RF, no CF) it will ring for more than 150µs and the noise
requires no external capacitors, no nulling or clock sig- and offset will suffer.
nals, and conforms to industry-standard 8-pin DIP and 8-
The solution is to add CF as above but beware! Too large
pin SOIC packages.
a value of CF will overdamp the loop, again preventing it
Input Capacitance and Compensation from reaching a final value by the 150µs deadline. This
condition doesn’t affect the LTC1250’s offset or output
The large input transistors create a parasitic 55pF capaci- stability, but 1/f noise begins to rise. As a rule of thumb,
tance from each input to V +. This input capacitance will the RFCF feedback pole should be ≥ 7kHz (1/150µs, the
react with the external feedback resistors to form a pole
frequency at which the loop settles) for best 1/f perfor-
which can affect amplifier stability. In low gain, high
mance; values between 100pF and 500pF work well with
impedance configurations, the pole can land below the
feedback resistors below 100k. This ensures adequate
unity-gain frequency of the feedback network and degrade
gain at 7kHz for the LTC1250 to properly null. High value
phase margin, causing ringing, oscillation, and other
feedback resistors (above 1M) may require experimenta-
unpleasantness. This is true of any op amp, however, the
55pF capacitance at the LTC1250’s inputs can affect tion to find the correct value because parasitics, both in
stability with a feedback network impedance as low as the LTC1250 and on the PC board, play an increasing role.
1.9k. This effect can be eliminated by adding a capacitor Low value resistors (below 5k) may not require a capaci-
across the feedback resistor, adding a zero which cancels tor at all.
the input pole (Figure 2). The value of this capacitor should
Input Bias Current
be:
55pF
CF ≥ The inputs of the LTC1250, like all zero-drift op amps,
AV draw only small switching spikes of AC bias current; DC
leakage current is negligible except at very high tempera-
where AV = closed-loop gain. Note that CF is not dependent tures. The large front-end transistors cause switching
on the value of RF. Circuits with higher gain (AV > 50) or spikes 3 to 4 times greater than standard zero-drift op
low loop impedance should not require CF for stability. amps: the ±50pA bias current spec is still many times
CF better than most bipolar parts. The spikes don’t match
from one input pin to the other, and are sometimes (but
RF not always) of opposite polarity. As a result, matching the
RIN
impedances at the inputs (Figure 3) will not cancel the bias
– current, and may cause additional errors. Don’t do it.
LTC1250
CP
+ RF
1250 F02

RIN
–
Figure 2. CF Cancels Phase Shift Due to Parasitic CP
LTC1250

Larger values of CF, commonly used in band-limited DC +

1250 F03

circuits, may actually increase low frequency noise. The

nulling circuitry in the LTC1250 closes a loop that includes
the external feedback network during part of its cycle. This
loop must settle to its final value within 150µs or it will not Figure 3. Extra Resistor Will Not Cancel Bias Current Errors

6
 LTC1250
UO U W U
APPLICATI S I FOR ATIO
Output Drive the previous page). Applications which require spike-free
The LTC1250 includes an enhanced output stage which output in addition to minimum noise will need a low-pass
provides nearly symmetrical output source/sink currents. filter after the LTC1250; a simple RC will usually do the job
This output is capable of swinging a minimum of ±4V into a (Figure 4). The LTC1051/LTC1053 data sheet includes more
1k load with ±5V supplies, and can sink or source >20mA information about zero-drift amplifier sampling behavior.
into low impedance loads. Lightly loaded (RL ≥100k), the CF

LTC1250 will swing to within millivolts of either rail. In single

RF
supply applications, it will typically swing 4.3V into a 1k load
with a 5V supply. –
47k
Minimizing External Errors LTC1250
+ 0.01
The input noise, offset voltage, and bias current specs for the
LTC1250 are all well below the levels of circuit board 1250 F04

parasitics. Thermocouples between the copper pins of the

Figure 4. RC Output Pole Limits Bandwidth to 330Hz
LTC1250 and the tin/lead solder used to connect them can
overwhelm the offset voltage of the LTC1250, especially if a Single Supply Operation
soldering iron has been around recently. Note also that when
The LTC1250 will operate with single supply voltages as low
the LTC1250’s output is heavily loaded, the chip may
as 4.5V, and the output swings to within millivolts of either
dissipate substantial power, raising the temperature of the
package and aggravating thermocouples at the inputs. supply when lightly loaded. The input stage will common
Although the LTC1250 will maintain its specified accuracy mode to within 250mV of ground with a single 5V supply,
under these conditions, care must be taken in the layout to and will common mode to ground with single supplies
prevent or compensate circuit errors. Be especially careful above 11V. Most bridge transducers bias their inputs above
of air currents when measuring low frequency noise; nearby ground when powered from single supplies, allowing them
moving objects (like people) can create very large noise to interface directly to the LTC1250 in single supply applica-
peaks with an unshielded circuit board. For more detailed tions. Single-ended, ground-referenced signals will need to
explanations and advice on how to avoid these errors, see be level shifted slightly to interface to the LTC1250’s inputs.
the LTC1051/LTC1053 data sheet. Fault Conditions
Sampling Behavior The LTC1250 is designed to withstand most external fault
conditions without latch-up or damage. However, unusually
The LTC1250’s zero-drift nulling loop samples the input at
severe fault conditions can destroy the part. All pins are
≈ 5kHz, allowing it to process signals below 2kHz with no
protected against faults of ±25mA or 5V beyond either
aliasing. Signals above this frequency may show aliasing
supply, whichever comes first. If the external circuitry can
behavior, although wideband internal circuitry generally
exceed these limits, series resistors or voltage clamp diodes
keeps errors to a minimum. The output of the LTC1250 will
should be included to prevent damage.
have small spikes at the clock frequency and its harmonics;
these will vary in amplitude with different feedback configu- The LTC1250 includes internal protection against ESD dam-
rations. Low frequency or band-limited systems should not age. All data sheet parameters are maintained to 1kV ESD on
be affected, but systems with higher bandwidth any pin; beyond 1kV, the input bias and offset currents will
(oversampling A/Ds, for example) may need to filter out increase, but the remaining specs are unaffected and the
these clock artifacts. Output spikes can be minimized with a part remains functional to 5kV at the input pins and 8kV at the
large feedback capacitor, but this will adversely affect noise output pin. Extreme ESD conditions should be guarded
performance (see Input Capacitance and Compensation on against by using standard anti-static precautions.

7
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
LTC1250
UO
TYPICAL APPLICATI S
Reference Buffer Differential Thermocouple Ampliifer

15V R3
C1 1M
7.5k 100pF 0.1%
3 7 R1
+ 10k 5V
3 1 6
LTC1250 0.1% 2 7
2 –
LM399 – 4 6 VOUT
LTC1250
100mV/°C
3
+ R6
4 2 – + R2 4 7.5k
10k 1%
TYPE K † 0.1% –5V
R4 R7
±10ppm ERROR AT ±15mA VCM C2
1M 500Ω
1µVP-P OUTPUT NOISE 100pF
0.1% FULL-SCALE TRIM
2.5µV/°C DRIFT (DUE TO LM399) 1250 TA03
5V
R8
R5 5k
VIN 3k 1%
10mV/°C
VOUT
†
LT1025 R9 FOR BEST ACCURACY, THERMOCOUPLE
33k RESISTANCE SHOULD BE LESS THAN 100Ω
GND
–5V
1250 TA04

U
PACKAGE DESCRIPTIO Dimensions in inches (millimeters) unless otherwise noted.
J8 Package 8-Lead Ceramic DIP N8 Package 8-Lead Plastic DIP
CORNER LEADS OPTION 0.405 0.400*
(4 PLCS) (10.287) (10.160)
0.005 MAX MAX
(0.127)
MIN 8 7 6 5
8 7 6 5
0.023 – 0.045
(0.584 – 1.143)
HALF LEAD
OPTION 0.025 0.255 ± 0.015*
0.220 – 0.310
0.045 – 0.068 (0.635) (6.477 ± 0.381)
(5.588 – 7.874)
(1.143 – 1.727) RAD TYP
FULL LEAD
OPTION 1 2 3 4
1 2 3 4 0.200
0.300 BSC
(5.080) 0.300 – 0.325 0.130 ± 0.005
(0.762 BSC) 0.045 – 0.065
MAX (3.302 ± 0.127)
(7.620 – 8.255) (1.143 – 1.651)

0.015 – 0.060
(0.381 – 1.524)
0.065
(1.651)
0.008 – 0.018 0.009 – 0.015 TYP
0° – 15° (0.229 – 0.381) 0.125
(0.203 – 0.457)
(3.175) 0.015
+0.025 0.045 ± 0.015 MIN (0.380)
0.045 – 0.068 0.325 –0.015

( )
0.385 ± 0.025 (1.143 ± 0.381) MIN
0.125
(9.779 ± 0.635) (1.143 – 1.727) +0.635
3.175 8.255
–0.381 0.100 ± 0.010 0.018 ± 0.003
0.014 – 0.026 0.100 ± 0.010 MIN (2.540 ± 0.254) (0.457 ± 0.076) N8 0694

(0.360 – 0.660) (2.540 ± 0.254)

*THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS.
MOLD FLASH OR PROTURSIONS SHALL NOT EXCEED 0.010 INCH (0.254mm).
NOTE: LEAD DIMENSIONS APPLY TO SOLDER DIP/PLATE OR TIN PLATE LEADS.
J8 0694

S8 Package 8-Lead Plastic SOIC 0.189 – 0.197*

(4.801 – 5.004)
0.010 – 0.020 7 5
× 45° 0.053 – 0.069 8 6
(0.254 – 0.508)
(1.346 – 1.752)
0.004 – 0.010
0.008 – 0.010
0°– 8° TYP (0.101 – 0.254)
(0.203 – 0.254)

0.228 – 0.244 0.150 – 0.157*

0.016 – 0.050 (5.791 – 6.197) (3.810 – 3.988)
0.014 – 0.019 0.050
0.406 – 1.270
(0.355 – 0.483) (1.270)
BSC
*THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS.
MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.006 INCH (0.15mm).
SO8 0294
1 2 3 4

LT/GP 0894 2K REV A • PRINTED IN USA

Linear Technology Corporation
8 1630 McCarthy Blvd., Milpitas, CA 95035-7487
(408) 432-1900 ● FAX: (408) 434-0507 ● TELEX: 499-3977  LINEAR TECHNOLOGY CORPORATION 1994