OPA337, OPA2337

OPA338, OPA2338
SBOS077B − JUNE 1997 − REVISED MARCH 2005

MicroSIZE, Single-Supply
CMOS OPERATIONAL AMPLIFIERS
MicroAmplifierE Series

FEATURES DESCRIPTION
D MicroSIZE PACKAGES: The OPA337 and OPA338 series rail-to-rail output CMOS
SOT23-5, SOT23-8 operational amplifiers are designed for low cost and
miniature applications. Packaged in the SOT23-8, the
D SINGLE-SUPPLY OPERATION OPA2337EA and OPA2338EA are Texas Instruments’
D RAIL-TO-RAIL OUTPUT SWING smallest dual op amps. At 1/4 the size of a conventional
SO-8 surface-mount, they are ideal for space-sensitive
D FET-INPUT: IB = 10pA max applications.
D HIGH SPEED:
Utilizing advanced CMOS technology, the OPA337 and
OPA337: 3MHz, 1.2V/µs (G = 1)
OPA338 op amps provide low bias current, high-speed
OPA338: 12.5MHz, 4.6V/µs (G = 5) operation, high open-loop gain, and rail-to-rail output
D OPERATION FROM 2.5V to 5.5V swing. They operate on a single supply with operation as
low as 2.5V while drawing only 525µA quiescent current.
D HIGH OPEN-LOOP GAIN: 120dB
In addition, the input common-mode voltage range
D LOW QUIESCENT CURRENT: 525µA/amp includes ground—ideal for single-supply operation.
D SINGLE AND DUAL VERSIONS The OPA337 series is unity-gain stable. The OPA338 series
is optimized for gains greater than or equal to 5. They are
easy-to-use and free from phase inversion and overload
APPLICATIONS problems found in some other op amps. Excellent
D BATTERY-POWERED INSTRUMENTS performance is maintained as the amplifiers swing to their
specified limits. The dual versions feature completely
D PHOTODIODE PRE-AMPS independent circuitry for lowest crosstalk and freedom from
D MEDICAL INSTRUMENTS interaction, even when overdriven or overloaded.
D TEST EQUIPMENT
G = 1 STABLE G ≥ 5 STABLE
D AUDIO SYSTEMS SINGLE DUAL SINGLE DUAL
D DRIVING ADCs PACKAGE OPA337 OPA2337 OPA338 OPA2338
SOT23-5 n n
D CONSUMER PRODUCTS SOT23-8 n n
SPICE model available at [Link]. MSOP-8 n
SO-8 n n n n
DIP-8 n n

OPA337, OPA338 OPA337, OPA338

OPA2337, OPA2338

NC 1 8 NC Out 1 5 V+
Out A 1 8 V+
−In 2 7 V+ V− 2 A
− In A 2 7 Out B
+In 3 6 Output +In 3 4 −In B
+In A 3 6 − In B
V− 4 5 NC
SOT23−5 V− 4 5 +In B

DIP−8(1), SO−8, MSOP−8(1)

NC = No Connection NOTE: (1) DIP AND MSOP−8 versions for OPA337, OPA2337 only. DIP−8(1) , SO−8, SOT23−8

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments
semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.

             
 Copyright  1997-2005, Texas Instruments Incorporated
                  

   !       !   

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SBOS077B − JUNE 1997 − REVISED MARCH 2005

This integrated circuit can be damaged by ESD. Texas

ABSOLUTE MAXIMUM RATINGS(1) Instruments recommends that all integrated circuits be
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.5V handled with appropriate precautions. Failure to observe
Input Voltage(2) . . . . . . . . . . . . . . . . . . . . (V−) − 0.5V to (V+) + 0.5V proper handling and installation procedures can cause damage.
Input Current(2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10mA
Output Short Circuit(3) . . . . . . . . . . . . . . . . . . . . . . . . . . Continuous ESD damage can range from subtle performance degradation to
Operating Temperature . . . . . . . . . . . . . . . . . . . . . −55°C to +125°C complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . −55°C to +125°C
cause the device not to meet its published specifications.
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150°C
Lead Temperature (soldering, 10s) . . . . . . . . . . . . . . . . . . . . . 300°C
(1) Stresses above these ratings may cause permanent damage.
Exposure to absolute maximum conditions for extended periods
may degrade device reliability. These are stress ratings only, and
functional operation of the device at these or any other conditions
beyond those specified is not supported.
(2) Input signal voltage is limited by internal diodes connected to
power supplies. See text.
(3) Short-circuit to ground, one amplifier per package.

ORDERING INFORMATION(1)
SPECIFIED
PACKAGE PACKAGE ORDERING TRANSPORT
PRODUCT DESCRIPTION PACKAGE-LEAD TEMPERATURE
DESIGNATOR MARKING NUMBER MEDIA, QUANTITY
RANGE
OPA337 Series
OPA337NA/250 Tape and Reel, 250
SOT23-5 DBV C37
OPA337NA/3K Tape and Reel, 3000
OPA337EA/250 Tape and Reel, 250
Single, MSOP-8 DGK G37
OPA337 −40°C
−40 C to +85
+85°C
C OPA337EA/2K5 Tape and Reel, 2500
G = 1 Stable
DIP-8 P OPA337PA OPA337PA Rails

SO-8 OPA337UA Rails

D OPA337UA
Surface-Mount OPA337UA/2K5 Tape and Reel, 2500
OPA2337EA/250 Tape and Reel, 250
SOT23-8 DCN A7
OPA2337EA/3K Tape and Reel, 3000
Dual,
OPA2337 DIP-8 P −40°C
−40 C to +85
+85°C
C OPA2337PA OPA2337PA Rails
G = 1 Stable
SO-8 OPA2337UA Rails
D OPA2337UA
Surface-Mount OPA2337UA/2K5 Tape and Reel, 2500
OPA338 Series
OPA338NA/250 Tape and Reel, 250
SOT23-5 DBV A38
Single, OPA338NA/3K Tape and Reel, 3000
OPA338 −40°C to +85°C
G ≥ 5 Stable OPA338UA Rails
SO-8
D OPA338UA
Surface-Mount OPA338UA/2K5 Tape and Reel, 2500
OPA2338EA/250 Tape and Reel, 250
SOT23-8 DCN A8
Dual, OPA2338EA/3K Tape and Reel, 3000
OPA2338 −40°C to +85°C
G ≥ 5 Stable OPA2338UA Rails
SO-8
D OPA2338UA
Surface-Mount OPA2338UA/2K5 Tape and Reel, 2500
(1) For the most current package and ordering information, see the Package Option Addendum located at the end of this data sheet.

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SBOS077B − JUNE 1997 − REVISED MARCH 2005

ELECTRICAL CHARACTERISTICS: VS = 2.7V to 5.5V

Boldface limits apply over the specified temperature range, −405C to +855C, VS = 5V.
At TA = +25°C and RL = 25kΩ connected to VS/2, unless otherwise noted.
OPA337, OPA2337,
OPA338, OPA2338
PARAMETER CONDITION MIN TYP(1) MAX UNIT
OFFSET VOLTAGE
Input Offset Voltage VOS ±0.5 ±3 mV
TA = −40°C to +85°C ±3.5 mV
vs Temperature dVOS/dT ±2 µV/°C
vs Power-Supply Rejection Ratio PSRR VS = 2.7V to 5.5V 25 125 µV/V
TA = −40°C to +85°C VS = 2.7V to 5.5V 125 µV/V
Channel Separation (dual versions) dc 0.3 µV/V
INPUT BIAS CURRENT
Input Bias Current IB ±0.2 ±10 pA
TA = −40°C to +85°C See Typical Curve
Input Offset Current IOS ±0.2 ±10 pA
NOISE
Input Voltage Noise, f = 0.1Hz to 10Hz 6 µVPP
Input Voltage Noise Density, f = 1kHz en 26 nV/√Hz
Current Noise Density, f = 1kHz in 0.6 fA/√Hz
INPUT VOLTAGE RANGE
Common-Mode Voltage Range VCM TA = −40°C to +85°C −0.2 (V+) − 1.2 V
Common-Mode Rejection Ratio CMRR −0.2V < VCM < (V+) − 1.2V 74 90 dB
TA = −40°C to +85°C −0.2V < VCM < (V+) − 1.2V 74 dB
INPUT IMPEDANCE
Differential 1013 2 Ω  pF
Common-Mode 1013 4 Ω  pF
OPEN-LOOP GAIN
Open-Loop Voltage Gain AOL RL = 25kΩ, 125mV < VO < (V+) − 125mV 100 120 dB
TA = −40°C to +85°C RL = 25kΩ, 125mV < VO < (V+) − 125mV 100 dB
RL = 5kΩ, 500mV < VO < (V+) − 500mV 100 114 dB
TA = −40°C to +85°C RL = 5kΩ, 500mV < VO < (V+) − 500mV 100 dB
OPA337 FREQUENCY RESPONSE
Gain-Bandwidth Product GBW VS = 5V, G = 1 3 MHz
Slew Rate SR VS = 5V, G = 1 1.2 V/µs
Settling TIme: 0.1% VS = 5V, 2V Step, CL = 100pF, G = 1 2 µs
0.01% VS = 5V, 2V Step, CL = 100pF, G = 1 2.5 µs
Overload Recovery Time VIN × G = VS 2 µs
Total Harmonic Distortion + Noise THD+N VS = 5V, VO = 3VPP, G = 1, f = 1kHz 0.001 %
OPA338 FREQUENCY RESPONSE
Gain-Bandwidth Product GBW VS = 5V, G = 5 12.5 MHz
Slew Rate SR VS = 5V, G = 5 4.6 V/µs
Settling TIme: 0.1% VS = 5V, 2V Step, CL = 100pF, G = 5 1.4 µs
0.01% VS = 5V, 2V Step, CL = 100pF, G = 5 1.9 µs
Overload Recovery Time VIN × G = VS 0.5 µs
Total Harmonic Distortion + Noise THD+N VS = 5V, VO = 3VPP, G = 5, f = 1kHz 0.0035 %
(1) VS = 5V.
(2) Output voltage swings are measured between the output and negative and positive power-supply rails.

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SBOS077B − JUNE 1997 − REVISED MARCH 2005

ELECTRICAL CHARACTERISTICS: VS = 2.7V to 5.5V (continued)

Boldface limits apply over the specified temperature range, −405C to +855C, VS = 5V.
At TA = +25°C and RL = 25kΩ connected to VS/2, unless otherwise noted.
OPA337, OPA2337,
OPA338, OPA2338
PARAMETER CONDITION MIN TYP(1) MAX UNIT
OUTPUT
Voltage Output Swing from Rail(2) RL = 25kΩ, AOL ≥ 100dB 40 125 mV
TA = −40°C to +85°C RL = 25kΩ, AOL ≥ 100dB 125 mV
RL = 5kΩ, AOL ≥ 100dB 150 500 mV
TA = −40°C to +85°C RL = 5kΩ, AOL ≥ 100dB 500 mV
Short-Circuit Current ±9 mA
Capacitive Load Drive See Typical Curve
POWER SUPPLY
Specified Voltage Range VS TA = −40°C to +85°C 2.7 5.5 V
Minimum Operating Voltage 2.5 V
Quiescent Current (per amplifier) IQ IO = 0 0.525 1 mA
TA = −40°C to +85°C IO = 0 1.2 mA
TEMPERATURE RANGE
Specified Range −40 +85 °C
Operating Range −55 +125 °C
Storage Range −55 +125 °C
Thermal Resistance qJA
SOT23-5 Surface-Mount 200 °C/W
SOT23-8 Surface-Mount 200 °C/W
MSOP-8 150 °C/W
SO-8 Surface-Mount 150 °C/W
DIP-8 100 °C/W
(1) VS = 5V.
(2) Output voltage swings are measured between the output and negative and positive power-supply rails.

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SBOS077B − JUNE 1997 − REVISED MARCH 2005

TYPICAL CHARACTERISTICS
At TA = +25°C, VS = +5V, and RL = 25kΩ connected to VS/2, unless otherwise noted.

POWER−SUPPLY REJECTION RATIO AND

OPEN−LOOP GAIN/PHASE vs FREQUENCY COMMON−MODE REJECTION RATIO vs FREQUENCY
160 0 100
OPA337 90 +PSRR
140
OPA338
120 −45 80 −PSRR
Open−Loop Gain (dB)

PSRR, CMRR (dB)

100 70
φ

Phase (_)
80 −90 60
60 50
G CMRR
40 −135 40
20 30
0 −180
20
−20
10
1 10 100 1k 10k 100k 1M 10M
1 10 100 1k 10k 100k 1M 10M
Frequency (Hz)
Frequency (Hz)

INPUT VOLTAGE AND CURRENT NOISE CHANNEL SEPARATION vs FREQUENCY

SPECTRAL DENSITY vs FREQUENCY 140
1k 1k

130
Voltage Noise
Channel Separation (dB)
Voltage Noise (nV√Hz)

100
Current Noise (fA√Hz)

100
120

10 10 110

100
1 Dual Versions
1
Current Noise 90

0.1 0.1
80
1 10 100 1k 10k 100k 1M 100 1k 10k 100k 1M
Frequency (Hz) Frequency (Hz)

INPUT BIAS CURRENT

INPUT BIAS CURRENT vs TEMPERATURE vs INPUT COMMON−MODE VOLTAGE
100 0.5

0.4
10
Input Bias Current (pA)

Input Bias Current (pA)

0.3

1
0.2

0.1
0.1

0.01
−75 −50 −25 0 25 50 75 100 125 −0.1
−1 0 1 2 3 4 5
Temperature (_C)
Common−Mode Voltage (V)

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SBOS077B − JUNE 1997 − REVISED MARCH 2005

TYPICAL CHARACTERISTICS (continued)

At TA = +25°C, VS = +5V, and RL = 25kΩ connected to VS/2, unless otherwise noted.

QUIESCENT CURRENT AND SHORT−CIRCUIT CURRENT

AOL, CMRR, PSRR vs TEMPERATURE
vs TEMPERATURE
140 130 600 12

130 120 550 IQ 11

AOL

Short−Circuit Current (mA)

Quiescent Current (µA)
120 110
AOL, CMRR (dB)

500 10

PSRR (dB)
−ISC
110 100 9
PSRR 450
+ISC
100 90 8
400

90 80
350 7
CMRR
80 70
300 6
−75 −50 −25 0 25 50 75 100 125
−75 −50 −25 0 25 50 75 100 125
Temperature (_C)
Temperature (_C)

QUIESCENT AND SHORT−CIRCUIT CURRENT MAXIMUM OUTPUT VOLTAGE vs FREQUENCY

vs SUPPLY VOLTAGE
6
700 ±12
Maximum output
5 voltage without slew
650 ±10 rate−induced distortion.
Short−Circuit Current (mA)

Output Voltage (VPP)

Quiescent Current (µA)

4
600 ±8
OPA338
+ISC 3
550 ±6
OPA337

±4 2
500 −ISC
IQ
450 ±2 1

400 0 0
2.5 3.0 3.5 4.0 4.5 5.0 5.5 10k 100k 1M 10M 100M
Supply Voltage (V) Frequency (Hz)

TOTAL HARMONIC DISTORTION + NOISE

OUTPUT VOLTAGE SWING vs OUTPUT CURRENT
vs FREQUENCY
0.1 2.5
VS = ±2.5V
2.0 RL Tied to Ground
1.5
Sourcing −55_C
Output Voltage (V)

1.0
0.01 G = +10, RL = 5kΩ, 25kΩ
0.5
THD+N (%)

G = +5, RL = 5kΩ, 25kΩ

0 25_C 125_C
RL = 5kΩ RL = 25kΩ −0.5
G = +1
0.001 −1.0
−55_ C
−1.5
Sinking
OPA337 −2.0
OPA338 VO = 3VPP
0.0001 −2.5
20 100 1k 10k 20k 0 ±1 ±2 ±3 ±4 ±5 ±6 ±7 ±8

Frequency (Hz) Output Current (mA)

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TYPICAL CHARACTERISTICS (continued)

At TA = +25°C, VS = +5V, and RL = 25kΩ connected to VS/2, unless otherwise noted.

OFFSET VOLTAGE OFFSET VOLTAGE DRIFT

PRODUCTION DISTRIBUTION PRODUCTION DISTRIBUTION
25 30
Typical distribution Typical distribution
of packaged units. of packaged units.
25
20

Percent of Amplifiers (%)

Percent of Amplifiers (%)

20
15
15
10
10

5
5

0 0
0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
−3.0

−2.5

−2.0

−1.5

−1.0

−0.5

0.5

1.0

1.5

2.0

2.5

3.0
Offset Voltage Drift (µV/_ C)
Offset Voltage (mV)

SMALL−SIGNAL OVERSHOOT vs LOAD CAPACITANCE

SETTLING TIME vs CLOSED−LOOP GAIN
60
100

50
OPA338
0.01%
(G = ±5) OPA337
40
Settling Time (µs)

Overshoot (%)

(G = ±1)

30
10 OPA338
OPA337
OPA337 20 (G = ±10)

10 OPA338
(G = ±50)
0.1%
0
1
10 100 1k 10k
1 10 100 1k
Load Capacitance (pF)
Closed−Loop Gain (V/V)

SMALL−SIGNAL STEP RESPONSE LARGE−SIGNAL STEP RESPONSE

C L = 100pF C L = 100pF
VS = +5V VS = +5V
OPA337 OPA338
G=1 G=5
500mV/div
50mV/div

OPA337
G =1
OPA338
G=5

1µs/div 2µs/div

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Normally, input currents are 0.2pA. However, large inputs

APPLICATIONS INFORMATION (greater than 500mV beyond the supply rails) can cause
The OPA337 and OPA338 series are fabricated on a excessive current to flow in or out of the input pins.
state-of-the-art CMOS process. The OPA337 series is Therefore, as well as keeping the input voltage below the
unity-gain stable. The OPA338 series is optimized for maximum rating, it is also important to limit the input
gains greater than or equal to 5. Both are suitable for a current to less than 10mA. This is easily accomplished
wide range of general-purpose applications. Power- with an input resistor as shown in Figure 2.
supply pins should be bypassed with 0.01µF ceramic
capacitors.

OPERATING VOLTAGE +5V

The OPA337 series and OPA338 series can operate from I OVERLOAD
a +2.5V to +5.5V single supply with excellent 10mA max
performance. Unlike most op amps which are specified at OPA337 VOUT
VIN
only one supply voltage, these op amps are specified for
5kΩ
real-world applications; a single limit applies throughout
the +2.7V to +5.5V supply range. This allows a designer
to have the same assured performance at any supply
voltage within the specified voltage range. Most behavior Figure 2. Input Current Protection for Voltages
remains unchanged throughout the full operating voltage Exceeding the Supply Voltage
range. Parameters which vary significantly with operating
voltage are shown in the Typical Characteristic curves. USING THE OPA338 IN LOW GAINS
The OPA338 series is optimized for gains greater than or
INPUT VOLTAGE equal to 5. It has significantly wider bandwidth (12.5MHz)
The input common-mode range extends from (V−) − 0.2V and faster slew rate (4.6V/µs) when compared to the
to (V+) − 1.2V. For normal operation, inputs should be OPA337 series. The OPA338 series can be used in lower
limited to this range. The absolute maximum input voltage gain configurations at low frequencies while maintaining
is 500mV beyond the supplies. Inputs greater than the its high slew rate with the proper compensation.
input common-mode range but less than maximum input
voltage, while not valid, will not cause any damage to the Figure 3 shows the OPA338 in a unity-gain buffer
op amp. Furthermore, if input current is limited the inputs configuration. At dc, the compensation capacitor C1 is
may go beyond the power supplies without phase effectively open resulting in 100% feedback (closed-loop
inversion (as shown in Figure 1) unlike some other op gain = 1). As frequency increases, C1 becomes lower
amps. impedance and closed-loop gain increases, eventually
becoming 1 + R2/R1 (in this case 5, which is equal to the
minimum gain required for stability).
OPA337, VIN = ±3V Greater Than VS = ±2.5V

VOUT, G = −1 Improved slew rate (4.6V/µs) versus R2

3V (not limited by OPA337 (1.2V/µs) in unity gain. 10kΩ
input common−
mode range) R1
2.5kΩ
C1
0V OPA338 VOUT
68pF
VIN
G = ±1 VOUT, G = +1 1
(limited by input C1 =
2πfCR1
common−mode
−3V range)
Where f C is the frequency at which closed−loop
gains less than 5 are not appropriatesee text.

Figure 1. OPA337—No Phase Inversion with Figure 3. Compensation of the OPA338 for
Inputs Greater than the Power-Supply Voltage Unity-Gain Buffer

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SBOS077B − JUNE 1997 − REVISED MARCH 2005

The required compensation capacitor value can be C1 is determined from the desired high-frequency gain (GH):
determined from the following equation:
C1 = (GH − 1) × C2
C1 = 1/(2πfCR1)
For a desired dc gain of 2 and high-frequency gain of 10,
Since fC may shift with process variations, it is the following resistor and capacitor values result:
recommended that a value less than fC be used for R1 = 10kΩ C1 = 150pF
determining C1. With fC = 1MHz and R1 = 2.5kΩ, the
compensation capacitor is about 68pF. R2 = 5kΩ C2 = 15pF

The selection of the compensation capacitor C1 is The capacitor values shown are the nearest standard
important. A proper value ensures that the closed-loop values. Capacitor values may need to be adjusted slightly
circuit gain is greater than or equal to 5 at high frequencies. to optimize performance. For more detailed information,
Referring to the Open-Loop Gain vs Frequency plot in the consult the section on Low Gain Compensation in the
Typical Characteristics section, the OPA338 gain line OPA846 data sheet (SBOS250) located at [Link].
(dashed in the curve) has a constant slope Figure 5 shows the large-signal transient response using
(−20dB/decade) up to approximately 3MHz. This the circuit given in Figure 4. As shown, the OPA338 is
frequency is referred to as fC. Beyond fC the slope of the stable in low gain applications and provides improved slew
curve increases, suggesting that closed-loop gains less rate performance when compared to the OPA337.
than 5 are not appropriate.
Figure 4 shows a compensation technique using an
inverting configuration. The low-frequency gain is set by
the resistor ratio while the high-frequency gain is set by the
capacitor ratio. As with the noninverting circuit, for OPA338
frequencies above fC the gain must be greater than the 500mV/div
recommended minimum stable gain for the op amp.
OPA337

C2
Improved slew rate versus OPA337 15pF
(see Figure 5).

R1 R2
5kΩ 10kΩ Time (2µs/div)
VIN

Figure 5. G = 2, Slew-Rate Comparison of the

C1
OPA338 VOUT OPA338 and the OPA337
150pF

TYPICAL APPLICATION
1 See Figure 6 for the OPA2337 in a typical application. The
C2 = , C1 = (GH − 1) × C2
2πfCR2 ADS7822 is a 12-bit, micropower, sampling analog-to-
Where GH is the high−frequency gain, digital converter available in the tiny MSOP-8 package. As
GH = 1 + C1/C2 with the OPA2337, it operates with a supply voltage as low
as +2.7V. When used with the miniature SOT23-8 package
Figure 4. Inverting Compensation Circuit of the of the OPA2337, the circuit is ideal for space-limited and
OPA338 for Low Gain low-power applications. In addition, the OPA2337’s high
Resistors R1 and R2 are chosen to set the desired dc input impedance allows large value resistors to be used
signal gain. Then the value for C2 is determined as follows: which results in small physical capacitors, further reducing
circuit size. For further information, consult the ADS7822
C2 = 1/(2πfCR2) data sheet (SBAS062) located at [Link].

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V+ = +2.7V to 5V Passband 300Hz to 3kHz

R9
510kΩ
R1 R2 R4
1.5kΩ 1MΩ 20kΩ

C1 C3
R7 R8
51kΩ 150kΩ 33pF VREF 1 V+ 8
1000pF 1/2
OPA2337E DCLOCK
Electret R3 1/2 +IN 7 D
ADS7822 OUT Serial
Microphone(1) 1MΩ R6 OPA2337E
2 12−Bit A/D 6 Interface
100kΩ C2 1000pF CS/SHDN
−IN
5
3 GND 4

NOTE: (1) Electret microphone

R5
with internal transistor (FET) G = 100
20kΩ
powered by R1.

Figure 6. Low-Power, Single-Supply, Speech Bandpass Filtered Data Acquisition System

SOT23−5 SOT23−8
(Package Designator: D) (Package Designator: DCN)

0.075
0.027 (1.905)
(0.686)
(0.889)

(0.889)
0.035

0.035
(2.54)

(2.54)
0.10

0.10

0.0375 0.0375
(0.9525) (0.9525) 0.018 0.026
(0.457) (0.66)

For further information on solder

pads for surface−mount packages, consult Application Bulletin SBFA015A.

Figure 7. Recommended SOT23-5 and SOT23-8 Solder Footprints

10
 PACKAGE OPTION ADDENDUM

[Link] 14-Oct-2022

PACKAGING INFORMATION

Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)

OPA2337EA/250 ACTIVE SOT-23 DCN 8 250 RoHS & Green NIPDAU Level-2-260C-1 YEAR A7 Samples

OPA2337EA/3K ACTIVE SOT-23 DCN 8 3000 RoHS & Green NIPDAU Level-2-260C-1 YEAR A7 Samples

OPA2337PA ACTIVE PDIP P 8 50 RoHS & Green NIPDAU N / A for Pkg Type OPA2337PA Samples

OPA2337UA ACTIVE SOIC D 8 75 RoHS & Green NIPDAU Level-2-260C-1 YEAR OPA Samples
2337UA
OPA2337UA/2K5 ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 OPA Samples
2337UA
OPA2337UA/2K5G4 ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 OPA Samples
2337UA
OPA2338EA/250 ACTIVE SOT-23 DCN 8 250 RoHS & Green NIPDAU Level-1-260C-UNLIM A8 Samples

OPA2338EA/3K ACTIVE SOT-23 DCN 8 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 A8 Samples

OPA2338UA ACTIVE SOIC D 8 75 RoHS & Green NIPDAU Level-2-260C-1 YEAR OPA Samples
2338UA
OPA2338UA/2K5 ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 OPA Samples
2338UA
OPA337EA/250 ACTIVE VSSOP DGK 8 250 RoHS & Green Call TI | NIPDAUAG Level-2-260C-1 YEAR -40 to 85 G37 Samples

OPA337NA/250 ACTIVE SOT-23 DBV 5 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 C37 Samples

OPA337NA/250G4 ACTIVE SOT-23 DBV 5 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 C37 Samples

OPA337NA/3K ACTIVE SOT-23 DBV 5 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 C37 Samples

OPA337NA/3KG4 ACTIVE SOT-23 DBV 5 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 C37 Samples

OPA337UA ACTIVE SOIC D 8 75 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 OPA Samples
337UA
OPA337UA/2K5 ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 OPA Samples
337UA
OPA337UAG4 ACTIVE SOIC D 8 75 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 OPA Samples
337UA

Addendum-Page 1
 PACKAGE OPTION ADDENDUM

[Link] 14-Oct-2022

Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)

OPA338NA/250 ACTIVE SOT-23 DBV 5 250 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 A38 Samples

OPA338NA/3K ACTIVE SOT-23 DBV 5 3000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 A38 Samples

OPA338UA ACTIVE SOIC D 8 75 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 OPA Samples
338UA
OPA338UAG4 ACTIVE SOIC D 8 75 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 OPA Samples
338UA

(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.

(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.

(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

Addendum-Page 2
 PACKAGE OPTION ADDENDUM

[Link] 14-Oct-2022

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 3
 PACKAGE MATERIALS INFORMATION

[Link] 3-Jun-2022

TAPE AND REEL INFORMATION

REEL DIMENSIONS TAPE DIMENSIONS

K0 P1

B0 W
Reel
Diameter
Cavity A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
W Overall width of the carrier tape
P1 Pitch between successive cavity centers

Reel Width (W1)

QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE

Sprocket Holes

Q1 Q2 Q1 Q2

Q3 Q4 Q3 Q4 User Direction of Feed

Pocket Quadrants

*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
OPA2337EA/250 SOT-23 DCN 8 250 179.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3
OPA2337EA/3K SOT-23 DCN 8 3000 179.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3
OPA2337UA/2K5 SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
OPA2338EA/250 SOT-23 DCN 8 250 180.0 8.4 3.15 3.1 1.55 4.0 8.0 Q3
OPA2338EA/3K SOT-23 DCN 8 3000 180.0 8.4 3.15 3.1 1.55 4.0 8.0 Q3
OPA2338UA/2K5 SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
OPA337NA/250 SOT-23 DBV 5 250 178.0 9.0 3.3 3.2 1.4 4.0 8.0 Q3
OPA337NA/3K SOT-23 DBV 5 3000 179.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3
OPA337NA/3K SOT-23 DBV 5 3000 178.0 9.0 3.3 3.2 1.4 4.0 8.0 Q3
OPA337UA/2K5 SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
OPA338NA/250 SOT-23 DBV 5 250 178.0 8.4 3.3 3.2 1.4 4.0 8.0 Q3
OPA338NA/3K SOT-23 DBV 5 3000 178.0 8.4 3.3 3.2 1.4 4.0 8.0 Q3

Pack Materials-Page 1
 PACKAGE MATERIALS INFORMATION

[Link] 3-Jun-2022

TAPE AND REEL BOX DIMENSIONS

Width (mm)
H
W

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
OPA2337EA/250 SOT-23 DCN 8 250 213.0 191.0 35.0
OPA2337EA/3K SOT-23 DCN 8 3000 213.0 191.0 35.0
OPA2337UA/2K5 SOIC D 8 2500 356.0 356.0 35.0
OPA2338EA/250 SOT-23 DCN 8 250 210.0 185.0 35.0
OPA2338EA/3K SOT-23 DCN 8 3000 210.0 185.0 35.0
OPA2338UA/2K5 SOIC D 8 2500 356.0 356.0 35.0
OPA337NA/250 SOT-23 DBV 5 250 180.0 180.0 18.0
OPA337NA/3K SOT-23 DBV 5 3000 203.0 203.0 35.0
OPA337NA/3K SOT-23 DBV 5 3000 180.0 180.0 18.0
OPA337UA/2K5 SOIC D 8 2500 356.0 356.0 35.0
OPA338NA/250 SOT-23 DBV 5 250 565.0 140.0 75.0
OPA338NA/3K SOT-23 DBV 5 3000 565.0 140.0 75.0

Pack Materials-Page 2
 PACKAGE MATERIALS INFORMATION

[Link] 3-Jun-2022

TUBE

T - Tube
height L - Tube length

W - Tube
width

B - Alignment groove width

*All dimensions are nominal

Device Package Name Package Type Pins SPQ L (mm) W (mm) T (µm) B (mm)
OPA2337PA P PDIP 8 50 506 13.97 11230 4.32
OPA2337UA D SOIC 8 75 506.6 8 3940 4.32
OPA2338UA D SOIC 8 75 506.6 8 3940 4.32
OPA337UA D SOIC 8 75 506.6 8 3940 4.32
OPA337UAG4 D SOIC 8 75 506.6 8 3940 4.32
OPA338UA D SOIC 8 75 506.6 8 3940 4.32
OPA338UAG4 D SOIC 8 75 506.6 8 3940 4.32

Pack Materials-Page 3
 PACKAGE OUTLINE
DBV0005A SCALE 4.000
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR

C
3.0
2.6 0.1 C
1.75 1.45
B A
1.45 0.90
PIN 1
INDEX AREA

1 5

2X 0.95 (0.1)
3.05
2.75
1.9 1.9
2
(0.15)

4
3
0.5
5X
0.3
0.15
0.2 C A B NOTE 5 (1.1) TYP
0.00

0.25
GAGE PLANE 0.22
TYP
0.08

8
TYP 0.6
0 TYP SEATING PLANE
0.3

4214839/G 03/2023

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Refernce JEDEC MO-178.
4. Body dimensions do not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.25 mm per side.
5. Support pin may differ or may not be present.

[Link]
 EXAMPLE BOARD LAYOUT
DBV0005A SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR

PKG
5X (1.1)
1
5
5X (0.6)

SYMM
(1.9)
2
2X (0.95)

3 4

(R0.05) TYP (2.6)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN
SCALE:15X

SOLDER MASK
SOLDER MASK METAL METAL UNDER OPENING
OPENING SOLDER MASK

EXPOSED METAL EXPOSED METAL

0.07 MAX 0.07 MIN

ARROUND ARROUND

NON SOLDER MASK SOLDER MASK

DEFINED DEFINED
(PREFERRED)

SOLDER MASK DETAILS

4214839/G 03/2023

NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

[Link]
 EXAMPLE STENCIL DESIGN
DBV0005A SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR

PKG
5X (1.1)
1
5
5X (0.6)

SYMM
2 (1.9)
2X(0.95)

3 4

(R0.05) TYP
(2.6)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL
SCALE:15X

4214839/G 03/2023

NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.

[Link]
 PACKAGE OUTLINE
D0008A SCALE 2.800
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT

SEATING PLANE
.228-.244 TYP
[5.80-6.19]
.004 [0.1] C
A PIN 1 ID AREA
6X .050
[1.27]
8
1

.189-.197 2X
[4.81-5.00] .150
NOTE 3 [3.81]

4X (0 -15 )

4
5
8X .012-.020
B .150-.157 [0.31-0.51]
.069 MAX
[3.81-3.98] .010 [0.25] C A B [1.75]
NOTE 4

.005-.010 TYP
[0.13-0.25]

4X (0 -15 )

SEE DETAIL A
.010
[0.25]

.004-.010
0 -8 [0.11-0.25]
.016-.050
[0.41-1.27] DETAIL A
(.041) TYPICAL
[1.04]

4214825/C 02/2019

NOTES:

1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15] per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.

[Link]
 EXAMPLE BOARD LAYOUT
D0008A SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT

8X (.061 )
[1.55]
SYMM SEE
DETAILS
1
8

8X (.024)
[0.6] SYMM

(R.002 ) TYP
[0.05]
5
4
6X (.050 )
[1.27]
(.213)
[5.4]

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN
SCALE:8X

SOLDER MASK SOLDER MASK

METAL METAL UNDER
OPENING OPENING SOLDER MASK

EXPOSED
METAL EXPOSED
METAL
.0028 MAX .0028 MIN
[0.07] [0.07]
ALL AROUND ALL AROUND

NON SOLDER MASK SOLDER MASK

DEFINED DEFINED

SOLDER MASK DETAILS

4214825/C 02/2019

NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

[Link]
 EXAMPLE STENCIL DESIGN
D0008A SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT

8X (.061 )
[1.55] SYMM

1
8

8X (.024)
[0.6] SYMM

(R.002 ) TYP
5 [0.05]
4
6X (.050 )
[1.27]
(.213)
[5.4]

SOLDER PASTE EXAMPLE

BASED ON .005 INCH [0.125 MM] THICK STENCIL
SCALE:8X

4214825/C 02/2019

NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.

[Link]
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