CPU - ALU ( Arithmetic Logic Unit), Control Unit and links memory
CPU components:
- MBR ( Memory buffer register or MDR Memory Data Register): a temporary storage for actual
data being processed to memory. MDR is a data buffer that holds data as it is transferred
between CPU and memory. During a read operation, data is transferred from memory to the
MDR for the CPU to access. During the write operation, data that needs to be written will be first
stored in the MDR.
- Memory Address Register: A CPU register that hold the memory address of the data the CPU
wants to process. When the CPU wants to read/write data to/from memory, it loads the address
of those data into the MAR.
- Program Counter Register: stores the address of the next instructions to be executed
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The system bus:
- Collection of wires and electrical lines that facilitate communication between CPU memory and
I/O devices
- A single computer bus that connects the major part of a computer system
- Combines the function of (data, address, and control)
- A data highway, allow exchange of information between these components
- Address bus:
o Unidirectional pathway that carries memory address from the CPU to memory and IO
devices
o Specify the location in memory or the IO devices that the CPU wants to communicate
with
o An address bus decides where or which devices should the data be read or sent to.
- Control bus
o Consists of control lines that carry various control signals between the CPU, mem and IO
devices
o Those signals coordinate and synchronize the operations of the components involved
o Signals that are sent could be read/write signals, interrupt signals and control signals for
specific operations
o Carry signals that report the status of different devices like cpu or memory
- Data bus:
o Bi-directional pathway that carries data mainly between the CPU, mem and IO devices
o Conduit for transferring data such as instructions or information in binary form.
o A data bus can be either parallel or in series.
Von neu man architecture:
- Single storage system: Data and instructions are stored In the same memory
- The CPU executes 1 instructions at a time from memory
- 1 cycle at a time. During Fetch( Fetch only), …
- Includes a CU and ALU
- Instructions and data are stored in the same memory and they are distinguishing by their
address in the memory
- Single memory, instructions and data conflicts, hard to exploit caches and security vulnerabilities
Harvard architectures:
- Have separate memories for instructions and data.
- Fetch data and instructions concurrently
- Independent memory buses for instructions and data transfers
- Complexity and Cost due to multiple memories modules ( program instructions can not be
changed during runtime)
- Increased memory footprint, separate instruction and data caches
Pipelining:
- A CPU processes instructions by breaking down the instruction execution process into smaller
stages. Each stage is responsible for a specific operation such as Fetch, Decode, Execute and
Store. While 1 instruction is being executed in 1 stage, another instruction is being fetched in the
previous stage, and another instruction can be decoded in the stage before that.
- Dividing the Cycle: Divides the Fetch-Decode-Execute into smaller, independent stages.
- Instruction Overlap: This overlap allows multiple instructions to be in different stages of the
pipeline
- Continuous Processing: As instructions move through the pipeline, each stages operate
independently and continuously. The pipeline is kept busy with multiple instructions in different
stages
- Efficient uses of Resources
- Reduced Idle Time: Improved performance and faster overall execution
Superscalar:
- Multiple instructions are executed simultaneously per clock cycle by concurrently dispatching
them to different functional units. CPU manages multiple instructions pipeline.
- Multiple Execution Units: These units work independently and can process different types of
instructions concurrently.
- Instruction Dispatch and Scheduling
- Out-of-Order Execution
- Brach Prediction
