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KEC-072
Roll No.
B.Tech.
(SEM VII) SEMESTER THEORY EXAMINATION, 2022-23
VLSI DESIGN
Time: 3 Hours Maximum Marks:100
Note: Attempt all questions. All questions carry equal marks
Q.1. Attempt any four parts of the following 5X4
(a) Discuss the classification of CMOS logic families. Discuss the operation of pass transistor in
dynamic logic circuit.
(b) Draw Y Chart (VLSI design methodology) and explain MOS Scaling. CAD Tools for VLSI Design
in brief
(c) For an n channel MOS transistor with µ n = 60cm2µA/V-s, Cox = 7.10-8 F/cm2, W = 20µm, L=2µm
and VT0 = 1.0V. Examine the relationship between the drain current and the terminal voltages.
OR
(d) Draw a 4X1 Multiplexer using Transmission Gate (TG).
(e) Discuss the operation of CMOS 6T SRAM cell circuit.
OR
(f) Using AOI logic Implement the logic function Z=A +B C+CD
Q.2. Attempt any two parts of the following 10X2
(a) Consider a CMOS inverter circuits with the following parameters V DD = 3.3V, VTon = 0.6V, VTop=
-0.7V, kn = 200µA/V2, kp= 80µA/V2, kR = 2.5 Calculate the noise margin of the circuits.
(b) Consider a CMOS inverter, with the following device parameters, V DD = 3.V, VTon = 0.6V, VTop =
W
( )
-0.7V , µnCox = 60µA/V2, µpCox = 20µA/V2, λ= 0. Determine the L rations of the nMOS and
the pMOS transistors such that the switching threshold is Vth = 1.5V.
OR
(c) Design the circuit described by the Boolean function Y =( A+C )( B+C )( D+E ) using CMOS
logic. Calculate the equivalent CMOS inverter circuit for simultaneous switching of all inputs
assuming that
( WL )=10 for pMOS transistor and
( WL )=5 for all nMOS transistor.
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Q.3. Attempt any two parts of the following 10X2
(a) Explain the CMOS inverter switching characteristic using the digital model. Estimate the
propagation delay of a minimum size inverter driving a 100fF capacitor W p=Wn= 3µm Lp=Ln= 2µm.
Cox=800aF/µm2 Rn=12kΩ and Rp=36kΩ
(b) Estimate the intrinsic propagation delay t PHL+tPLH of a three-input NAND gate using minimum size
transistor (Rn=8kΩ, Rp=24kΩ and Coutn =4.8fF).Estimate the circuit delay also when the gate is
driving a load capacitance of 100fF.
OR
(c) Design a five stage ring oscillator with Wn =Wp=10µm. determine the oscillation frequency
Q.4. Attempt any two parts of the following 10X2
(a) (i) Discuss the operation of single stage shift register circuits
(ii) Design a D flip-flop using CMOS circuits.
(b) Discuss the Elmore Delay. In a CMOS inverter power supply V DD =5V, determine the fall
time, which is define as the time elapsed between the time point at which V out=V90% = 4.5V
and the time point at which V out=V10% =0.5. The output load capacitance is 1pF. The nMOS
2
transistor parameters are as follows: VTn = 1.0V, µnCox = 20µA/V ,
W
L n
=10 ( )
.
OR
(c) Elaborate how domino CMOS logic overcomes charge sharing problem. In a domino
CMOS circuits logic function Z is implemented with inputs (A,E,H) are high and other inputs are
low. Z=( A + B+C+ D )( E+ F +G ) ( H + I ) . Calculate equivalent CMOS inverter circuit
for simultaneous switching of all inputs assuming that (W/L)=20 for all pMOS transistor
and (W/L)=10 for all nMOS transistors.
Q. 5. Attempt any four parts of the following 5X4
(a) Classify various fault models. Define the terns Controllability and Observability.
(b) Explain the operation of DRAM cell with suitable CMOS circuits
(c) Explain the implementation of Built in Self Test (BIST) design techniques for VLSI
Circuits.
(d) Write short notes on Adiabatic CMOS logic. Design an adiabatic 2 input AND/NAND gate
(e) Explain the concept of low power MTCMOS VLSI design techniques.
(f) Draw a stick diagram of two input CMOS NAND logic gate.
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