Current

The total current in a semiconductor is the total of

Drift Current and Diffusion Current

J  JN  JP

dn
JN = JN,drift + JN,diff = qnn + qDN
dx

dp
JP = JP,drift + JP,diff = qnP  qDP
dx
 Einstein Relation

At Equilibrium (JN=0, JP=0), a gradient in carrier conc. will result

in electric field to balance the current flow

dn
JN = JN,drift + JN,diff = qnn + qDN =0
dx
The diffusion coefficient and mobility can have a relation as below:

dn qDN
qnn + qDN =0 qnn qn =0
dx kT
kT
Dn  n
dn
=
n dEc
=
n
q
q
dx kT dx kT
kT
Electric Field Dp  p
q
Generation & Recombination
The minority carrier lifetime (t) is the average time for the excess
minority carrier survives in majority carriers
n  n  n0
p  p  p0
Charge neutrality p  n (Excess Carrier due to external excitation: Light, Voltage….)

Usually, the semiconductor is in a “Low level injection”

p  n  n0 For n-type semiconductor
p  n  p0 For p-type semiconductor

In addition, the recombination is facilitated by the deep traps to

capture electrons and holes , considering the recombination in n-Si
Through traps NT
p  p
G R  C p NT p 
t tp
1
tp 
cpNT
 Continuity Equation
When a semiconductor is disturbed from equilibrium with excess
holes or electrons , it will relax back to equilibrium
dn n dp p
 
dt tn dt tp

Considering a carrier flux through a infinitesimal volume Adx

n 1 n
Adx   [ Jn (x)  Jn (x  dx)]A  Adx
t q tn

Jn (x)
Jn (x  dx)  Jn (x)  dx
Since x
J (x)
Jn (x  dx)  Jn (x)  n dx
x

n 1 J n ( x )  n
  G
t q x tn
Similar p 1 J p ( x )  p
  G
t q x tp
 Quasi-Fermi Level
At Equilibrium

EF  Ei
n  ni exp( ) EF N-type
kT
Ei  EF
p  ni exp( ) EF P-type
kT

At Non-Equilibrium, example is under illumination of light

FN  E i
n  ni exp( )
kT
Ei  FP
p  ni exp( )
kT
 Outline

 Junction
• PN Junction
• Metal-semiconductor Junction
• Heterojunction
 MOSFET
• MOS Cap
• MOSFET
• Basic Process Flow
 BJT
 Other Devices
• HEMT
• HBT
 P-N Junction
Depletion Layer (W)
P (dope Na) N (dope Nd)
Ec
EF

Ei qVb
EF Ev Fermi Level

Intrinsic Fermi Level

P-type N-type

qVb  (Ei  EF )P side  (EF  Ei )N side

NA
(Ei  EF )p  kT ln( )
Fermi level (Equilibrium Energy) ni
across materials is at the ND
same level (EF  Ei )N  kT ln( )
ni

NAND
qVb  kT ln( 2
)
ni
 The Depletion Approximation
Assuming a Step Junction
1D Poisson Equation
At Depletion Region,
P-side: ionized acceptor=> -qNA At p-side (-xp<x<0)
N-side: ionized donor=> qND
d qNA
=
dx  si
P N x qNA
∫ d = ∫ xp  Si
dx

-xp 0 xn qNA
= ( x + xp )
  si
ND At n-side (0<x<xn); similarly
d qND
NA =
dx  si
qND
= ( xn x)
E  si

NAxp  NDxn
 P-N Junction Depletion Width

At P-side At N-side
Vb
dV qNA dV qND
= = ( x + xp ) = = ( xn x)
dx  si dx  si
V(x) xqNA qND
 dV  
Vb xn

0  xp 
si
(x  x p )dx V(x)
dV  
x  si
(x n  x )dx

qNA qND
V (x )  ( x  x p )2 V (x )  Vb  ( x n  x )2
2 si 2 si
Since NA x p  ND x n
At x=0, the voltage of P-side and N-side are equal

qNA 2 qND
x p  Vb  ( x n )2
2 si 2 si
If NA>>ND, xn>>xp
2 si ( Vb ) ND
xp  ( )
q NA (NA  ND ) 2 si ( Vb ) 1 1 2si (Vb )
xn  xp  (  ) xn  xp 
q NA ND qND
2 si ( Vb ) NA
xn  ( )
q ND (NA  ND )
P-N Junction with Applied Voltage
P (dope NA) Depletion Layer (W) N (dope ND)
Ec

qVb
No Bias
Ev Fermi Level

Intrinsic Fermi Level

P (dope NA) Depletion Layer (W) N (dope ND)

Ec

q(Vb-VF)
Ev Fermi Level
Forward Bias
Intrinsic Fermi Level

P (dope NA) Depletion Layer (W) N (dope ND)

Ec

q(Vb+Vr)
Ev
Fermi Level
Reverse Bias
Intrinsic Fermi Level
 P-N Junction with Applied Voltage
Forward Reverse Forward
Reverse E
ND
P N
NA

0
-xp xn

2 si (Vb  VA ) ND
xp  ( )
q NA (NA  ND )
2 si (Vb  VA ) 1 1
W  xn  xp  (  )
q NA ND
2 si (Vb  VA ) NA
xn  ( )
q ND (NA  ND )
 Depletion width increase at reverse bias, decrease at forward bias

 If NA>>ND XP~0 2 si (Vb  VA ) 1

W  xn  ( )
q ND
 If ND>>NA Xn~0 2 si ( Vb  VA ) 1
W  xp  ( )
q NA
Electric Field of P-N Junction w/i Bias
P (dope NA) Depletion Layer (W) N (dope ND)
Ec

q(Vb+Vr) (-Vr is reverse bias)

Ev
Fermi Level

Intrinsic Fermi Level

Approximation using One-side dominated Junction; Example: NA>>ND, xn>>xp

1
xn
x ∫ dx = (0) W = Vb
2
VA

2 si ( Vb  VA )
W  xn  xp 
qN
E
2( Vb VA ) 2qN( Vb VA )
( 0 ) = =
W  Si

(VA positive forward, VA negative reverse)

 Breakdown of P-N Junction
Avalanche Breakdown Zener Breakdown
P (dope NA) N (dope ND) P (dope NA) N (dope ND)
Ec Ec

Depletion Layer (W) q(Vb+Vr) Depletion Layer (W) q(Vb+Vr)

Ev Ev
Fermi Level Fermi Level

Intrinsic Fermi Level Intrinsic Fermi Level

2qNVbr  Si Crit

2
(assume │Vbr│ >> │ Vb │)
 crit = Vbr =
 Si 2qN

 Avalanche Breakdown: High field induced impact ionization

 Zener Breakdown: Direct tunneling, this could happen when both N,P sides
are heavily doped
 For the same material, Breakdown voltage decrease with increase of N
 Materials with smaller bandgap has lower breakdown voltage
Reverse Current of P-N Junction

P (dope NA) N (dope ND)

Ec
Depletion Layer (W)

q(Vb+Vr)
Ev
Fermi Level

Intrinsic Fermi Level

At reverse bias condition, generation of carrier that could happen

at the edge of depletion layer. The generated carrier can move out of
depletion region due to bias.
 I-V of P-N Junction

 When a PN junction is in forward bias,

the potential barrier is reduced
 More minority carriers are injected in P (dope NA) Depletion Layer (L) N (dope ND)
Ec
the depletion region (n,p >0) result q(Vb-VA)
in diffusion current and recombination
Ev Fermi Level
with majority carrier
Intrinsic Fermi Level
KEY Concept: PN Junction Current is formed by
Minority Carrier Diffusion Current. It will derived
in subsequent page
I
J  JN  JP Dominate

dn d(n)
JN  JN,drift  JN,diff  qnnE  qDN  qnnE  qDN
dx dx
V
dp d(p)
JP  JP,drift  JP,diff  qp PE  qDP  qpPE  qDP
dx dx
 I-V of P-N Junction
Derivation of Excess Carrier n,p
P (dope NA) Depletion Layer N (dope ND) Carrier Concentration under Bias VA
Ec
(FN  Ei )
q(Vb-VA) n  ni exp( )
kT
Ev Fermi Level (E  F )
p  ni exp( i P )
Intrinsic Fermi Level kT
(FN  FP ) qV
np  ni exp( )  ni exp( A )
2 2
0
-xp xn kT kT

Excess Minority Carrier Concentration

p(x p )  NA n(xn )  ND
2 qVA 2 qVA
ni exp( ) ni exp( )
kT (Under Bias) p(x n )  kT
n(x p ) 
NA ND
2 2
n (No Bias) n
n(x p )  i p(xn )  i
NA ND
2 2
n qV n qV
n( xp )  i (exp( A )  1) Excess Carrier p(xn )  i (exp( A )  1)
NA kT ND kT
 I-V of P-N Junction
For x to the LEFT of xp For x to the RIGHT of xn
P-Type Depletion N-Type dp
Region JN  qnnE  qDN
dn
0 Jp  qp pE  qDp 0
dx dx
d(n  np ) dnp d(p  pN ) dpN
JN  qDN  qDN Jp  qDp  qDp
-xp xn dx dx dx dx

From the continuity equation, at steady state

At P-Type Side At N-Type Side

n 1 JN (x ) np p 1 Jp (x ) p

   
 t q x tN t q x tp
d2 np np d2 pN pN
DN  0 DP  0
dx 2 tN dx 2 tP

d2np np np d2pN pN pN

  LN  DNtN   2 LP  DPtP
dx 2 DNtn L2N dx 2 DPtP LP

np (x)  Ae  x / L  Be x / L
N N
General Solution pN (x)  Ae  x / L  Be x / L
P P
 I-V of P-N Junction

P-Type Depletion N-Type

Region

Change the
Coordinate X” Xp=0 Xn=0 X’
From the continuity Equation, at steady state

At N-Type Side pN (x' )  Ae x'/ LP  Bex'/ LP

p N ( x '    )  0
Boundary Conditions are: ni2 qV
 p N ( x '  0)  (exp( A )  1)
ND kT
ni2 qV
Therefore, B=0 A (exp( A )  1)
ND kT

ni2 qV  x'
pN (x' )  (exp( A )  1) exp( )
ND kT LP

Similar ni2 qV  x"

nP (x" )  (exp( A )  1) exp( )
NA kT LN
 I-V of P-N Junction

P-Type Depletion N-Type

Region

xp xn
dnP (x" ) DNni2 qV  x'
At p-side JN  qDN q (exp( A )  1) exp( )
dx " NALN kT LN

dpN (x' ) DPni2 qV  x'

At n-side JP  qDP q (exp( A )  1) exp( )
dx ' NDLP kT LP

At the edge of depletion regions, x’=x”=0, For the current under bias VA

DNni2 DPni2 qV
JN  JP  (q q )(exp( A )  1)
NALN NDLP kT

• PN Junction Current is formed by Minority Carrier Diffusion Current.

• Concentration gradient (n,p ) is more noticeable compared with minority
carrier than the majority carrier due to the difference in its base-amount.
• No electric field outside depletion region.
 Metal-Semiconductor Junction
Vacuum
E0

 • E0 is the energy of free electron in

FM FS vacuum
EC • Energy difference between vacuum and
EF Fermi level is called WORKFUNCTION (F)
Ei
• Energy required to remove an electron
EF from metal is the WORKFUNCTION of
EV metal (FM)

Metal
Semiconductor
 Metal-Semiconductor Junction
1D Poisson Equation
d qND
= (E: electric field)
E0 dx  si

FM  FS qNA
EC = (x W)
EF  si
Ei
EF
EV V(x ) = ∫ (x)dx
Metal
Semiconductor  qND
V (x )  ( W  x )2
2 si
q(Vb-VA)
FB At X=0, V(0)= -(Vb-VA)

2 si ( Vb  VA )
W
X qND
0 W
 Metal-Semiconductor Junction

EV Bandgap of Si EC

List of metal Workfunction

(Materials Science and Engineering R 88 (2015) 1–41)

 Hetero-Junction
Material 1 Material 2 Material 1 Material 2

E0 E0 Vacuum E0

1 1 2 2
Ec
Ec Ec
Ec
EF EF
EF
Ev Ev
Ev Ev

 At equilibrium, the Fermi Level of material 1 and 2 are aligned

 There are discontinuity at interface, a spike at conduction band.

 Hetero-Junction
Vacuum Vacuum
Vacuum
E0 E0 E0 E0 E0 E0

1 1 2 2 1 1 2 2 1 1 2 2

Ec Ec Ec
Ec
Eg Eg Eg Eg
Ec
Ev
Ev Ev Eg Ev Ec
Ev Eg
Ev
Type I Straddle Type II Stagger Type III Broken

Small Eg within One edge small Eg within Small Eg outside

Bandgap of large Eg Bandgap of large Eg Bandgap of large Eg
 Outline

 Junction
• PN Junction
• Metal-semiconductor Junction
• Heterojunction
 MOSFET
• MOS Cap
• MOSFET
• Basic Process Flow
 BJT
 Other Devices
• HEMT
• HBT
 MOSFET: MOS Gate
E0
• Example of a NFET (p-type channel doping)
FM  FS
EC (C-V) of Gate
Ei
EF EF
EV

Semiconductor
Assume M=S Metal

F

Ei Ei
EF s
EF
Ei Ei
EF EF
F = Ei-EF
s (bending of Ei)=2F

VG=0
Qinv=Cox(VG-VT)
VG<0 0<VG<VT
Flat Band Accumulation Inversion VT<VG
Strong Inversion (see next page)

• Gate Voltage modulate the charges in channel

• Capacitance-Voltage (C-V) test is used to characterize the charge modulation 26
 Band at Equilibrium (w. Flat-band voltage)
P-type Si (N channel) Typically, FMFS

At Equilibrium
Flat Band Condition
E0

FM Si F
EC S

EC
Ei Ei
EF qFF EF
EF qFF EF
EV
EV

Semiconductor Semiconductor
Metal Metal

N-Si
kT N D Apply Flat Band Voltage
EF - Ei = ln( ) = F
q ni (VFB)= FMS= FM -Fs
Remember: P-Si (Ideally, a negative voltage)
kT n
Ei - EF =
q
ln( i ) = F
NA
 S   Si  ( EC  E F )
 Threshold Voltage (w/ Flat Band Voltage)
P-type Si (N channel) At Strong Inversion
kT N A
qVOX S = 2F = 2(E i - E F ) = 2 ln( )
q ni
W
2 s ( 2F )
W=
EC qN A
Ei
qF EF Q d = qN A Wd = 2s SqN A = 2s ( 2F )qN A
s=2F EV
Qd
VG = VFB + S + VOX = VFB + S +
qS qVG Cox
2 s SqN A (Cox= Ci (i: insulator)
= VFB + S + Vox= Vi
COX in some pages)

2 s ( 2F )qN A p-Si

At Threshold Condition (VG=VT) VT = VFB + 2F +
COX
S=2B, meaning that surface
charge(n) = NA 2 s ( 2F )qN D
VT = VFB + 2F - n-Si
COX
FET starts to Turn-on at VT
 Interface and Oxide (Real)

Ci=Cox:gate oxide capacitance (i: insulator)

Textbook: Solid State
Electronic Devices CH.6 Qi is interface charges including
(Ben Streetman, 7ed.) Fixed, interface traps..etc.)
 Threshold Voltage

Capacitance of
Ideally, V FB  ms gate insulator (oxide)
Ci ; also call Cox
Qi
In reality V FB  ms 
Ci
Qi Qd
So V T   ms    2 F
Ci Ci

Adjustment of Threshold Voltage

• Gate Electrode (Metal)
• Control Ci thickness
• Channel Doping
Textbook: Solid State
Electronic Devices CH.6
(Ben Streetman, 7ed.)
 MOSFET
Relation of IDS with VDS, at Constant VG
G G

Oxide Oxide
Inversion Inversion D
S Inversion D S
Depletion Depletion

G G
Oxide Oxide
Inversion D Inversion D
S S
Depletion Depletion
 MOSFET
MOS Capacitor MOS FET
G G

Oxide Oxide
Inversion
Inversion Inversion D
S
Depletion Depletion

y
Qinv  Cox (V GS  VT ) Qinv  Cox (V GS  VT  VC (y))

For VGS > VT

 For a MOSFET, the Channel potential varies with respective to position

due to the drain to source voltage.

 For MOSFET, it can be assumed that the charge in semiconductor is a

linear function of location (y) along the gate from Drain to Source
 MOSFET I-V Characteristics
Qinv  Cox ( V GS  VT  VC )
Non-Saturate Saturation
VDS (Sat)=VGS-Vt

IDSdy I dy
dVC  IDSdR    DS
nq eff Wt inv Q inv eff W

L VDS
0
IDSdy   
0
 eff WQ inv ( VC )dVC

W VDS
IDS    eff  Qinv ( VC )dVC
L 0

Non-saturate Region
W eff COX 2
VDS
IDS  [(VGS  Vt ) VDS  ]
L 2 For VDS< VDS (Sat)

WCOX At saturate Region

IDS  (VGS  Vt )2
2L For VDS> VDS (Sat)=(VGS-Vt)
 N/P MOS
NMOS PMOS

Gate Gate
Gate Oxide Gate Oxide

P-Si N-Si

To Turn on Channel, VGS> VT>0 To Turn on Channel, VGS< VT<0

VGS=-0.7V

VGS=-0.6V
 Junctions in MOSFET

Gate
Gate Oxide
N- N-
N+ N+

APT
Punchthrough

P-type

PN junctions in CMOS technology to confine the current path

 Structure of CMOS

NMOS PMOS

HM
Contact ILD0
MG MG
Silicide HK
N P
STI
P-Well N-Well
 Advanced Planar CMOS Flow

STI Poly+Hardmask dep

Shallow Trench Etch /Pattern/Etch
P-Well N-Well

Light dope drain (LDD)

Oxide fill & CMP STI implant
P-Well N-Well

Spacer Formation
STI Oxide Dep STI (Dep + Etch)
P-Well N-Well

STI Well Implant S/D and Pocket

STI Implant
(Multiple steps
P-Well N-Well For anti-punch through)
P-Well N-Well

37
 Advanced Planar CMOS Flow

HK/MG
S/D Epitaxy HK/MG Fill
Epi

P-Well N-Well P-Well N-Well

Silicide

Epi Silicide Dep HM

RTA
P-Well N-Well Selective Etch P-Well N-Well

SiN ILD0
Contact Etch
SiN + ILD0 Oxide

P-Well N-Well P-Well N-Well

Poly removal Contact Metal Fill

P-Well N-Well P-Well N-Well

38
 Outline

 Junction
• PN Junction
• Metal-semiconductor Junction
• Heterojunction
 MOSFET
• MOS Cap
• MOSFET
• Basic Process Flow
 BJT
 Other Devices
• HEMT
• HBT
 DC Parameters of BJT
Gummel Plot
Ic Increase IB

VCE
([Link]
NPN BJT
qVBE
Ic  Is [exp( )  1] (Is: Saturation Current)
kT
Ic  IB (Current Gain)

I I
IE  IC  IB  (IC  C )  C
 
I q qV qI
Gm  ( C )  IS exp( BE ) ~ C
VBE kT kT kT
 Outline

 Junction
• PN Junction
• Metal-semiconductor Junction
• Heterojunction
 MOSFET
• MOS Cap
• MOSFET
• Basic Process Flow
 BJT
 Other Devices
• GaN HEMT
• HBT
 GaN on Si HEMT

AlGaN

Vg1 > Vg2

Off-State
Gate Vg2

Source Drain AlGaN

AlGaN GaN
GaNchannel
AlGaN Barrier

GaN Channel
Interlayer (GaN or AlGaN, [C] doped On-State
Buffer Layer Vg1
AlN Nucleation Layer e-e-
e-
Si (111) GaN channel
AlGaN
 D-mode v.s E-mode
D-mode: “Depletion Mode (Normally-on) device, Vt is negative
E-mode: “Enhancement Mode (Normally-off) device, Vt is positive

Example:

(source: Panasonic)
 RF- SiGe HBT
 SiGe Base (~15-20% Ge) for good
current gain
 Integrated with CMOS for BiCMOS
Emitter technology
 High frequency operation near
N+ Spacer
Base Poly advanced CMOS with less nano-pattern
Selective Collector
P+ P-SiGe 20~30n P+ Epi

N- Si
STI STI

Oxide Si
N+ SiGe

P
 HBT
RF- GaAs/InGaP HBT

 Major power amplifier technology for Cellular phone; good yield and performance
 N+InGaAs at emitter for low contact resistance
 InGaP emitter for good current gain

Emitter
AuGe/Ni/Au
N+ InGaAs
Base N GaAs Base
Pt/Ti/Au N InGaP emiiter~ 50n
P+ GaAs~ 70n
AuGe/Ni/Au
N- GaAs (Sub-collector) Collector

N+ GaAs

S.I. GaAs