03-02-2024

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Micro Processor
Unit 3

Global Descriptor Table & GDTR

• The GDT is used to implement memory protection and virtual memory.
• The GDT contains descriptors of Global Segments.
• The segments which are available to all the tasks in the system are
called global segments.
• GDT can contain any type of descriptor (user, system, LDT, TSS)
except interrupt and exception descriptors.
• The max size of the GDT can be 64 KB.

• The size of GDT is always Limit + 1

• GDTR is a 48 bit register. It defines the GDT in the

Physical Memory.
• The upper 4 bytes (32 bits) give the starting address of
the GDT also called the base address.
• The lower 2 bytes give the 16-bit Limit which decides
the size of the GDT.

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Interrupt Descriptor Table & IDTR

• The IDT contains Interrupt Descriptors..
• Each Interrupt descriptor is 8 bytes in size.
• It gives the Starting Address, Limit and Access Rights of the segment.
• These Descriptors direct the µP towards the respective ISR
whenever an interrupt occurs. Hence the Descriptors are also
called “Interrupt Gates”.

• 80386 µP supports 256 interrupts.

• Hence max size of the IDT is 256 x 8 = 2KB.
• Minimum size of IDT is 256 bytes to hold the descriptors for the
32 intel reserved interrupts
• The size of IDT is Limit + 1. Hence max value of Limit must be 07FFH
• IDTR is a 48 bit register. It defines the IDT in the Physical Memory.
• The upper 4 bytes (32 bits) give the starting address of the IDT also called the
base address.
• The lower 2 bytes give the 16-bit Limit which decides the size of the IDT.

Local Descriptor Table & LDTR

• LDTR is a 16 bit register.
• It contains a selector, which
points to the LDT Descriptor in
the GDT.
• Every task in 80386 µP has a
local memory space. Here it has
its local segments, which are
only available to that particular
task.
• The descriptors of all the
local segments are present
in the LDT of that task.
• There is an individual
LDT for each task.
• The Descriptor for the
LDT itself is present in
the GDT.
• The LDT Descriptor is of
8 bytes.

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• The structure of LDT is

similar to that of GDT. It also
has max 8k Descriptors each
of size 8 Bytes and hence
max size of LDT is also
64KB.

Instruction

Address Virtual Address (logical add) Selector(16) Offset(32)

Translation
Segmentation Translation

Linear Address [] DIR(10) TABLE(10) Offset(12)

Page Translation(Optional)

Physical Address[32bit]
Logical address is a 48 bit address which contain a 16 bit selector
and a 32bit offset address. The 16 bits are given by the segment
register and 32bit offset is given in the instruction, register or
memory location.
Linear Address is a 32bit address, which acts as the physical
address if paging is not enabled. If paging is enabled the Linear
address is broken in three parts page directory index(10bit), Page
table index(10bit) and Offset in the page selected (12bit)
Physical Address is the real address of data present in the
memory.

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Address Translation Mechanism

• Though the selector is of 16-bits,
only 14 bits are used as two bits
give the Privilege Level used for
protection as seen above. Each
selector value corresponds to a
different segment. Hence there can
be max 214 segments.
• Since offset addresses are 32 bit,
each segment can be max 232 =
4GB. Hence the max total Virtual
memory that can be accessed = 214
x 232 = 246 =64 Terra Bytes.
• Out of 14 bits of the selector, one
bit is used as a table identifier (TI)
if TI = 1 then use LDT, if TI = 0
then use GDT
• The total 48 bit address(16 bit
segment add+ 32 bit offset add) is
called Virtual address. It is
converted into a 32 bit physical
address using two translations:
Segment translation (compulsory)
and page translation (optional).
13 Bit selector TI RPL 32 bit Offset Address

Segmentation
(Segment Translation)

• The Virtual Address is given by a Segment Register (16) and an Offset

Register (32).
• The segment register is also called as selector. Out of these 16 bits 2 bits
are used to store the privilege level of segment.
• The remaining 14 bits give a 13 bit index (selector) which leads to a
descriptor in LDT or in GDT, depending upon the TI bit. If TI = 1 the
LDT, if TI = 0 then GDT.

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Segmentation (Segment Translation)

13 Bit selector TI RPL 32 bit Offset Address

• Using the specified index the descriptor is

accessed from LDT of GDT.
• This Descriptor is copied into an on chip
Segment Descriptor Cache. It is of 8 bytes.

There is a bit “P” in the Descriptor.

If P = 0, the Segment is Not Present in the Physical Memory
If P = 1, the Segment is Present in the Physical Memory.
Then the base address (starting address) of the segment is available in the
Descriptor.
To this base address, the 32-bit offset address is added.
This finally gives the 32 bit Linear Address of the desired location.
Before granting access to the desired location, a protection check is performed
based on the information given by the access rights in the Descriptor.
If the checks are valid then access is granted, else a general protection fault occurs.
If Paging is not implemented, then the 32 bit linear address is the final 32 bit
Physical Address

Segment Descriptor

Sube Daar 8Bytes

Segment Descriptor
Base Address
Limit
Access Bits

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Format of Segment Descriptor

Each segment descriptor is 8 bytes in size.

It gives the Starting Address, Limit and Access Rights of the segment.
S=0: system descriptor; if S=1: non-system descriptor

• P(Present bit):
• if P=0 the segment is not present in the physical memory.
• If P=1 the segment is present in the physical memory.
• DPL(Descriptor Privilege bits):
• These two bits the privilege level of the segment.
• S(System Descriptor)
• if S=0 it’s a System Descriptor 1
• If S=1 it’s a user (Code or Data) segment
• TYPE (Type of Segment): 3 bits tells the type of segment if it’s a
non system segment it can be data, code or stack. If it’s a
system segment it can be TSS, call, task, trap or interrupt gate.
• A Accessed Bit
• If A=1 the segment was recently accessed.
• If A=0 the segment is not accessed for a long time.
• G Granularity Bit
• If G=1 the segment is page granular i.e. size= limit *4kB
• If G=0 the segment is byte granular i.e. size= limit.
• D Default Operation Size (for code segments only)
• If D=1 the segment is a 32 bit segment(80386).
• If D=0 the segment is a 16 bit segment(8086).
• AVL: Available to the programmer

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Type bits (not in the syllabus of

this unit)
E=0 ED=1=Stack Segment(SS) W=0 read only
ED=0=Data Segment(DS,ES,FS,GS) W=1 write enabled
E=1=Code segment C=0 non conforming code seg. R=0 only execute is
C=1 conforming code segment allowed
(no privilege check) R=1 Read and
execute are allowed

Page Translation(Paging)

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Page Translation
• The Virtual Memory space is divided into equal
size blocks of 4KB called “Pages”
• The Physical Memory space (also called Main
Memory) is also divided into equal size blocks of 4
KB called Page Frames (also simply called pages).
• As Physical Memory is of 4 GB and page size is 4
KB there are total 1 M pages (220) in the Physical
Memory.
• A page from Virtual Memory is loaded into any
available page frame of Physical Memory

• Whenever a page is required to be accessed, the µP first

checks if the desired page is present in the Physical
Memory.
• If it’s present the operation is performed on the Physical
Memory.
• It it’s not present in the Physical Memory, a “Page
Fault” occurs.
• On a Page Fault the desired page is loaded form Virtual
Memory into any available page frame of Physical
Memory.
• If no page frame is available, then a “Page
Replacement” is performed by replacing an old page
from the Physical Memory with the new desired page
from the Virtual Memory.
• Since a page of Virtual Memory can be loaded into any
page frame of Physical Memory, a “Page Table” is
required to give the mapping between Virtual Memory
page number and Physical Memory page frame number.
• Page table tells which page of Virtual Memory is
present in which page of Physical Memory

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Page Translation

• Once the page to be replaced is decided, a “Dirty Bit” is checked to determine if the page
is modified in the Physical Memory.
• If Dirty bit = 1, then the page has been modified and hence must be copied back into
Virtual Memory before being replaced else the modified information will be lost.
• Page table tells which page of Virtual Memory is present in which page of Physical
Memory
• But since there are too many page frames in the Physical Memory (2 20 i.e. 1M), the page
table will become too large and searches will become extremely slow.
• Instead of having straight 1M (220) entries in the page table, there are 1K (210) entries in a
page table and there are 1K (210) such page tables.
• Each page table is of 4KB and has 1K “Page Table Entries” (PTEs) each of size 4
bytes. Each PTE gives information about a Page Frame.
• The PTE has following information:
• 20 bit page frame address: Gives the upper 20 bits of the starting address of the page frame. Lower
12 bits are 0.
• D: Dirty bit indicates whether the page has been modified (1) or not (0).
• A: Accessed Bit tells whether the page has been accessed or not (1 means accessed). This is used by
replacement algorithms.
• U/S: (User or Supervisor) and R/W: (Read or Write) give protection information.
• P: Present bit indicates whether the page is present in the Physical Memory

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• Information about all the page tables is stored in the “Page Directory”.
• The page directory is of 4KB and has 1K “Page Directory Entries” (PDEs) each
of size 4 bytes. Each PDE gives information about a Page Table.
• The PDE has following information:
• 20 bit page frame address: Gives the upper 20 bits of the starting address of the
corresponding page table. Lower 12 bits are 0.
• D: Dirty bit indicates whether the page has been modified (1) or not (0).
• A: Accessed Bit tells whether the page has been accessed or not (1 means accessed). This is
used by replacement algorithms.
• U/S: (User or Supervisor) and R/W: (Read or Write) give protection information.
• P: Present bit indicates whether the page is present in the Physical Memory
• The Page Directory is of 4 KB and begins from a 4 KB aligned location.
• The address of the page directory is given by the PGBR (page Directory Base
Register) field in CR3.

The 32 bit Linear Address can be divided into three parts.

The higher 10 bits select one PDE out of 1K PDEs in the page directory.
This gives the starting address in the page table.
The next 10 bits select one PTE out of 1K PTEs in the page table.
This gives the starting address of the page frame.
Finally, the lowest 12 bits (offset) select a location within the 4KB page.

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Translational
Lookaside Buffer

• To access any location, µP must first access a PDE in the page

directory then a PTE in the page table, then access the page. This
can make the process very slow.
• To speed up the process a “Translation Look-aside Buffer” is used
(called TLB).
• The TLB is an on chip cache which stores 32 most recently used
PTEs and PDEs. This makes subsequent access to these pages
(whose information is cached in the TLB) much faster as there is
no need to access the Page directory and the page table.
• µP can directly obtain the starting address of the page frame from
the TLB and hence directly access the page.
• Due to principle of “Locality of reference” most systems get a Hit
ratio of >98% on the TLB, thus making the operations very fast.

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Pyq
• Adress translation
• Segment descriptor
• Format of selector
• Paging mechanism , linear to physical
• GDTR,LDTR,IDTR

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