The Intel 8085/8085AH is a microprocessor, i.e.

, an 8-bit parallel central processing unit implemented in sili-

con gate NMOS/HMOS/C-MOS technology. It is available in a 40-pin IC package fabricated on a single LSI
chip. It is designed with higher processing speed, ranging from 3 MHz to 5 MHz Lower power consumption
and power-down mode is provided, thereby offering a high level of system integration. This processor uses
a multiplexed address/data bus. The address bus is split between the 8-bit address bus and the 8-bit data bus.
The on-chip address latch allows a direct interface with the processor. The features of 8085 microprocessors
are given below:

Power-down mode (HALT-HOLD)

Low power dissipation: about 50 mW
Single +3 to +6 V power supply
Operating temperature from –40 to + 85°C
On-chip clock generator incorporating external crystal oscillators
On-chip system controller
Four-vectored interrupt including one non-maskable
Serial input/Serial output port
Addressing capability to 64K bytes of memory
TTL compatible
Available in 40-pin plastic DIP package

The functional block diagram of Intel 8085 is depicted in Fig. 2.1. It consists of three main sections: an arith-
metic and logic unit, timing and control unit and a set of registers. These important sections are described in
the subsequent pages.
 RST
SID SOD
INTR INTA 5.5 6.5 7.5 TRAP

Interrupt Control Serial I/O Control

8-Bit Internal Data Bus

Temporary Flag Instruction

Accumulator Register Flip-Flops Register

B REG C REG
Arithmetic
Logic Unit D REG E REG
(ALU) Instruction
Decoder
H REG L REG
Register
Stack Pointer Array

Program Counter
Incrementer/Decrementer
Address Latch

Power Down Timing and Control

X1 Clock
Control Status DMA Reset Data/Address
X2 Generator Address Buffer
Buffer

CLK READY RD WR ALE S0 S1 IO/M HOLD HLDA RESET IN RESET OUT A 15–A 8 AD 7–AD 0
OUT
Address Bus Address/Data Bus
Generally, a microprocessor performs four different operations: memory read, memory write, input/output
read and input/output write. In the memory read operation, data will be read from memory and in the memory
write operation, data will be written in the memory. Data input from input devices are I/O read and data out-
put to output devices are I/O write operations.
The memory read/write and Input/Output read and write operations are performed as part of communica-
tion between the microprocessor and memory or Input/Output devices. Microprocessors communicate with
the memory, and I/O devices through address bus, data bus and control bus as depicted in Fig. 2.2. For this
communication, firstly the microprocessor identifies the peripheral devices by proper addressing. Then it
sends data and provides control signal for synchronization.

Control Bus

Address Bus

Data
8085 output
Output Input
Memory
Microprocessor Device Device
Data
Input

Data Bus

Figure 2.3 shows the memory read operation. Initially, the microprocessor places a 16-bit address on
the address bus. Then the external decoder logic circuit decodes the 16-bit address on the address bus and
the memory location is identified. Thereafter, the microprocessor sends MEMR control signal which enables
the memory IC. After that, the content of the memory location is placed on the data bus and also sent to the
microprocessor. Figure 2.4 shows the data flow diagram for data transfer from the memory to microprocessor.
The step-by-step procedure of data flow is given below:
The 16-bit memory address is stored in the program counter. Therefore, the program counter sends
the 16-bit address on the address bus. The memory address decoder is decoded and identifies the
specified memory location.
The control unit sends the control signal RD in the next clock cycle and the memory IC is enabled.
RD is active for two clock periods.
When the memory IC is enabled, the byte from the memory location is placed on the data bus AD7–
AD0. After that data is transferred to the microprocessor.
 D7–D0
Data Bus

Data 1
Data 2
8085 Data 3
Microprocessor

Memory Decoder
Memory
A15–A0 Address Bus IC
16-bit
Memory
Address

MEMR
Memory Read

Data Bus

Internal Data Bus

Data 1
B C Data 2
Data 3
Memory Decoder

D E
Instruction
ALU
Decoder
H L

Stock
Pointer

Program
Counter

Control
Signal

Address Bus

RD
All arithmetic and logical operations are performed in the Arithmetic Logic Unit (ALU). The functioning of
the ALU is given in Fig. 2.5. The ALU functioning consists of Accumulator (A), Temporary Register (TR),
Flag Register (FR) and arithmetic logic unit. The temporary register is not accessible to the user. Therefore,
the user cannot read the content of TR. Actually, this register is used to store or load the operand during

Internal Data Bus

Temporary Flag Flip-Flops

Accumulator
Register

Arithmetic
Logic
Unit

arithmetic and logical operations. Accumulator, TR and flag register are explained in Section 2 2.5 in detail.
The ALU always operates with one or two operands. Generally, operands are available in general-purpose
registers or memory locations. The results after arithmetic and logical operations are stored in the accumula-
tor. The sequence of operations in ALU are given below:
(i) One operand is in the A register.
(ii) The other operand may be in the general-purpose register or memory location, which will be trans-
ferred to the temporary register.
(iii) Then contents of the accumulator and temporary registers are considered as inputs of ALU and the
specified operation is carried out in the ALU.
(iv) The result of ALU operation is transferred in the A register through internal data bus.
(v) The content of the flag register will be changed depending on the result.
The arithmetic logic unit (ALU) performs the following operations:
Addition
Subtraction
Logical AND
Logical OR
Logical EXCLUSIVE OR
Complement
Increment by 1
Decrement by 1
Rotate Left, Rotate Right
Clear
The control unit controls the operations of different units while the CPU generates timing sequence signals
for the execution of instructions. This unit controls the data flow between CPU and memory and CPU and
peripheral devices. This unit provides control, status, DMA and reset signals to perform any memory and
input–output related operations. Actually, it controls the entire operation of microprocessors. Therefore, the
timing and control unit acts as the brain of the microprocessor.

The Intel 8085 has six general-purpose registers to store 8-bit data and these registers are identified as B, C,
D, E, H and L. When two registers are combined, 16-bit data can be stored in a register pair. The only possible
combinations of register pairs are BC, DE and HL. These register pairs are used to perform 16-bit opera-
tions. There is an accumulator register and one flag register. The accumulator is an 8-bit register. Arithmetic
and logical operations are performed in the accumulator and after operation, the result will be stored in the
accumulator. In addition with the above registers, there are two 16-bit registers, namely, the Stack Pointer
(SP) and Program Counter (PC).

One 8-bit accumulator (ACC) known as register A

Six 8-bit general-purpose registers: B, C, D, E, H and L
One 16-bit Stack Pointer (SP)
One 16-bit Program Counter (PC)
Instruction register
Temporary register
Program Status Word (PSW) Register

The accumulator is an 8-bit register, which is part of the Arithmetic Logic Unit
(ALU). This is identified as register A or ACC. It is used to store 8-bit data and to perform arithmetic as well
as logic operations. The final result of an operation performed in the ALU is also stored in the accumulator.

The general-purpose registers of the 8085 microprocessor are B,

C, D, E, H and L registers as shown in Fig. 2.6. These
registers are used to store 8-bit operands. To hold a 16- B C
bit data or 16-bit memory address location, two 8-bit General-Purpose
registers can be combined. The combination of two 8-bit D E Register
registers is known as a register pair. The only possible
H L
combination register pairs of the 8085 microprocessor
are B-C, D-E and H-L. The programmer cannot form a Stack Pointer
register pair by selecting any two registers of his choice.
The H-L register pair can be used as the address of Program Counter
memory location whereas B-C and D-E register pairs Control Registers
are used to store 16-bit data. During the execution Incrementer/
Decrementer
of the program, all general-purpose registers can be Address Latch
accessed by program instructions and also used for data
manipulation.
 In addition to the above general-purpose registers, the 8085
microprocessor has special-purpose registers, namely, Program Counter (PC), Stack Pointer (SP), Flags/
Status Registers (SR), Instruction Register (IR), Memory Address Register (MAR), Temporary Register
(TR), and Memory Buffer Register (MBR).

The program counter is a 16-bit special-purpose register. This is used to

hold the memory address of the next instruction which will be executed. Actually, this register keeps track
of memory locations of the instructions during execution of program. The microprocessor uses this register
to execute instructions in sequence. For this, the microprocessor increments the content of the program
counter.
The stack pointer is a 16-bit register, which is used to point the memory
location called the stack. The stack is a sequence of memory locations in the R/W memory. The starting of the
stack is defined by loading a 16-bit address into the stack pointer. Generally, the programmers use this register
to store and retrieve the contents of the accumulator, flags, program counter as well as general-purpose
registers during the execution of a program. The organization and application of stacks are incorporated in
Chapter 4.
The Arithmetic Logic Unit (ALU) includes five flip-flops, which are
set or reset after an ALU operation according to data conditions of the result in the accumulator and other
general-purpose registers. The status of each flip-flop is known as a flag. Therefore, there are five flags,
namely, Carry flag (CY), Parity flag (P), Auxiliary Carry flag (AC), Zero flag (Z), and Sign (S) flags. The
most commonly used flags are Carry(CY), Zero(Z) and Sign(S). Generally, the microprocessor uses these
flags to test data conditions.
For example, after addition of two 8-bit numbers, if the sum in the accumulator is larger than eight bits,
the flip-flop, which is used to indicate a carry, is set to one. So the Carry flag (CY) is set to1. If the result is
zero after any arithmetic operation, the Zero (Z) flag is set to one.
Figure 2.7 shows an 8-bit register, which indicates bit positions of different flags. This register is known
as flag register and it is adjacent to the accumulator. Though it is an eight-bit register, only five bit positions
out of eight are used to store the outputs of the five flip-flops. The flags are stored in the 8-bit register so that
the programmer can check these flags through an instruction. These flags are used in the decision-making
process of the microprocessor.

D7 D6 D5 D4 D3 D2 D1 D0 Bit Position

S Z × AC × P × CY

S — Sign Flag
Z — Zero Flag
AC — Auxiliary Carry Flag
P — Parity Flag
CS — Carry Flag

The arithmetic operation generates a carry in case of addition or a borrow in case

of subtraction after execution of an arithmetic instruction and the carry flag is set to 1. When the two 8-bit
numbers are added and the sum is larger than 8 bits, a carry is produced and the carry flag is set to 1. During
subtraction, if borrow is generated, the carry flag is also set to 1. The position of carry flag is D0 as depicted
in Fig. 2.7.
After an arithmetic or logical operation, if the number of 1s in the result is even (even
parity), this parity status flag (P) is set, and if the number of 1s is odd (odd parity), this flag is reset. For
example, if the data byte is 1 1 1 1 1 1 1 1, the number of 1s in the data byte is eight (even parity) and the
parity flag (P) is set to 1. The position of the parity flag is D2 as shown in Fig. 2.7.
In arithmetic operations of numbers, if a carry is generated by bit D3 and
passed on to D4, the auxiliary carry flag (AC) is set. Actually this flag is used for internally Binary Coded
Decimal (BCD) operations and this is not available for the programmer to change the sequence of operations
through jump instructions. The position of auxiliary carry flag is D4 as given in Fig. 2.7.
When an 8-bit ALU operation results in zero, the Zero (Z) flag is set; otherwise it is
reset. This flag is affected by the results of the accumulator and general-purpose registers.
The sign flag has its importance only when a signed arithmetic operation is performed. In
arithmetic operations of signed numbers where the bit D7 is used to indicate a sign, this flag is set to indicate
the sign of a number.
The most significant bit of an 8-bit data is the sign bit. When a number is negative, the sign bit is 1. If the
number is positive, the sign bit is 0. For an 8-bit signed operation, the remaining 7 bits are used to represent
the magnitude of a number. After execution of a signed arithmetic operation, the MSB of the result also rep-
resents its sign. The position of the sign flag is D7 as depicted in Fig. 2.7.
In a flag register five bits (D7 D6 D4 D2 D0) indicate the five status flags and three bits D5 D3 and
D1 are undefined. The combination of these 8 bits is known as Program Status Word (PSW). The PSW and
the accumulator can be used as a 16-bit unit for stack operation.

Determine the status of different flags after addition of 07H and CFH.

When 07H and CFH are added, the result is non zero. The Z flag is set to 0. There is a carry from 3rd bit
to 4th bit. Therefore, the auxiliary carry (AC) flag is set to 1. As the MSB of the sum is 1, the S flag is set
to 1. Since there are five numbers of 1s in the result, the parity flag (P) is set to 0. Figure 2.8 shows the status
of different flags after addition of 07H and CFH.

ADD 07H and CFH

07H = 0 0 0 0 0 1 1 1 Result is non-zero

Z is set to 0 (Z = 0)
CFH = 1 1 0 0 1 1 1 1
There are five number of 1s
1101 0110 P is set to 0 (P = 0)

Carry from 3rd bit to 4th bit

MSB of the SUM is 1 AC is set to 1 (AC = 1)
S is set to 1 (S = 1)
 Find out the status of different flags after addition of CEH and 9BH

If CEH and 9BH are added, the result is non zero. Hence, the Z flag is set to 0. There is a carry from 3rd bit
to 4th bit. As a result, the auxiliary carry (AC) flag is set to 1. Since the MSB of the sum is 0, the S flag is set
to 0. As there are four numbers of 1s in the result, the parity flag (P) is set to 1. The carry is generated after
addition of CEH and 9BH as the sum is greater than 8 bits. Therefore, CS is set to 1. Figure 2.9 shows the
status of different flags after addition of CEH and 9BH.
ADD CEH and 9BH

CEH = 1 1 0 0 1 1 1 0 Result is non-zero

Z is set to 0 (Z = 0)
9BH = 1 0 0 1 1 0 1 1
There are four number of 1s
1011 01001 P is set to 1 (P = 1)

Carry is generated Carry from 3rd bit to 4th bit

CS is set to 1 (CS = 1) AC is set to 1 (AC = 1)

MSB of the SUM is 0

S is set to 0 (S = 0)

The instruction register holds the operation code (opcode) of the current
instruction of a program during an arithmetic/logical operation. The instruction is fetched from the memory
prior to execution. The decoder takes the instruction and decodes it. After that, the decoded instruction is
passed to the next stage for execution.
The Memory Address Register holds the address of the next
program instruction. Then MAR feeds the address bus with addresses of the memory location of the program
instruction which will be executed.
This is an 8-bit register, which is associated with ALU. This register holds
data during arithmetic and logical operation. This register can be used by the microprocessor but is not
accessible to the programmer.

Control Bus
The system bus is collection of wires which are used (Timing Signals,
to transfer binary numbers, one bit per wire. The Ready Signals,
Interrupts)
8085 microprocessor communicates with memory
and input and output devices using three buses,
8085 Address Bus
namely, address bus, data bus and control bus, as (16-bit)
Microprocessor
depicted in Fig. 2.10.

Each memory location has a

unique address. The address bus consists of 16 wires, Data Bus
(8-bit)
therefore address bus has 16 bits. Its ‘width’ is 16
bits. A 16-bit binary number allows 216 different
 A15 Higher-order
A8 Higher - order Address Bus
Address Bus
ALE

AD7 DQ A7

AD6 DQ A6

AD5 DQ A5
8085
Microprocessor
AD4 DQ A4
Lower-order
Address Bus
AD3 DQ A3

AD2 DQ A2

AD1 DQ A1

AD0 DQ A0

74LS373

D7
D6
D5
D4
Data
D3 Bus
D2
D1
D0

numbers, or 65536 different numbers, i.e., 0000 0000 0000 0000 up to 1111 1111 1111 1111. Therefore,
the Intel 8085 microprocessor has 65536 = 64K, where 1K = 1024) memory for locations and each memory
location contains 1 byte of data. The address bus is unidirectional. That means numbers can only be sent from
microprocessor to memory, and not the other way. The 16-bit address bus consists of the 8 most significant
bits of the address A15–A8 and the 8 least significant bits of the address/data AD7–AD0. A7–A0 is multiplexed
with the data lines D0–D7. During the first clock period of the machine cycle, the microprocessor sends 8
MSBs of the address on the A bus and 8 LSBs of the address on the AD bus. If the data is sent during the first
clock period, it will be latched. After the first clock pulse, AD lines as data bus is shown in Fig. 2.11 and the
timing diagram is depicted in Fig. 2.12.

Data bus as 8-bit data is stored in each memory location. The data bus is used to move
or transfer data in binary form. The data is transferred between the microprocessor and external devices.
In the 8085 microprocessor, the data size is 8 bits. Consequently, the data bus typically consists of 8 wires.
Therefore, 28 combinations of binary digits are possible. Data bus is used to transmit ‘data’, i.e., information,
 Machine Cycle (M1)

T1 T2 T3 T4

Clock

A8–A15 PCH (Higher Order Address Bus)

AD0–AD7 PCL Lower D0–D7

Lower Order
Address A0–A7

ALE

RD

results of arithmetic, etc, between the memory and the microprocessor. This bus is bi-directional. Size of the
data bus determines what arithmetic can be done. As a data bus is 8 bits wide, the largest number is 11111111
(255 in decimal).
The address/data bus sends data and addresses at different instant of time. Therefore, it transmits either
data or an address at a particular moment. The AD-bus always operates in the time-shared mode.

The control bus has various lines which have specific functions for coordinating and
controlling microprocessor operations. For example, the RD/WR line is a control signal and this is also a
single binary digit. This signal can differentiate the read and write operations. When RD is logically ‘1’,
memory and other input output devices are read. If WR is logically ‘0’, data can be written in memory
and any other devices. Various other control signals are used to control and coordinate the operation of the
system. Typically, 8085 microprocessor has 11 control lines, namely, S0, S1, IO/M, RD, WR, ALE, READY,
HOLD, HLDA, RESET IN and RESET OUT. The microprocessor cannot function correctly without these
vital control signals. The control bus carries control signals, partly unidirectional, partly bi-directional.

Figure 2.13 shows the schematic diagram of Intel 8085. The PIN diagram of the 8085 microprocessor is
illustrated in Fig. 2.14. The descriptions of various PINS are as follows:
 x1
A15 Higher-order
A8 Address Bus
x0
AD7 Lower-order
CLK (Out) Address/Data Bus
AD0
SID
ALE
SOD
TRAP RD
RST 7.5
WR
RST 6.5
8085
IO/W
RST 5.5
INTR S1
INTA S0
READY
RESET IN
HOLD

HLDA RESET OUT

X1 1 40 VCC
X2 2 39 HOLD
RESET OUT 3 38 HLDA
SOD 4 37 CLK(OUT)
SID 5 36 RESET IN
TRAP 6 35 READY
RST 7.5 7 34 IO/M
RST 6.5 8 33 S1
RST 5.5 9 32 RD
INTR 10 31 WR
INTA 11 30 ALE
AD0 12 29 S0
AD1 13 28 A15
AD2 14 27 A14
AD3 15 26 A13
AD4 16 25 A12
AD5 17 24 A11
AD6 18 23 A10
AD7 19 22 A9
GND 20 21 A8
 Machine cycle status States Machine cycle status States
IO/M S1 S0 IO/M S1 S0
0 0 1 Memory write 1 1 1 Interrupt Acknowledge
0 1 0 Memory read x 0 0 Halt
1 0 1 I/O write x x x Hold
1 1 0 I/O read x x x Reset
0 1 1 Opcode fetch

These are address buses. These are used for the most significant 8
bits of the memory address or 8 bits of I/O address, 3-stated during Hold and Halt modes and during RESET.

These are multiplexed address/data buses. These lines serve a

dual purpose. These are used for the least significant 8 bits of the memory address or I/O during the first clock
cycle (T state) of a machine cycle. After that it becomes the data bus during the second and third clock cycles.
The address on the higher-order bus remains on the bus for the entire machine cycle. But the lower-order
address is changed after the first clock cycle. Actually, this address is latched and used for identifying the
memory address. The AD7–AD0 is used to identify the memory location. Figure 2.9 shows the address bus
A15 to A0 after latching operation. When ALE signal is low, the data is latched till the next ALE signal. The
output of the latch represents the lower-order address bus A7–A0. If ALE is high, the latch is transparent. This
means that the output changes according to input data.

ALE stands for Address Latch Enable. During the

first clock state of a machine cycle, it becomes high and enables the address to get latched either into the
memory or external latch. The falling edge of ALE is set to guarantee set-up, can hold times for the address
information. The falling edge ALE can also be used to strobe the status information.

These are machine-cycle status signals sent by the microprocessor to

distinguish the various types of operations given in Table 2.1. IO/M, S0 and S1 become valid at the beginning
of a machine cycle and remain stable throughout the cycle. IO/M signals differentiate whether the address
is for memory or input–output devices. When IO/M becomes high, I/O operation is performed. It is low for
memory operations. When this signal is combined with RD and WR, this signal transfers the CPU data into
I/O or memory devices.

It is a READ control signal. When

RD is low level, the selected memory or I/O device to be read is available in the data bus for the data transfer.
It has 3-stated during Hold and Halt modes and during RESET.

The WR signal is used for WRITE

control operation. The low level on WR indicates the data on the data bus to be written into the selected
memory or I/O location. It has 3-stated during Hold and Halt modes and during RESET.
Figure 2.15 shows the generation of four different control signals by combining RD, WR and IO/ M
signals. The signal IO/ M is low for any memory-related operation. The IO/ M is logically ANDed with
RD, WR signals and generates memory read MEMR and memory write MEMW control signals. If IO/ M
becomes high, then Input/Output peripheral operations. It is depicted in Fig. 2.15 that the signal is ANDed
with RD, WR signals and generate I/O read IOR and I/O write IOW control signals for any I/O related
operation.

When READY is high during a read or write operation, it indicates that the memory
or I/O device is ready to send or receive data. When READY is low, the CPU will wait for the number of
clock cycles until READY becomes high.

HOLD indicates that another

master is requesting the use of the address and data IO/M
buses. After receiving the hold request, the CPU will MEMR
RD
relinquish the use of the bus as soon as the completion
of the current bus cycle.
MEMW
The processor can regain the bus only after WR
8085
the HOLD is removed. When the HOLD is acknowl- Microprocessor
edged, the address, data, RD, WR, and IO/M lines are
3-stated. IOR

HLDA stands for HOLD

ACKNOWLEDGE. This signal indicates that the CPU IOW
has received the Hold request and that it will relinquish
the bus in the next clock cycle. When the Hold request
is removed, HLDA goes low. The CPU takes the bus
one half-clock cycle after HLDA goes low.

INTR is the INTERRUPT REQUEST signal. It is used as general-purpose interrupt.

Among interrupts, it has the lowest priority. It is sampled only during the next to the last clock cycle of an
instruction. If it is active, the Program Counter (PC) will be inhibited from incrementing and an Interrupt
Acknowledge (INTA) signal will be issued. The microprocessor suspends its normal sequence of instructions.
During this cycle, a RESTART or CALL instruction can be inserted to jump to the interrupt service routine.
The INTR can be enabled and disabled by using software. It is disabled by RESET and immediately
after an interrupt is accepted. Generally, the interrupt signal is used by I/O devices to transfer data to the
microprocessor without wasting its time.

It is an interrupt acknowledge signal. This is used instead of RD during the

instruction cycle after an INTR is accepted. This signal is sent by the microprocessor after INTR is received.
It can be used to activate the 8259 interrupt IC.

RST 5.5, RST 6.5 and RST 7.5 are the restart interrupts.
These three inputs have the same timing as INTR except they cause an internal restart to be automatically
inserted. The priority order of these interrupts is given in Table 2.2. These interrupts have a higher priority
than INTR. These are vectored interrupts and during execution, transfer the program to the specified memory
location.
 Name Priority Address branched to memory location when interrupt occurs
TRAP 1 0024H
RST 7.5 2 003CH
RST 6.5 3 0034H
RST 5.5 4 002CH
INTR 5 The address branched depending on the instruction provided to the CPU when the inter-
rupt is acknowledged

Trap interrupt is a nonmaskable restart interrupt. It has the highest priority of any
interrupt as depicted in Table 2.2. It is recognized at the same timing as INTR or RST 5.5 or RST 6.5 or RST
7.5. It is unaffected by any mask or Interrupt enable.

The RESETIN signal resets the program counter to zero and it also resets the
Interrupt Enable and HLDA flip-flops. It does not affect any other flag or register except the instruction
register. The data and address buses and the control lines are 3-stated during RESETIN and because of the
asynchronous nature of RESETIN, the processor’s internal registers and flags may be altered by RESET
with unpredictable results. RESETIN is a Schmitt-triggered input, allowing connection to an RC network for
power-on RESET delay. The CPU is held in the reset condition as long as RESETIN is applied.

RESETOUT indicates that the CPU is in RESET condition. This can be

used as a system reset. This signal is also synchronized to the processor clock and lasts an integral number
of clock periods.

The X1 and X2 terminals are connected to a crystal or RC network or LC network to

drive the internal clock generator. X1 may be an external clock input from a logic gate. The input frequency is
divided by 2 to give the processor’s internal operating frequency. When 6 MHz clock frequency of a crystal
or RC network or LC network is applied to the processor, the microprocessor operates in 3 MHz.

The Clock output signal can be used as a system clock. The time period of CLK is
twice the X1, X2 input time period.

SID stands for Serial Input Data line. The data on this line is loaded into the accumulator
bit 7 whenever a RIM instruction is executed.

SOD stands for Serial Output Data line. The output SOD is set or reset as specified
by the SIM instruction.

The 8085 microprocessor operates on a 5 V supply, which is connected

with VCC terminal at PIN number 40.
 Ground Reference.
The power supply ground is connected to GND at PIN number 20.
Table 2.3 shows the comparisons between 8085 and 8080A based on power supply, frequency and chip
count. The 8085 is much simpler than 8080A for generating status information and control signals. The 8085
include all 72 instructions of 8080A, but it has two more instructions such as serial I/O and additional inter-
rupt lines.

Parameters 8085 8080A

Power supply +5V +5V, –5V and +12V
Functional microprocessor One 8085 IC with latch and gates One 8080A, one 8224 and one 8228
Clock pulse One z Two z1 z2
Clock frequency 3 MHz 2 MHz
Address bus 16-bit address lines Lower-order address 16-bit address lines
bus is multiplexed with data bus
Data bus 8-bit data lines 8-bit data lines Data and status
information are multiplexed
Interrupt Five lines One line
Extra features Serial I/O lines
Status The lines S0, S1 and IO/M indicates Complex procedure to generate status
operation status information
Instruction set 74 instructions 72 instructions

In this chapter the architecture of 8085 microprocessor has been explained. The microprocessor
communicates with memory, input and output peripheral devices through an address bus, data bus and
control bus. An address bus is a group of lines that are used to locate a memory address or external
device.
The 8085 microprocessor has 16-bit address lines A15 to A0. This bus is unidirectional. Data bus is a
group of bi-directional lines. These lines are used to transfer data between microprocessor and memory
or input and output peripheral devices. The 8085 microprocessor has 8-bit data lines D7 to D0, which is
time multiplexing of lower order address/data bus AD7–AD0.
Generally, a microprocessor performs four operations: memory read, memory write, I/O read and I/O
write. The generation of read/write control signal MEMR, MEMW, IOR, IOW are incorporated in this
section.
The PIN diagrams of 8085 and their functions are also explained in this chapter.