INTRODUCTION

1.1 INTRODUCTION
Gone are the days when huge computers made of vacuum tubes sat humming in entire
dedicated rooms and could do about 360 multiplications of 10-digit numbers in a second.
Though they were heralded as the fastest computing machines of that time, they surely
don’t stand a chance when compared to the modern-day machines. Modern progressing
second. But what drove this change? The whole domain of computing ushered into a new
dawn of electronic miniaturization with the advent of semiconductor transistor by
Bardeen (1947-48) and then the Bipolar Transistor by Shockley (1949) in the Bell
Laboratory. Since the invention of the first IC (Integrated Circuit) in the form of a Flip
Flop by Jack Kilby in 1958, our ability to pack more and more transistors onto a single
chip has doubled roughly every 18 months, in accordance with the Moore’s Law. Such
exponential development had never been seen in any other field and it still continues to
be a major area of research work.
VLSI chiefly comprises of Front-End Design and Back End design these days. While front
end design includes digital design using HDL, design verification through simulation and
other verification techniques, the design from gates and design for testability, backend
design comprises of CMOS library design and its characterization. It also covers the
physical design and fault simulation.

1.2 MOORE’S LAW

Moore's Law is the observation made by Gordon Moore, co-founder of Intel, in 1965. He
noticed that the number of transistors on a microchip was doubling approximately every
two years, leading to a consistent exponential increase in computing power. This
observation has become a guiding principle for the semiconductor industry and has driven
the rapid advancements in technology we've seen over the past several decades. However,
as transistor sizes approach physical limits and manufacturing costs rise, some experts
debate whether Moore's Law will continue to hold true in the future.

In the decades that followed Gordon Moore's original observation, Moore’s law guided
the semiconductor industry in long-term planning and setting targets for research and
development (R&D). Moore's Law has been a driving force of technological and social

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change, productivity, and economic growth that are hallmarks of the late 20th and early
21st centuries.

1.3 HISTORY

In 1920s when several inventors attempted devices that were intended to control current
in solid-state diodes and convert them into triodes. After World War II, when the use of
silicon and germanium crystals as radar detectors led to improvements in fabrication and
theory. Scientists who had worked on radar returned to solid-state device development.
The invention of the first transistor was at Bell Labs in 1947, the field of electronics
shifted from vacuum tubes to solid-state devices.

With the small transistor at their hands, electrical engineers of the 1950s saw the
possibilities of constructing far more advanced circuits. However, as the complexity of
circuits grew, problems arose.[1] One problem was the size of the circuit. A complex circuit
like a computer was dependent on speed. If the components were large, the wires
interconnecting them must be long. The electric signals took time to go through the circuit,
thus slowing the computer.

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The invention of the integrated circuit by Jack Kilby and Robert Noyce solved this
problem by making all the components and the chip out of the same block (monolith) of
semiconductor material. The circuits could be made smaller, and the manufacturing
process could be automated. This led to the idea of integrating all components on a single-
crystal silicon wafer, which led to small-scale integration (SSI) in the early 1960s, and
then medium-scale integration (MSI) in the late 1960s.

Very large-scale integration was made possible with the wide adoption of the MOS
transistor, originally invented by Mohamed M. Atalla and Dawon Kahng at Bell Labs in
1959. Atalla first proposed the concept of the MOS integrated circuit chip in 1960,
followed by Kahng in 1961, both noting that the MOS transistor's ease of fabrication made
it useful for integrated circuits. General Microelectronics introduced the first commercial
MOS integrated circuit in 1964. In the early 1970s, MOS integrated circuit technology
allowed the integration of more than 10,000 transistors in a single chip. This paved the
way for VLSI in the 1970s and 1980s, with tens of thousands of MOS transistors on a
single chip (later hundreds of thousands, then millions, and now billions).

The first semiconductor chips held two transistors each. Subsequent advances added more
transistors, and as a consequence, more individual functions or systems were integrated
over time. The first integrated circuits held only a few devices, perhaps as many as ten
diodes, transistors, resistors and capacitors, making it possible to fabricate one or more
logic gates on a single device. Now known retrospectively as small-scale integration
(SSI), improvements in technique led to devices with hundreds of logic gates, known as
medium-scale integration (MSI). Further improvements led to large-scale integration
(LSI), i.e. systems with at least a thousand logic gates. Current technology has moved far
past this mark and today's microprocessors have many millions of gates and billions of
individual transistors.

At one time, there was an effort to name and calibrate various levels of large-scale
integration above VLSI. Terms like ultra-large-scale integration (ULSI) were used. But
the huge number of gates and transistors available on common devices has rendered such
fine distinctions moot. Terms suggesting greater than VLSI levels of integration are no
longer in widespread use.

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In 2008, billion-transistor processors became commercially available. This became more
commonplace as semiconductor fabrication advanced from the then-current generation of
65 nm processes. Current designs, unlike the earliest devices, use extensive design
automation and automated logic synthesis to lay out the transistors, enabling higher levels
of complexity in the resulting logic functionality. Certain high-performance logic blocks
like the SRAM (static random-access memory) cell, are still designed by hand to ensure
the highest efficiency.

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 CHAPTER 2
DESIGN FLOW
2.1 INTRODUCTION
Design flow, also known as the design methodology, is a systematic approach used in VLSI
design to ensure the efficient and effective development of integrated circuits. It provides a
structured frame work that helps designers navigate through different stages of the design
process, from concept to production. The design flow encompasses several steps, including
specifications, design entry, synthesis, verification, layout and fabrication

2.2 DESGIN FLOW

While Simple logic gates might be considered as SSI devices and multiplexers and parity
encoders as MSI, the world of VLSI is much more diverse. Generally, the entire design
procedure follows a step-by-step approach in which each design step is followed by
simulation before actually being put onto the hardware or moving on to the next step. The
major design steps are different levels of abstractions of the device as a whole:

[Link] Specification: It is more of a high-level representation of the system. The

major parameters considered at this level are performance, functionality, physical
dimensions, fabrication technology and design techniques. It has to be a trade-off between
market requirements, the available technology and the economic viability of the design.
The end specifications include the size, speed, power and functionality of the VLSI
system.

2. Architecture Definition: Basic specifications like Floating point units, which system to
use, like RISC( Reduce instruction set) and CISC(Complex instruction set), number of
ALU’s cache size etc.

3. Functional Design: Defines the major functional units of the system and hence
facilitates the identification of interconnect requirements between units, the physical and
electrical specifications of each unit. A sort of block diagram is decided upon with the
number of inputs, outputs and timing decided upon without any details of the internal
structure.

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4. Logic Design: The actual logic is developed at this level. Boolean expressions, control
flow, word width, register allocation etc. are developed and the outcome is called a
Register Transfer Level (RTL) description. This part is implemented either with Hardware
Descriptive Languages like VHDL and/or Verilog. Gate minimization techniques are
employed to find the simplest, or rather the smallest most effective implementation of the
logic.

5. Circuit Design: While the logic design gives the simplified implementation of the logic,
the realization of the circuit in the form of a netlist is done in this step. Gates, transistors
and interconnects are put in place to make a netlist. This again is a software step and the
outcome is checked via simulation.

6. Physical Design: The conversion of the netlist into its geometrical representation is
done in this step and the result is called a layout. This step follows some predefined fixed
rules like the lambda rules which provide the exact details of the size, ratio and spacing
between components. This step is further divided into sub-steps which are

6.1 Circuit Partitioning: Because of the huge number of transistors involved, it is

not possible to handle the entire circuit all at once due to limitations on
computational capabilities and memory requirements. Hence the whole circuit is
broken down into blocks which are interconnected.

6.2 Floor Planning and Placement: Choosing the best layout for each block from
partitioning step and the overall chip, considering the interconnect area between
the blocks, the exact positioning on the chip in order to minimize the area
arrangement while meeting the performance constraints through iterative
approach are the major design steps taken care of in this step.

6.3 Routing: The quality of placement becomes evident only after this step is
completed. Routing involves the completion of the interconnections between
modules. This is completed in two steps. First connections are completed between
blocks without taking into consideration the exact geometric details of each wire
and pin. Then, a detailed routing step completes point to point connections
between pins on the blocks.

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 6.4 Layout Compaction: The smaller the chip size can get, the better it is. The
compression of the layout from all directions to minimize the chip area thereby
reducing wire lengths, signal delays and overall cost takes place in this design
step.

6.5 Extraction and Verification: The circuit is extracted from the layout for
comparison with the original netlist, performance verification, and reliability
verification and to check the correctness of the layout is done before the final step
of packaging.

7. Packaging: The chips are put together on a Printed Circuit Board or a Multi Chip
Module to obtain the final finished product.

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Initially, design can be done with three different methodologies which provide different
levels of freedom of customization to the programmers. The design methods, in increasing
order of customization support, which also means increased amount of overhead on the
part of the programmer, are FPGA and PLDs, Standard Cell (Semi Custom) and Full
Custom Design.

While FPGA’s have inbuilt libraries and a board already built with interconnections and
blocks already in place; Semi Custom design can allow the placement of blocks in user
defined custom fashion with some independence, while most libraries are still available
for program development. Full Custom Design adopts a start from scratch approach where
the programmer is required to write the whole set of libraries and also has full control
over the block development, placement and routing. This also is the same sequence from
entry level designing to professional designing

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 CHAPTER 3
HARDWARE DESCRIPTION LANGUAGE
3.1 INTRODUCTION
In the early days of Integrated Circuits, engineers had to sit down and physically
draw transistors and their connections on paper to design them such that it can
be fabricated on silicon. Bigger and complex circuits demanded more engineers,
time and other resources and soon enough there was a need to have a better way
of designing integrated circuits.
Hardware description language (HDL) is a specialized computer language used
to program electronic and digital logic circuits. The structure, operation and
design of the circuits are programmable using HDL. HDL includes a textual
description consisting of operators, expressions, statements, inputs and outputs.
Instead of generating a computer executable file, the HDL compilers provide a
gate map. The gate map obtained is then downloaded to the programming device
to check the operations of the desired circuit. The language helps to describe any
digital circuit in the form of structural, behavioural and gate level and it is found
to be an excellent programming language for FPGAs and CPLDs.
The three common HDLs are Verilog, VHDL, and SystemC. Of these, SystemC is the
newest. The HDLs will allow fast design and better verification. In most of the industries,
Verilog and VHDL are common. Verilog, one of the main Hardware Description Language
standardized as IEEE 1364 is used for designing all types of circuits. It consists of modules and
the language allows Behavioral, Dataflow and Structural Description. VHDL (Very High Speed
Integrated Circuit Hardware Description Language) is standardized by IEEE1164. The design
is composed of entities consisting of multiple architectures. SystemC is a language that consist
a set of C++classes and macros. It allows electronic system level and transaction modeling.

3.2 NEED FOR HDL

The Moore’s Law in the year 1970 has brought a drastic change in the field of
IC technology. This change has made the developers to bring out complex digital
and electronic circuits. But the problem was the absence of a better programming
language allowing hardware and software codesign. Complex digital circuit
designs require more time for development, synthesis, simulation and
debugging. The arrival of HDLs has helped to solve this problem by allowing
each module to be worked by a separate team.
All the goals like power, throughput, latency (delay), test coverage, functionality
and area consumption required for a design can be known by using HDL. As a

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result, the designer can make the necessary engineering tradeoffs and can
develop the design in a better and efficient way. Simple syntax, expressions,
statements, concurrent and sequential programming is also necessary while
describing the electronics circuits. All these features can be obtained by using a
hardware description language. Now while comparing HDL and C languages,
the major difference is that HDL provides the timing information of a design.

3.3 POPULARS HLD’S

There are several HDLs available but the most popular HDLs are Verilog and VHDL.
Verilog: Verilog stands for verification logic. It is used to model and stimulate the Digital
circuits Application-Specific Integrated Circuits (ASICs) and Field-Programmable Gate
Arrays (FPGAs).
VHDL: VHDL stands for Very High-speed Integrated Circuit Hardware Description
Language (VHSIC). It is used to design digital circuits. It is often used to design complex
Digital circuits such as Microprocessors and Digital Signal Processors.

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 CHAPTER 4
VERILOG
4.1 INTRODUCTION
For a long time, computer programming languages like FORTRAN, Pascal, and C were used
to describe computer programs and their code execution is sequential. But there isn't any
language to describe the digital circuits. This is when Hardware Description Language(HDL)
came into play. HDLs are even popular for verification purposes. There are mainly two types
of HDL:
• Verilog HDL
• VHDL (Very High-Speed was Integrated Circuit (VHSIC) Hardware Description
Language)
4.2 VERILOG
Verilog was developed to simplify the process and make the Hardware
description language(HDL) more robust and flexible. Today, Verilog is the most
popular HDL used and practiced throughout the semiconductor industry. Verilog
consist a level of abstraction that helps hide away the details of its
implementation and technology.

4.3 VERILOG MODELLING STYLES

Verilog Design has the capability of designing a module in several coding styles.
Depending on the needs of a design, internals of each module can be defined at
four level of abstractions. Irrespective of the internal abstraction level, the
module would behave exactly in the similar way to the external environment.
Following are the four different levels of abstraction which can be described by
the four different coding styles of Verilog language:
These three modelling styles of Verilog HDL are related to the three previously mentioned
modelling aspects of the digital circuit.
1. Structural
2. Behavioural
3. Data flow
4.4 Structural Modelling Style
The structural modelling style is the lowest level of abstraction obtained using logic gates.
Similar to schematic or circuit diagrams of the digital circuit, Verilog uses primitive gates to
compile and synthesize the program.

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Of course, this abstraction can’t be understood by humans. Machines, however, have the
definite capability of compiling and logically synthesizing the code.
The language supports multiple gates such as and, or, nand, xor, nor, and xnor. You can also
use tri-state gates and multiple-output gates such as bufif1, bufif0, notif1, notif0, not,
and buf.
Here’s the syntax of these gates:
• and | or | nand | xor | nor | xnor [instance name] (output, input1, ….., inputn);
• not | buf [instance name] (output 1, output2, ….., output n, input);
• bufif1 | bufif0 | notif1 | notif0 [instance name] (output, input, control);
4.5 Behavioural Modelling Style
Behavioural modelling is the highest of level abstraction that completely depends on the circuit
behaviour or on the truth table.
If you know how your circuit will behave, you can design it. In fact, you can design the module
without knowing the components of the hardware.
However, even though it is the closest in terms of natural language understanding of the circuit
functionality, this modelling type is hardest to implement and synthesize. Hence, it is utilized
for complex circuits such as pure combinational or sequential circuits.
A module developed using behavioural modelling contains initial or always statements, which
are executed concurrently (according to the parallelism of the model). The procedural
statements in the module are executed sequentially.
At time=0, both the initial and always will execute and then, always statements run for the
remaining time. Here’s the syntax:
always [timing control] procedural_statements;
initial [ timing control] procedural_statements;
4.6 Data Flow Modelling Style
The data flow is a medium level abstraction, which is achieved by defining the data flow of the
module. You can design the module by defining and expressing input signals which are
assigned to the output, very much similar to logical expressions.
For most of the modules, data flow modelling is simple to implement and can be easily
translated to structure such as in the case of combinational circuits.
The combinational circuits use continuous assignments, where value is defined for a data net.
assign[delay] LHS_net = RHS_expression

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 CHAPTER 5
Verilog code for 4:1 MUX using Different Modelling
5.1 INTRODUCTION
A multiplexer is a data selector device that selects one input from several input lines, depending
upon the enabled, select lines, and yields one single output.
A multiplexer of 2n inputs has n select lines, are used to select which input line to send to the
output. There is only one output in the multiplexer, no matter what’s its configuration.
These devices are used extensively in the areas where the multiple data can be transferred over
a single line like in the communication systems and bus architecture hardware. Visit this post
for a crystal clear explanation to multiplexers

Truth Tabel for 4:1 MUX

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5.2 Data flow modelling
The dataflow modeling represents the flow of the data. It is described through the data flow
through the combinational circuits rather than the logic gates used.
In Verilog, the assign statement is used in data-flow abstraction.
It is necessary to know the logical expression of the circuit to make a dataflow model. The
equation for 4:1 MUX is:
Logical Expression: out = (a. s1′.s0′) + (b.s1′.s0) + (c.s1.s0′) + (d. s1.s0)

5.3 Verilog code for 4×1 multiplexer using data flow modeling
module m41 ( input a,
input b,
input c,
input d,
input s0, s1,
output out);
assign out = s1 ? (s0 ? d : c) : (s0 ? b : a);
endmodule

OUTPUT

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5.3 Gate level modeling

The gate-level abstraction is the lowest level of modeling. The switch level model is also a low
level of modeling but it isn’t that common. The gate-level modeling style uses the built-in basic
logic gates predefined in Verilog. We only need to know the logic diagram of the system since
the only requirement is to know the layout of the particular logic gates.

5.4 Verilog code for 4×1 multiplexer using gate-level modelling

module m41(out, a, b, c, d, s0, s1);
output out;
input a, b, c, d, s0, s1;
wire sobar, s1bar, T1, T2, T3, T4;
not (s0bar, s0), (s1bar, s1);
and (T1, a, s0bar, s1bar), (T2, b, s0bar, s1),(T3, c, s0, s1bar), (T4, d, s0, s1);
or(out, T1, T2, T3, T4);
endmodule

OUTPUT

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 CHAPTER 6
Verilog code for demultiplexer
6.1 INTRODUCTION
A demultiplexer is a circuit that places the value of a single data input onto multiple data
outputs. The demultiplexer circuit can also be implemented using a decoder circuit.
Here we are going to work with 1-to-4 demultiplexer. A 1-to-4 demultiplexer consists of
• one input data line,
• four outputs, and
• two control lines to make selections.
The below diagram shows the circuit of the 1-to-4 demultiplexer. Here a1 and a0 are control or
select lines y0, y1, y2, y3 are outputs, and Din is the data line.

Truth table for De-mux

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6.2 Verilog code for demultiplexer
module demux_1_4(
input [1:0] sel,
input i,
output reg y0,y1,y2,y3);
always @(*) begin
case(sel)
2'h0: {y0,y1,y2,y3} = {i,3'b0};
2'h1: {y0,y1,y2,y3} = {1'b0,i,2'b0};
2'h2: {y0,y1,y2,y3} = {2'b0,i,1'b0};
2'h3: {y0,y1,y2,y3} = {3'b0,i};
default: $display("Invalid sel input");
endcase
end
endmodule

OUTPUT

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 CHAPTER 7
Simulation Using Testbench

7.1 Introduction
Simulations are controlled using testbenches. A testbench is an additional
Verilog module (not part of the actual system design) used to generate the
appropriate waveforms on the input ports of the module under test, in order to
exercise the functionality of that module. Optionally, the testbench also monitors
the outputs of the module under test, and generates warnings if they deviate from
the expected output values. A testbench is simply a Verilog module. But it is
different from the Verilog code we write for a DUT. Since the DUT’s Verilog
code is what we use for planning our hardware, it must be synthesizable.
Whereas, a testbench module need not be synthesizable. We just need to simulate
it to check the functionality of our DUT.

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 CHAPTER 8
Verilog code for Halfadder using testbench
8.1 Intoduction
Half adder is a combinational circuit which computer binary addition of two binary inputs. It
is one of the basic combinational circuit in which we have combination of two gates (ex-or
gate, and gate). The truth table of half adder is given below and we can write boolean
expression for half adder as follows sum=a⊕b

Truth table

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8.2 Verilog code for Half-adder
module half_adder_d (
input a,b,
output sum,carry
);
assign sum = a ^ b;
assign carry = a & b;
endmodule
8.3 Half-adder Testbench
module half_adder_tb;
reg a,b;
wire sum,carry;
half_adder_s uut(a,b,sum,carry);
initial begin
a = 0; b = 0;
#10
b = 0; b = 1;
#10
a = 1; b = 0;
#10
b = 1; b = 1;
#10
$finish();
end
endmodule

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OUTPUT

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 CHAPTER 9
Encoder
9.1 INTRODUCTION
An encoder basically converts ‘M’ input lines (can be decimal, hex, octal, etc) to coded ‘N’
output lines. Various encoders can be designed like decimal-to-binary encoders, octal-to-binary
encoders, decimal- to-BCD encoders, etc
An encoder basically shrinks receiving many input data lines to the output lines. This is helpful
in reducing input data lines for further processing.

9.2 BINARY ENCODER

The binary encoder converts M (=2^n) input lines to N (=n) coded binary code.
It is also known as a digital encoder. A single input line must be high for valid
coded output, otherwise, the output line will be invalid. To address this limitation,
the priority encoder prioritizes each input line when multiple input lines are set
to high.
Nomenclature: M: N encoder where M denotes input lines and N denotes coded
output lines.
9.3 8:3BINARY ENCODER

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Logical Expression
y2 = D4 + D5 + D6 + D7
y1 = D2 + D3 + D6 + D7
y0 = D1 + D3 + D5 + D7

9.4 8:3 BINARY ENCODER VERILOG CODE

module binary encoder(
input [7:0] D,
output [2:0] y);
assign y[2] = D[4] | D[5] | D[6] | D[7];
assign y[1] = D[2] | D[3] | D[6] | D[7];
assign y[0] = D[1] | D[3] | D[5] | D[7];
endmodule
9.5 TESTBENCH CODE
module tb;
reg [7:0] D;
wire [2:0] y;
int i;
binary encoder bin_enc(D, y);
initial begin
D=8'b1; #1;
for(i=0; i<8; i++) begin
$display("D = %h(in dec:%0d) -> y = %0h", D, i, y);
D=D<<1; #1;
end
end
endmodule
OUTPUT
D = 01(in dec:0) -> y = 0
D = 02(in dec:1) -> y = 1
D = 04(in dec:2) -> y = 2

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D = 08(in dec:3) -> y = 3
D = 10(in dec:4) -> y = 4
D = 20(in dec:5) -> y = 5
D = 40(in dec:6) -> y = 6
D = 80(in dec:7) -> y = 7

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 CHAPTER 10
Decoder
10.1 INTRODUCTION

The decoder behaves exactly opposite of the encoder. They decode already
coded input to its decoded form. The ‘N’(=n) input coded lines decode to
‘M’(=2^n) decoded output lines. The decoder sets exactly one line high at the
output for a given encoded input line.
Nomenclature: N: M decoder where N denotes coded input lines and M denotes
decoded output lines

10.2 3:8 BINARY DECODER TRUTH TABEL

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10.3 3:8 BINARY DECODER VERILOG CODE

module binary decoder(

input [2:0] D,
output reg [7:0] y);

always@(D) begin
y = 0;
case(D)
3'b000: y[0] = 1'b1;
3'b001: y[1] = 1'b1;
3'b010: y[2] = 1'b1;
3'b011: y[3] = 1'b1;
3'b100: y[4] = 1'b1;
3'b101: y[5] = 1'b1;
3'b110: y[6] = 1'b1;
3'b111: y[7] = 1'b1;
default: y = 0;
endcase
end
endmodule
10.4 TEST BENCH
module tb;
reg [2:0] D;
wire [7:0] y;
binary_decoder bin_dec(D, y);
initial begin
$monitor("D = %b -> y = %0b", D, y);
repeat(5) begin

26
 D=$random; #1;
end
end
endmodule
OUTPUT
D = 100 -> y = 10000
D = 001 -> y = 10
D = 011 -> y = 1000
D = 101 -> y = 100000

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 CHAPTER 11
Implementation of 8 x8 asynchronous FIFO memory
11.1 Introduction
Design and Verification of Asynchronous FIFO using Verilog/UVM FIFOs are
often used to safely pass data from one clock domain to another asynchronous
clock domain. Using a FIFO to pass data from one clock domain to another
clock domain requires multi-asynchronous clock design techniques. There are
many ways to design a FIFO wrong. There are many ways to design a FIFO
right but still make it difficult to properly synthesize and analyze the design.
This project will detail one method that is used to design, synthesize and
analyze a safe FIFO between different clock domains without using Gray code
pointers that are synchronized into a different clock domain before testing for
"FIFO full" or "FIFO empty" conditions.

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11.2 Program

module async_fifo (
input wire clk_w, // Write clock
input wire clk_r, // Read clock
input wire wr_en, // Write enable
input wire rd_en, // Read enable
input wire [7:0] data_in,// Data input
output reg [7:0] data_out,// Data output
output reg full, // FIFO full flag
output reg empty, // FIFO empty flag
output reg [2:0] count // Number of elements in FIFO
);

reg [7:0] fifo_mem [7:0]; // Memory array for 8x8 FIFO

reg [2:0] wr_pointer; // Write pointer
reg [2:0] rd_pointer; // Read pointer

initial begin
wr_pointer = 3'b000;
rd_pointer = 3'b000;
count = 3'b000;
full = 1'b0;
empty = 1'b1;
end

// Write process
always @(posedge clk_w) begin
if (wr_en && !full) begin

29
 fifo_mem[wr_pointer] <= data_in; // Write data
wr_pointer <= wr_pointer + 1'b1; // Increment write pointer
count <= count + 1'b1; // Increment count
end
// Update full/empty flags
if (count == 3'b111)
full <= 1'b1;
else
full <= 1'b0;
if (count == 3'b000)
empty <= 1'b1;
else
empty <= 1'b0;
end

// Read process
always @(posedge clk_r) begin
if (rd_en && !empty) begin
data_out <= fifo_mem[rd_pointer]; // Read data
rd_pointer <= rd_pointer + 1'b1; // Increment read pointer
count <= count - 1'b1; // Decrement count
end
// Update full/empty flags
if (count == 3'b111)
full <= 1'b1;
else
full <= 1'b0;
if (count == 3'b000)
empty <= 1'b1;
else

30
 empty <= 1'b0;
end
endmodule
11.3 Testbench
module tb_async_fifo;

// Testbench signals
reg clk_w;
reg clk_r;
reg wr_en;
reg rd_en;
reg [7:0] data_in;
wire [7:0] data_out;
wire full;
wire empty;
wire [2:0] count;

// Instantiate the FIFO

async_fifo uut (
.clk_w(clk_w),
.clk_r(clk_r),
.wr_en(wr_en),
.rd_en(rd_en),
.data_in(data_in),
.data_out(data_out),
.full(full),
.empty(empty),
.count(count)
);

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// Generate write clock
initial begin
clk_w = 0;
forever #5 clk_w = ~clk_w; // 10 ns period
end

// Generate read clock

initial begin
clk_r = 0;
forever #7 clk_r = ~clk_r; // 14 ns period
end

// Test procedure
initial begin
// Initialize signals
wr_en = 0;
rd_en = 0;
data_in = 8'h00;

// Write data into the FIFO

#10;
wr_en = 1;
data_in = 8'h01; #10;
data_in = 8'h02; #10;
data_in = 8'h03; #10;
data_in = 8'h04; #10;
data_in = 8'h05; #10;
data_in = 8'h06; #10;
data_in = 8'h07; #10;
data_in = 8'h08; #10; // This should fill the FIFO

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 wr_en = 0; // Disable write

// Read data from the FIFO

#20;
rd_en = 1; #10; // Read first element
rd_en = 1; #10; // Read second element
rd_en = 1; #10; // Read third element
rd_en = 1; #10; // Read fourth element
rd_en = 1; #10; // Read fifth element
rd_en = 1; #10; // Read sixth element
rd_en = 1; #10; // Read seventh element
rd_en = 1; #10; // Read eighth element
rd_en = 1; #10; // This should empty the FIFO
rd_en = 0; // Disable read

// End simulation
#20;
$stop;
end

// Monitor outputs
initial begin
$monitor("Time: %0t | Data In: %h | Data Out: %h | Full: %b | Empty: %b | Count: %d",
$time, data_in, data_out, full, empty, count);
end

endmodule

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11.4 Result

Plot from 100ns to 220ns

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 CHAPTER 12
CONCLUSION

During my internship at , I gained invaluable insights into the field of VLSI design and
implementation. Over the course of my experience, I engaged in various projects that allowed
me to apply theoretical knowledge to practical scenarios, enhancing my understanding of
digital circuit design, layout techniques, and verification processes.
I was involved in [briefly mention specific projects or tasks, e.g., "developing a testbench for
a FIFO module", which provided me with hands-on experience in using industry-standard
tools like [mention tools, e.g., Cadence, Synopsys, or others]. Collaborating with experienced
professionals and participating in team meetings broadened my perspective on project
workflows and the importance of communication in a multidisciplinary environment.
This internship not only improved my technical skills but also reinforced the significance of
attention to detail and problem-solving in VLSI design. I developed a greater appreciation for
the complexities involved in chip design and the iterative nature of the development process.
Looking forward, I am eager to apply the skills and knowledge I have gained during this
internship in my future academic and professional endeavours. I am grateful for the
opportunity to work alongside talented individuals and contribute to impactful projects within
the field of VLSI.

35