UNIT-2

Logic Design With Behavioral

Models of Combinational and
Sequential Logic
 Contents
• Behavioral modelling
• Data types for behavioral modelling
• Behavioral models of combinational logic
• Propagation delay and continuous assignments
• Lathes and level sensitive circuits in Verilog
• Cyclic behavioral models of flip flops and latches
• Cyclic behavior and edge detection
• A Comparison of styles for behavioral modelling
Behavioral Modeling
• For designing ASICs and FPGAs, large circuits are partitioned to form
an architecture
• ie., A configuration of functional units that communicate through their ports
• Each unit is described by a behavioral model of its functionality.

• Behavioral modeling is the predominant descriptive style used by

industry, enabling the design of massive chips.
• It describes the functionality of a design – What the designed circuit will do,
but not How to build it in hardware
• Behavioral models specify the input-output model of a logic circuit -
- and suppress details about its low-level internal structure and
physical implementation.

• Propagation delays are not included in the behavioral model

• But they are considered by synthesis tool when it imposes timing constraints.
• Behavioral modeling encourages designers to
1. Rapidly create a behavioral prototype of a design (without
binding it to hardware detail)
2. Verify its functionality and
3. Uses a synthesis tool to optimize and map the design into a
selected physical technology, subject to constraints on timing
and/or area.
Datatypes for Behavioral modeling
• All Computer programs represent information as variables (eg:
integers & real numbers) that can be retrieved, manipulated, and
stored in memory.
• A Variable may represent
• A number used in computation
• A value of data
• Or a computed value

• Variable are declared and used according to rules that govern the
data types supported by the language
• All variables in Verilog have only two families of predefined data types
• Nets
• Registers

• Net variables act like wires in a physical circuit and establish

connectivity between design objects

• Register variables act like variables in ordinary procedural languages

• They store information while the program executes
•Mainly used are
•net type wire
•Register type reg and integer

•A wire and reg have default size of 1 bit.

•The size of integer is automatically fixed at the word
length supported by host computers, at least 32 bits.
Boolean equation based Behavioral models
of combinational logic
• A Boolean equation describes combinational logic by an expression of
operations on variables.
• In Verilog, it is the continuous assignment statement.

Eg. AOI Gate:

• AOI gate with additional input, enable, and to have a three-state
output:
• Here, the conditional operator (? :) act like if-then-else switch
•Note: The continuous assignment statement is an implicit,
abstract and compact representation of the structure
• described by an equivalent gate level schematic or netlist of
primitives.
• AOI Gate declares y_out to be of type wire, and associates with it a
Boolean expression that defines the value of y_out
• A continuous assignment statement with a conditional operator
provides a convenient way to model a circuit.
• Eg: A two channel Multiplexer 32-bit datapaths.
• Verilog code of 2x1 MUX:
 Propagation delay and Continuous
assignments
•Propagation (inertial) delay can be associated with a
continuous assignment
• So that its implicit logic has the same functionality and timing
characteristics as its gate level counterpart.
 AOI gate structure with unit Prop. Delay
• A logic expression assigning value to the wire and includes a unit time
delay
• Detects change in its RHS expression and schedules a change to
update the LHS variable (subject to the Prop delay)
2-bit comparator using continuous
assignment statements
• Called as implicit combinational logic (i.e., no explicit binding to
hardware or to primitive gates)
 Verilog counterparts of three common
descriptions of combinational logic
• All the following describe level sensitive behavior
- i.e., variables are updated immediately when an input changes
 Latches and Level Sensitive circuits in
Verilog
• Note: A set of continuous assignment statements has implicit
feedback if a variable in one of the RHS expressions is also the target
of an assignment.
• Eg: Cross coupled NAND gate

• However, the synthesis tools do not accommodate this form of

feedback.
• They support feedback implied by a continuous assignment in which
RHS exp uses a conditional operator.
Transparent Latch
• Follows the data input while the latch is enabled, but otherwise will
hold the value it had when the enable input was de-asserted.
 Simulation results of transparent Latch

• When feedback is used in a continuous assignment statement with a

conditional operator,
-a synthesis tool will infer the functionality of a latch and its hardware implementation
The Latch model with nested conditional
operators
•Active- low reset & enable
Simulation results
Summary
•Continuous assignments are convenient for modeling
- small Boolean expressions,
- three-state behavior and
- Transparent latches

•Hence, for larger designs, it is worthwhile to consider other

language constucts
- Which describe edge sensitive as well as level sensitive behavior.
 Cyclic behavioral models of Flip-flops and
Latches
• Continuous assignment statements are limited to modeling
level-sensitive behavior combinational logic and transparent
latches.
- hence, they can’t model edge-sensitive circuits, like flip-flops
• Verilog uses a cyclic behavior to model edge-sensitive
functionality.
- Using Procedural statements to generate the values of
variables, execute to extract, manipulate, and store variables in
memory.

• Cyclic behaviors: They do not expire after their last Procedural

statement has executed; instead, they re-execute.

• Cyclic behaviors are used to model (and synthesize) both level

sensitive and edge – sensitive (synchronous) behavior (flip-flops).
Example – D - Flip flop
• The keyword “always” declares a cyclic behavior corresponding to
edge triggered flip-flop.

• At every rising edge of clk – behavior’s procedural statements execute

• In above example,
<= is a non blocking, or concurrent, assignment operator
= is also a procedural assignment operator

•A variable that is assigned value by a

procedural-assignment operator in a single-pass or cyclic
behavior must be a declared register-type variable (not a
net)
Cyclic behavior and Edge Detection
• A cyclic behavior is activated at the beginning of simulation
- And it will execute its associated procedural statements.
- Subjected to timing control imposed by delay control (# operator) and event
control expressions (@ operator)

• The Verilog keyword posedge qualifies event control expression

- to execute its procedural statements only when rising edge of the assignment
signal has occurred.
- Similar is other one called negedge (falling edge)
Example: D-flipflop
•This coding discipline allows a synthesis tool to correctly
1. Identify the synchronizing signal (its name and its location in the
event control expression are not predetermined)
2. Infer the need for a flip-flop to hold the value of q between the
active edges of the synchronizing signal.

• Note: The Verilog language allows a mixture of level-sensitive and

edge-qualified variable in an event control expression,
- But synthesis tool do not support such models of behavior.
Example: Transparent Latch
 A Comparison of Styles for Behavioral
Modeling
•Here, we compare simpler and more readable
alternatives that also use continuous
assignments
•And then we contrast modeling styles based on
1. Continuous Assignment Models
2. Register Transfer Level (RTL) models
3. Algorithms based models
Continuous assignment models
• It describes Level-sensitive behavior.
• Continuous assignments execute concurrently with each other, with
gate-level primitives, and with all of the behaviors in a description.

• {} is a Verilog concatenation operator

• Continuous assignment statements and the relational operators
32-bit Comparator
Dataflow/RTL Models
• Describes concurrent operations on signals
4-bit Serial Shift Register
Verilog code
Incorrect model of 4-bit Serial Shift Register

•A
• Procedural assignments are called blocked assignments
- as it must complete execution (i.e., write results to memory) before the next
statement in the behavior can execute.
- This sets the stage for expression substitution.
• Failure to appreciate the effects of expression substitution can lead to
incorrect models
• An alternative dataflow model uses concurrent procedural
assignments also called, non blocking assignments in a cyclic
behavior.
Example: 4-bit serial shift register with non
blocking assignment operators (<=)
 Algorithm based Models
• Described by a circuit’s input – output algorithms
• The algorithm prescribes a sequence of procedural assignments
within a cyclic behavior.
• The algorithm described by the model doesn’t have explicit binding to
hardware
- Which makes challenging for a synthesis tool, because it must
perform architectural synthesis.
• NOTE: Assignment statements in dataflow (RTL) model execute
concurrently (in parallel), where as the statements in algorithm model
execute sequentially, without an explicit architecture
Example: Algorithm based model
Synthesis results derived from compare_2_algo
 Port Names: A matter of style
• To ensure that only constructs supported by synthesis tools are used.
• The ports will be ordered in the following sequence
- Data path bidirectional signals
- Bidirectional control signals
- Data path outputs
- Control outputs
- Data path inputs
- Control inputs
- Synchronizing signals
 Simulation with Behavioral Models
• Simulator behaves differently, when a cyclic process is activated
• Their associated statements execute sequentially, in the same step,
until the simulator encounters either
- A delay control operator (#)
- An event control operator (@)
- A wait construct, or
- The last statement
• Models of primitives and continuous assignments cant’t suspend
themselves, instead they execute immediately
• Cyclic behavior can suspend themselves
• Good modeling will prevent endless execution happening. Otherwise
reach for the OFF button.

• If multiple behaviors are activated at the same time step, the order in
which the simulator executes them is indeterminate.

• Synthesis tools will warn of such features in the model