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Design of a Two-Bit Magnitude Comparator Based on Pass Transistor,

Transmission Gate and Conventional Static CMOS Logic

Conference Paper · July 2020

DOI: 10.1109/ICCCNT49239.2020.9225501

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 IEEE - 49239

Design of a Two-Bit Magnitude Comparator Based

on Pass Transistor, Transmission Gate and
Conventional Static CMOS Logic
Samiha Lubaba K. M. Faisal
Department of Electrical and Computer Engineering Department of Electrical and Computer Engineering
North South University North South University
Dhaka, Bangladesh Dhaka, Bangladesh
samihalubaba@[Link] kmfaisal63@[Link]

Moumita Sadia Islam Mehedi Hasan

Department of Electrical and Computer Engineering Jack-Kilby VLSI Lab
North South University University of Science and Technology, Chittagong
Dhaka, Bangladesh Chattogram, Bangladesh
prituislam@[Link] mehedi.hasan01@[Link]

Abstract—Since there is a swift technological progress going [16-17]. In addition, instruction sorting in microprocessors
on in the recent years, semiconductor industry evolved to such requires MC [18]. Hence, because of having significant
an extend that requirement of optimal performance in demand in VLSI design, an effective MC design will bring
electronic circuits have become essential. Therefore, there is about great performance escalation of ALU.
high requirement of energy efficient fast circuit designs in
modern Integrated Circuits (IC). Comparison of two binary In this research, a hybrid two-bit magnitude comparator
digits is one of the fundamental arithmetic operations in using PTL, TGL and C-CMOS logic has been presented.
Arithmetic Logic Units (ALU) of ICs and processors. A hybrid Performance of the proposed hybrid two-bit MC has been
design approach for implementing a two-bit Magnitude compared with the existing designs to validate its
Comparator (MC) has been proposed in this work. The hybrid effectiveness. Cadence design tools have been used in this
design consists of three different logic techniques namely: (a) research for performance evaluation in standard 90 nm
Pass Transistor Logic (PTL), (b) Transmission Gate Logic technology node.
(TGL) and (c) Conventional Static CMOS Logic (C-CMOS
logic). The effectiveness of the proposed design has been II. LITERATURE REVIEW OF TWO-BIT MAGNITUDE
compared with 6 state of art two-bit magnitude comparators COMPARATOR DESIGNS
using Cadence tools in 90 nm technology node. The proposed
design showed best perormacne in case of delay and Power Due to wide area of applications, MC has become a prime
Delay Product (PDP) which proved the effectiveness of the subject of interest for which numerus two-bit MC designs
design, Moreover, power consumption of the design is also low have been implemented by researchers [19-20]. Two-bit MC
which makes it highly usable for portable devices that requires using PTL utilizes 40 CMOS transistors is reported in [21].
low-power consumption. The major disadvantage associated with this sort of design is
degradation of voltage since N-MOS only passes strong logic
Keywords—magnitude comparator, binary comparator, pass 0 (zero). Hence, PTL MC suffers from low driving power and
transistor logic, transmission gate, conventional static CMOS has high power consumption.
logic, gate diffusion input technique.
Later on, in order to overcome the disadvantages of PTL,
I. INTRODUCTION C-CMOS logic has been developed. This design employs
complementary set of N-MOS and P-MOS transistors for full-
Due to rapid elcalation in usage of portable devices,
swing logic implementation. Two-bit MC design using C-
demand for high-performance circuits in electronic devices
CMOS logic has been reported in [22]. Transistor count (TC)
have become a crucial need [1-4]. Modern highly complex
for this design is 66. This high TC makes the input impedance
electronic devices requires ICs and processors that have high
high which accounts for high delay. However, in case of
efficiency and speed [5-6]. Therefore, efficient design
driving power, the design is dignificantly robust.
methologies are highly demanded in order to cope up with the
expected performance parameters of modern devices [7-9]. In TGL do not incorporate the weakness of voltage
order to meet the performance requirements, many efficient degradation unlike PTL. However, high TC in TGL results in
design techniques have been developed and implemented [10- high area in silicon chip. Moreover, driving power is also an
12]. issue in this sort of design. Two-bit MC using TGL is reported
in [23] which employs 66 transistors.
MC in digital ALU is the component used for comparing
two binary digits or numbers [13]. By comparing two binary Two-bit MC design employing Full Adder (FA) cell is
numbers, it provides output if they are greater than or equal to reported in [24]. The design employed 30 transistors and used
one-another [14-15]. This component in ALU is highly FA design in [25]. TC of this MC is low while compared to
utilized in parallel processing and digital signal processing the previously mentioned PTL and C-CMOS MCs.
11th ICCCNT 2020 July 1-3,
2020 - IIT – Kharagpur
Kharagpur, India
 IEEE - 49239
Gate Diffusion Input (GDI) method enables designers to hybrid XNOR gates in order to generate the internal node
build VLSI circuits with less TC compared to other design signals. Usage of C-CMOS method in the initial circuitry is
methods [26-27]. Major drawback of this design is the voltage deliberately avoided in order to reduce the high-input
degradation unlike PTL. Two-bit MC using GDI technique in impedance of C-CMOS design. In this way, the RC time
[28] only requires 28 transistors which is the lowest TC constants of the circuits become low. Due to this low RC time
reported in this research. constant, the input signals can quickly pass along the circuit
components for which delay has been reduced significantly.
Hybrid logic style based two-bit MC in [29] requires 46
transistors. The design used hybrid logic based AND and The output signals generated from the hybrid XNOR gates
XNOR gates for internal logic signal generation. Then the are later passed onto C-CMOS based circuit which provides
internal signals are send to C-CMOS based circuit for full swing output signals having high driving power. C-CMOS
generating output terms. Major advantage of this design lies logic is intentionally placed in generating the output signals in
in the intelligent use of C-CMOS method based circuit in the order to provide robustness and driving power to the circuit.
outer signal generation [30].
C. Circuit Implementation
Dynamic logic based MC designs are also available in Since Fig. 1 implies that MC implementation would
literature [31-32]. However, the porposed and the other MCs require AND and XNOR gates, finding the perfect AND and
mentioned are static CMOS based for which comparison in XNOR gates would result in performance increment of the
this research are conducted only among static CMOS based proposed two-bit MC. Various AND and XNOR gates are
designs. available in [33-39]. Logic gates in [33] don not provide full
III. PROPOSED DESIGN swing operarion. As per simulation results seen in [39], logic
gates in [39] is highly efficient and would bring about great
To have descriptive analysis of proposed two-bit MC cell, perfromacne enhancement if applied to the proposed MC.
design methodology has been described using the following Hence, logic gates designed in [39] have been chosen in order
sub-sections. to implement the porposed MC circuit diagram.
TABLE I. TABLE OF OPERATION OF A TWO-BIT MAGNITUDE For AND operation, C-CMOS based design has been
COMPARATOR utilized. For ALB and AGB, XNOR operation is required.
Inputs Outputs This XNOR gate can be designed by interchanging 𝐴 and 𝐴̅ in
A1 , B1 A0 , B0 AGB ALB AEB the XOR gate represented in [39]. After employing the cirucits
A 1 = B1 A 0 = B0 0 0 1 for generating XNOR singnals, C-CMOS circuits has been
A 1 = B1 A0 >B0 1 0 0 developed for the Boolean expressions in (1) and (2). Full
A 1 = B1 A0 <B0 0 1 0 circuit diagram has been depicted in Fig. 2.
A 1 > B1 X 1 0 0
A 1 < B1 X 0 1 0
AGB: A>B (A is greater than B)
ALB: A<B (A is Smaller than B)
AEB: A= B (A and B are equal)
X= Don’t care condition

A. Understanding Logic Operation of Two-Bit MC:

In order to be able to design a two-bit MC, at first, it is
necessary to fully understand its logic of operation. Operation
technique of two-bit MC is conveyed using Table I. In Table
I, the binary numbers required to be compared are denoted as
A and B. The most significant bits are represented by A1 , B1.
Least significant bits of the binary numbers A and B are
denoted by A0 and B0 respectively.
Operation conveyed in Table I can be written using
Boolean Algebra in order to express the operation of two-bit
MC using Boolean Equations. The equations are Fig. 1. Block diagram of proposed magnitude comparator.

AGB = A1 + A0 XN1 (1) IV. SIMULATION RESULT ANALYSIS, COMPARISON AND

ALB = B1 + B0 XN1 (2) DISCUSSION
AEB = XN0 XN1 (3)
In order to compared the porposed MC with the existing
Here, XN0= A0 XNOR B0 and XN1= A1 XNOR B1 ones described in section II, circuit simulation has been
Hence, it is clear from the above mentioned discussions conducted in 90 nm CMOS process. Cadence CAD tools have
that implementation of the two-bit MC would require AND been utilized for this purpose. All designs have been simulated
and XNOR operations. Later, a complex logic gate would be for 1.0 V supply voltage so that the designs get similar
required to implement Boolean equations stated in (1) and (2) environment for comparison. Obtained simulation results
have been presented in Table II and Fig. 3-5.
B. Block Diagram
The simulation results in Table II states that the porposed
As per observations made from Table I and eq. 1-3,
MC is highly efficient in case of propagation delay. PTL based
proposed 2-bit MC operation process is expressed using Fig. MC has quite satisfying speed. Compared to the other designs,
1. Initially, the inputs are passed onto the TGL and PTL based
GDI based MC in [28] has very high delay.
11th ICCCNT 2020 July 1-3,
2020 - IIT – Kharagpur
Kharagpur, India
 IEEE - 49239
Power consumption of the design is also low compared to 15.116
16
the designs in [21-23, 29]. Only MC design in [28] has less 13.589
14
average power than the two-bit MC in this research work. 12 11.031

Power (W)
However, there is a problem associated with GDI based MC 10
in [28]. The design only consists of circuits for AEB and AGB. 7.783 7.801 7.792
8
Circuit for ALB is missing in this design. Adding this circuit 6
would add more transistor to the overall design and will result 4
in increased power dissipation. 2
In case of PDP, porposed design achieved the best position 0
which proved its effectiveness. Although having satisfying
delay, PTL based design has the highest power dissipation for
which its PDP is high. GDI based design obtained highest
PDP due to its high delay. 2-Bit MC Cells
V. CONCLUSION
Fig. 3. Simulation results of power dissipation.
This works presented the design of a two-bit MC. The
proposed MC utilized PTL and TGL based logic circuits for
0.6
generating the initial signals from the inputs which reduced
0.513
TC. Output terminals consisted C-CMOS circuits to provide 0.5
robustness and driving power. For comparison purpose, 0.356
0.4

Delay (ns)
porposed MC has been simulated in 90 nm CMOS process 0.311
0.287
along with the existing ones. The porposed MC achieved quite 0.3
satisfying performance parameters which proved its 0.212 0.192
0.2
effectiveness. Due to the high performance obtained by the
porposed design, it is proved that the design is highly useful 0.1
for designing modern microprocessors [40-43]. 0
TABLE II. SIMULATION RESULT OF MAGNITUDE COMPARATORS
Comparator Ref no. TC Power Delay PDP
logic style (c) (ns) (fJ)
PTL [21] 40 11.031 0.287 3.166 2-Bit MC Cells
C-CMOS logic [22] 66 13.589 0.311 4.226
TGL MC [23] 66 15.116 0.356 5.381 Fig. 4. Simulation results of propagation delay.
FA based MC [24] 30 Failed
GDI Method [28] 28 7.783 0.513 3.992
6
Hybrid [29] 46 7.802 0.212 1.654 5.381
Proposed …. 46 7.792 0.192 1.496 5 4.226 3.992
4
PDP (fJ)

3.166
3
1.654 1.496
2
1
0

2-Bit MC Cells

Fig. 5. Simulation results of PDP.

REFERENCES
[1] M. Hasan, M. H. Anik and S. Islam, "Microcontroller Based Smart
Home System with Enhanced Appliance Switching Capacity," 2018
Fifth HCT Information Technology Trends (ITT), Dubai, United Arab
Emirates, 2018, pp. 364-367.
[2] H. Naseri and S. Timarchi, "Low-Power and Fast Full Adder by
Exploring New XOR and XNOR Gates," in IEEE Transactions on
Very Large Scale Integration (VLSI) Systems, vol. 26, no. 8, pp. 1481-
1493, Aug. 2018.
[3] R. F. Mirzaee, M. H. Moaiyeri, H. Khorsand and K. Navi, “A New
Robust and Hybrid High-Performance Full Adder Cell,” Journal of
Circuits, Systems and Computers, vol. 20, no. 4, pp. 641-655, 2011.
Fig. 2. Proposed two-bit magnitude comparator. [4] M. Hasan, M. H. Anik, S. Chowdhury, S. A. Chowdhury, T. I. Bilash,
S. Islam, “Low-cost Appliance Switching Circuit for Discarding

11th ICCCNT 2020 July 1-3,

2020 - IIT – Kharagpur
Kharagpur, India
 IEEE - 49239
Technical Issues of Microcontroller Controlled Smart [23] Anjuli, Satyajit Anand: ‘Two-bit Magnitude Comparator Design Using
Home,” International Journal of Sensors and Sensor Networks, vol. 7, Different Logic Styles’ International Journal of Engineering Science
no. 2, pp. 16-22, 2019. Invention, vol. 2 , no. 1, pp. 13-24, 2013.
[5] M. Hasan, A. Z. Dipto, M. S. Islam, A. Sorwar, S. Alam, “A Smart [24] A. Sharma and P. Sharma, "Area and power efficient 4-bit comparator
Semi-Automated Multifarious Surveillance Bot for Outdoor Security design by using 1-bit full adder module," in Proc. 2014 International
Using Thermal Image Processing,” Advances in Networks. vol. 7, no. Conference on Parallel, Distributed and Grid Computing, Solan, 2014,
2, pp. 21-28, 2019. pp. 1-6.
[6] M. F. Karin, K. S. Noor and H. U. Zaman, "Hardware based design and [25] H. T. Bui, Y. Wang, and Y. Jiang, “Design and analysis of low-power
implementation of a bottle recycling machine using FPGA," 2016 10-transistor full adders using novel XOR-XNOR gates,” IEEE Trans.
IEEE Conference on Systems, Process and Control (ICSPC), Bandar Circuits Syst. II, Analog Digit. Signal Process., vol. 49, no. 1, pp. 25–
Hilir, 2016, pp. 43-46. 30, Jan. 2002.
[7] M. Hasan, P. Biswas, M. T. I. Bilash and M. A. Z. Dipto, "Smart Home [26] A. Morgenshtein, M. Moreinis and R. Ginosar, "Asynchronous gate-
Systems: Overview and Comparative Analysis," 2018 Fourth diffusion-input (GDI) circuits," in IEEE Transactions on Very Large
International Conference on Research in Computational Intelligence Scale Integration (VLSI) Systems, vol. 12, no. 8, pp. 847-856, Aug.
and Communication Networks (ICRCICN), Kolkata, India, 2018, pp. 2004.
264-268. [27] A. Morgenshtein, A. Fish, and I. A. Wagner, "Gate-Diflusion Input
[8] N. H. E. Weste and D. M. Harris, CMOS VLSI Design: A Circuits and (GDI): A Power-Etlicient Method for Digital Combinatorial Circuits,"
Systems Perspective, 4th ed. Boston, MA, USA: Addison-Wesley, IEEE Transactions on Very Large Scale Integration (VLSI) systems,
2010. Vol. 10, No. 5, pp.566-581, October 2002.
[9] R. Hossain, M. Ahmed, H. U. Zaman and M. A. Nazim, "A [28] A. Gupta, M. Khatri, S. K. Rajput, A. Mehra and S. Bathla, "Design of
comparative study of various simulation software for design and low power magnitude comparator," in Proc. 2017 7th International
analysis of operational amplifier based integrator circuits," 2017 8th Conference on Cloud Computing, Data Science & Engineering -
Annual Industrial Automation and Electromechanical Engineering Confluence, Noida, 2017, pp. 754-758.
Conference (IEMECON), Bangkok, 2017, pp. 278-282. [29] M. Hasan, U. K. Saha, M. S. Hossain, P. Biswas, M. J. Hossein and M.
[10] M. Hasan, M. J. Hossein, U. K. Saha and M. S. Tarif, "Overview and A. Z. Dipto, "Low Power Design of a Two Bit Mangitude Comparator
Comparative Performance Analysis of Various Full Adder Cells in 90 for High Speed Operation," 2019 International Conference on
nm Technology," 2018 4th International Conference on Computing Computer Communication and Informatics (ICCCI), Coimbatore,
Communication and Automation (ICCCA), Greater Noida, India, 2018, Tamil Nadu, India, 2019, pp. 1-4.
pp. 1-6. [30] M. Hasan, U. K. Saha, A. Sorwar, M. A. Z. Dipto, M. S. Hossain and
[11] S. A. Karim and H. U. Zaman, "Simulation and visualization of carrier H. U. Zaman, "A Novel Hybrid Full Adder Based on Gate Diffusion
trajectories in distributed MIGFET devices a simulation of newtonian Input Technique, Transmission Gate and Static CMOS Logic," 2019
particles at small dimensions," 2016 19th International Conference on 10th International Conference on Computing, Communication and
Computer and Information Technology (ICCIT), Dhaka, 2016, pp. 139- Networking Technologies (ICCCNT), Kanpur, India, 2019, pp. 1-6.
144. [31] A. Gupta, M. Khatri, S. K. Rajput, A. Mehra and S. Bathla, "Design of
[12] S. Kang and Y. Leblebici, CMOS Magnitude Integrated Circuit, low power magnitude comparator," in Proc. 2017 7th International
Analysis and Design, 3rd Ed, 2003. Conference on Cloud Computing, Data Science & Engineering -
[13] P. Chuang, D. Li and M. Sachdev, "A Low-Power High-Performance Confluence, Noida, 2017, pp. 754-758.
Single-Cycle Tree-Based 64-Bit Binary Comparator," IEEE [32] P. Corsonello, S. Perri and G. Cocorullo, "Performance comparison
Transactions on Circuits and Systems II: Express Briefs, vol. 59, no. 2, between static and dynamic CMOS logic implementations of a
pp. 108-112, Feb. 2012 pipelined square-rooting circuit," in Proc. IEE Proceedings - Circuits,
[14] S. A. Karim and H. U. Zaman, "Qualitative analysis of an equivalent Devices and Systems, vol. 147, no. 6, pp. 347-355, Dec. 2000.
full adder circuit using MIGFET: An alternative approach to full adder [33] H. T. Bui, Y. Wang, and Y. Jiang, “Design and analysis of low-power
circuit via direct truth table implementation," 2016 International 10-transistor full adders using novel XOR-XNOR gates,” IEEE Trans.
Conference on Microelectronics, Computing and Communications Circuits Syst. II, Analog Digit. Signal Process., vol. 49, no. 1, pp. 25–
(MicroCom), Durgapur, 2016, pp. 1-6. 30, Jan. 2002.
[15] G. Sharma, H. Arora, J. Chawla and J. Ramzai, "Comparative analysis [34] P. Bhattacharyya, B. Kundu, S. Ghosh, V. Kumar and A. Dandapat,
of a 2-bit magnitude comparator using various high performance "Performance Analysis of a Low-Power High-Speed Hybrid 1-bit Full
techniques," 2015 International Conference on Communications and Adder Circuit," IEEE Transactions on Very Large Scale Integration
Signal Processing (ICCSP), Melmaruvathur, 2015, pp. 0079-0083. (VLSI) Systems, vol. 23, no. 10, pp. 2001-2008, Oct. 2015.
[16] M. Drozdowski, Scheduling for Parallel Processing, 1st ed. London, [35] M. Shoba and R. Nakkeeran, “GDI based full adders for energy
United Kingdom, Springer-Verlag London, 2009. efficient arithmetic applications,” Engineering Science and
[17] D. Marković, R. W. Brodersen, DSP Architecture Design Essentials, Technology, an International Journal, vol. 19, no. 1, pp. 485-496,
1st Ed, New York, NY, 2012. 2016.
[18] Vijaya Shekhawat, Tripti Sharma and Krishna Gopal Sharma, “2-Bit [36] C. H. Chang, J. M. Gu, M. Zhang, “A Review of 0.18-μm Full Adder
Magnitude Comparator using GDI Technique” in Proc. IEEE Performances for Tree Structured Arithmetic CIrcuits” IEEE
International Conference on Recent Advances and Innovations in Transactions on Very Large Scale Integr. (VLSI) Syst., vol. 13, no. 6,
Engineering (ICRAIE-2014), 2014, Jaipur, India. pp.1-5. pp. 686–695, Jun. 2005.
[19] M. Hasan, M. S. Islam, M. R. Ahmed, “Performance Improvement of [37] S. Goel, M. A. Elgamel and M. A. Bayoumi, "Novel design
4-Bit Static CMOS Carry Look-Ahead Adder Using Modified Circuits methodology for high-performance XOR-XNOR circuit design," 16th
for Carry Propagate and Generate Terms,” Science Journal of Circuits, Symposium on Integrated Circuits and Systems Design, 2003. SBCCI
Systems and Signal Processing, vo. 8, no. 2. pp. 76-81, 2019. 2003. Proceedings., Sao Paulo, Brazil, 2003, pp. 71-76.
[20] M. Hasan, P. Biswas, M. S. Alam, H. U. Zaman, M. Hossain and S. [38] S. Wairya, G. Singh, Vishant, R. K. Nagaria and S. Tiwari, "Design
Islam, "High Speed and Ultra Low Power Design of Carry-Out Bit of analysis of XOR (4T) based low voltage CMOS full adder
4-Bit Carry Look-Ahead Adder," 2019 10th International Conference circuit," 2011 Nirma University International Conference on
on Computing, Communication and Networking Technologies Engineering, Ahmedabad, Gujarat, 2011, pp. 1-7.
(ICCCNT), Kanpur, 2019, pp. 1-5. [39] M. Hasan, M. J. Hossein, M. Hossain, H. U. Zaman and S. Islam,
[21] S. Bhuvaneswari, R. Prabakaran and N. J. R Muniraj, “Efficient "Design of a Scalable Low-Power 1-Bit Hybrid Full Adder for Fast
Implementation of 2-Bit Magnitude Comparator Using PTL,” Computation," in IEEE Transactions on Circuits and Systems II:
International Journal of Advance Research, Ideas And Innovations in Express Briefs, vol. 67, no. 8, pp. 1464-1468, 2020.
Technology, vol. 3, no. 6, pp. 140-144, 2017. [40] A. Morgenshtein, A. Fish and I. A. Wagner, "Gate-diffusion input
[22] D. N. Mukherjee, S. Panda and B. Maji, "Design of low power 2-bit (GDI): a power-efficient method for digital combinatorial circuits," in
magnitude comparator," 2017 Devices for Integrated Circuit (DevIC), IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
Kalyani, 2017, pp. 103-109. vol. 10, no. 5, pp. 566-581, Oct. 2002.

11th ICCCNT 2020 July 1-3,

2020 - IIT – Kharagpur
Kharagpur, India
 IEEE - 49239
[41] M. Hasan, H. U. Zaman, M. Hossain, P. Biswas, S. Islam, “Gate International Conference on Logistics, Informatics and Service
diffusion input technique based full swing and scalable 1-bit hybrid full Sciences, Budapest, Hundary, 2020.
adder for high performance applications,” Engineering Science and [43] S. Hasan, F. Faisal, S. Sabrin, Z. Tong, M. Hasan, D. Debnath, M. S.
Technology, An International Journal, 2020. Hossain, A. H. Siddique, J. Alam, “A Simplified Approach to Develop
[42] L Q. Hu, A. Yadav, H. Liu, S. Azam, A. Karim, B. Shanmugam, A. H. Low Cost Semi-Automated Prototype of a Wheelchair,” University of
Siddique, M. Hasan, “Analysis of Lemon Company’s Cross-Border E- Science and Technology Annual (USTA), 2020.
Commerce Logistics Distribution Mode Selection,” 2020 10th

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2020 - IIT – Kharagpur
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