INTRODUCTION TO

WAFER TO CHIP DESIGN

FABRICATION PROCESS
PSG INSTITURE OF TECHNOLOGY AND APPLIED RESEARCH,
25 NOVEMBER 2024
PRESENTED BY:
HARSHA P
VENNILA A
DEEKSHA R
NEYA S
 Introduction to
Semiconductor Fabrication

THE MANUFACTURING PHASE OF AN INTEGRATED CIRCUIT CAN BE DIVIDED INTO TWO STEPS.
THE FIRST,WAFER FABRICATION, IS THE EXTREMELY SOPHISTICATED AND INTRICATE
PROCESS OF MANUFACTURING THE SILICON CHIP. THE SECOND, ASSEMBLY, IS THE HIGHLY
PRECISE AND AUTOMATED PROCESS OF PACKAGING THE DIE.

THOSE TWO PHASES ARE COMMONLY KNOWN AS “FRONT-END” AND “BACK-END”. THEY
INCLUDE TWO TEST STEPS: WAFER PROBING AND FINAL TEST.
SAND

SILICON

WAFER

CHIP
Semiconductor Manufacturing Process - Steps
Involved
Silicon Wafers as starting material

The starting material for modern

Manufacturing process
integrated circuits is very-high-
purity, single-crystal [Link]
material is initially grown as a
single crystal ingot. It takes the
shape of a steel-gray solid
cylinder 10 cm to 30 cm in diameter
.
This crystalis then sawed (like a
loaf of bread) to produce circular
wafers that are 400µm to 600µm
thick.
The surface of the wafer is then
polished to a mirror finish using
chemical and mechanical polishing
(CMP) techniques.
Wafer properties and doping
The basic electrical and mechanical properties of the wafer depend
on :
(These variables are strictly controlled during crystal growth. This
allows the alteration of the electrical properties of the silicon, in
particular its resistivity)
[Link] orientation of the crystalline structure
[Link] impurity concentrations
[Link] of impurities present.
Depending on the types of impurity, either holes (in p-type silicon)
or electrons (in n-type silicon) can be responsible for electrical
conduction.
Types of doping:
One part of the manufacturing process called diffusion (the other
part being the oxide growth). The second way to dope the silicon is
called ionic implantation. Silicon is the most widely used
semiconductor material, primarily due to its abundance, low cost,
and relatively stable properties at high temperatures.
Oxidation
In oxidation, silicon reacts with oxygen to form silicon dioxide (SiO2)
The oxygen used in the reaction can be introduced either as a high-
purity gas (referred toas a “dry oxidation”) or as steam (forming a
“wet oxidation”).
In general, wet oxidation has a faster growth rate, but dry oxidation
gives better electrical characteristics.
This oxide layer is used as mask during dopant diffusion, as a
junction passivator, as an insulating oxide or as a gate dielectric
in MOS transistor fabrication.
Serves as an insulating layer that blocks leakage current between
circuits. The oxide layer also protects the silicon wafer during the
subsequent ion implantation and etching processes. In other words,
the silicon dioxide layer serves as a reliable shield during the
semiconductor manufacturing process.
PHOTOLITHOGRAPHY
PHOTOLITHOGRAPHY
Photoresist - Photosensitive layer coated on wafer surface
using a spin-on technique
Photographic plate with drawn patterns - Selectively
expose the photoresist under deep ultraviolet illumination
(UV)
The exposed areas will become softened (for positive
photoresist) which can then be removed using a chemical,
causing the mask pattern to be duplicated on the wafer
The patterned photoresist layer can be used as an
effective masking layer to protect materials below from
wet chemical etching.
After the etching step(s), the photoresist is stripped away, STEP-AND-REPEAT REDUCTION
TECHNIQUE TO FACILITATE THE MASS
leaving behind a permanent pattern of the photomask on PRODUCTION OF INTEGRATED CIRCUITS

the wafer surface

ETCHING
Wet etching(Isotropic etching): Chemical
solutions remove the exposed photosensitive
layers in all directions(e.g., HF acid is used
to etch SiO2, KOH for Si, and H3PO4 for Al.
In wet etching, an undercut will occur
depending on the thickness of the layer, WET ETCHING
hence changing the original pattern.
RIE(reactive ion etching) dry etching can be
used if exact dimension is critical.
This method is essentially a directional
bombardment of the exposed surface using a
corrosive gas (or ions).
The cross-section of the etched layer is
usually highly directional (anisotropic
etching) and has the same dimension as the DRY ETCHING
photoresist pattern.
ION IMPLANTATION
Introduces impurities into the semiconductor crystal
An ion implanter produces ions of the desired dopant,
accelerates them by an electric field, and allows them to
strike the semiconductor surface.
The ions become embedded in the crystal lattice.
The depth of penetration is related to the energy of the
ion beam, which the accelerating field voltage can
control.
The quantity of ions implanted can be controlled by
Doping
varying the beam current (flow of ions). atoms
Since both voltage and current can be accurately
measured and controlled, ion implantation results in
impurity profiles that are much more accurate and
reproducible than can be obtained by diffusion.
Normally it is used when accurate control of the doping
profile is essential for device operation.
DIFFUSION
Diffusion is a process by which atoms move from a high-
concentration region to a low-concentration region.
This is another method to introduce impurity atoms (dopants)
into silicon to change its resistivity.
The rate at which dopants diffuse in silicon is a strong
function of temperature.
Diffusion of impurities is usually carried out at high
temperatures (1000–1200°C) to obtain the desired doping
profile.
When the wafer is cooled to room temperature, the impurities
are essentially “frozen” in position.
The depth to which the impurities diffuse depends on both
the temperature and the processing time.
The most common impurities used as dopants are boron (p-
type), phosphorus (n-type), and arsenic (n-type).
These dopants can be effectively masked by thin silicon
dioxide layers.
DIFFERENCE BETWEEN DIFFUSION AND ION IMPLANTATION

DIFFUSION ION IMPLANTATION

Performed at room temperature, followed by

Uses high-temperature heating (1000°C–1200°C).
annealing.

Limited control over dopant depth and Highly precise control over depth and
concentration. concentration.

Gradual concentration gradient, highest at the Sharp concentration profile with a peak at a
surface. specific depth.

Causes minimal lattice damage. Causes lattice damage; requires annealing to repair.

Best for deep junctions and broad doping. Ideal for shallow junctions and advanced devices.
CHEMICAL VAPOR DEPOSITION

Chemical vapor deposition (CVD) is a process by which gases or vapors are

chemically reacted, leading to the formation of solids on a substrate.
CVD can be used to deposit various materials on a silicon substrate
including SiO2 ,Si3 N4 , polysilicon, and so on.
The advantage of a CVD layer is that the oxide deposits at a faster rate and
a lower temperature (below 500°C).
If the reaction temperature is high enough (above 1000°C), the layer deposited will be a crystalline layer . Such a
layer is called an epitaxial layer, and the deposition process is referred to as epitaxy.
At lower temperatures, or if the substrate surface is not single-crystal silicon, the atoms will not be able to aligned
along the same crystalline direction. Such a layer is called polycrystalline silicon (poly Si), since it consists of many
small crystals of silicon aligned in random fashion.
Polysilicon layers are normally doped very heavily to form highly conductive regions that can be used for electrical
interconnections.
PLANARIZATION – CHEMICAL MECHANICAL POLISHING (CMP)

Planarization is a flattening or smoothing out of the wafer surface topography.

Chemical mechanical polishing (CMP) is a powerful fabrication technique that uses
chemical oxidation and mechanical abrasion to remove material and achieve very high
levels of planarity.
Chemical mechanical planarization has been widely applied to selectively remove
materials for topography planarization and device structure formation in
semiconductor manufacturing.
The selective material removal is achieved by using chemical reaction and mechanical
abrasion
During polishing, chemical reaction products and mechanical wear debris are
generated. Slurry particles and polishing byproducts are pressed onto wafer surface.
Post-CMP cleaning is required to remove particles, organic residues, and metallic
contaminants from wafers with different surface, chemical, and mechanical properties
in various geometric features, without generating scratches, water marks, surface
roughness, corrosion, and dielectric constant shift.
METALLIZATION AND INTERCONNECTS

The purpose of metallization is to interconnect the various components

(transistors, capacitors, etc.) to form the desired integrated circuit.
Metallization involves the deposition of a metal over the entire surface
of the silicon. The required interconnection pattern is then selectively
etched.
The metal layer is normally deposited via a sputtering process.

A pure metal disk (e.g., 99.99% aluminum target) is placed under an Ar (argon) ion gun inside a vacuum chamber.
The wafers are also mounted inside the chamber above the target.
The Ar ions will not react with the metal, since argon is a noble gas. However, the ions are made to physically
bombard the target and literally knock metal atoms out of the target.
These metal atoms will then coat all the surface inside the chamber, including the wafers. The thickness of the
metal film can be controlled by the length of the sputtering time, which is normally in the range of 1 to 2 minutes.
The metal interconnects can then be defined using photolithography and etching steps.
LAYER-BY-LAYER FABRICATION PROCESS
 ASSEMBLY AND PACKAGING

A finished silicon wafer may contain several hundreds of finished

circuits or chips. A chip may contain from 10 to more than 108
transistors; each chip is rectangular and can be up to tens of millimeters
on a side.
The circuits are first tested electrically (while still in wafer form) using
an automatic probing station. Bad circuits are marked for later
identification. The circuits are then separated from each other (by
dicing), and the good circuits (dies) are mounted in packages(headers).

Finegold wires are normally used to interconnect the pins of the

package to the metallization pattern on the die. Finally, the package is
sealed using plastic or epoxy under vacuum or in an inert atmosphere.
TESTING AND QUALITY CONTROL

ATEs test semiconductor devices by simulating real-world scenarios, applying electrical stimuli, and measuring
responses to ensure functionality, performance, and defect-free manufacturing. Key vendors include Advantest
and Teradyne, offering solutions for digital, mixed-signal, power, RF, and memory tests.

Wafer Test: Wafer Test is also referred to as Chip Probe Test, and it is performed on the die itself
before chip [Link] is performed using Automatic Test Equipment which has the tester and the
needle like structures called the probe cards.
Package Test is the second step of chip production testing which is performed after the wafer is
packaged. Package serves many purposes

Key Metrics:
The quality and efficiency of the production process is assessed by metrics of yield and defect level.
Yield is defined as the fraction of functional and error-free chips produced divided by the maximum
number of chips that could have been produced on a single wafer.
Another parameter that defines the manufacturing quality of the product is defective parts per million
(DPPM). It refers to the maximum number of defective parts shipped for every million parts shipped to
the customer
STEPS OF WAFER TESTING
Visual Inspection:
Technicians look for cracks, scratches, or any irregularities on the surface. This step
is crucial as physical defects will limit the performance of the wafer during wafer
testing.
Wafer Probing:
In this stage, a probe card is used. This equipment tests the electrical properties of the
circuits on the wafer using chip probe techniques. Each tiny area on the wafer (known
as a die) is tested to make sure it conducts electricity properly.
Die Test:
After probing, each individual die on the wafer undergoes a more detailed test. This
die test checks for functional defects in each circuit.
Binning and Dicing:
Based on the test results, individual dies on the wafer are sorted or “binned”
according to their performance. Dies that meet the required specifications are
classified for further processing, while those that don’t are either retested, if possible,
or discarded.
Chip Packaging and Testing:
The functional dies are then packaged, where each die is placed in a protective
casing with external contacts added. This step involves several sub-steps, including
die attachment, wire bonding (or flip-chip bonding), and encapsulation. s. This step
tests the integrated circuit within its package for functionality, performance, and
compliance with the specified standards.
 EMERGING TRENDS IN VLSI FABRICATION
1. FinFET Technology: FinFET, short for “fin field-effect transistor,” is a significant
advancement in chip manufacturing. This three-dimensional transistor design
allows for better control of electrical current flow, resulting in improved performance
and energy efficiency. FinFET technology has been instrumental in overcoming the
limitations of traditional planar transistor designs.

2. Extreme Ultraviolet (EUV) Lithography: EUV lithography is a cutting-edge

technique that uses ultraviolet light with a short wavelength to pattern and etch
intricate circuit patterns onto silicon wafers. This allows for the fabrication of smaller
and more complex chip designs with higher precision and accuracy. EUV
lithography is a key enabler for advanced chip manufacturing.

3. 3D Integration: 3D integration refers to the stacking of multiple chip layers

vertically, enabling the integration of different functionalities within a smaller
footprint. This not only allows for the development of more compact devices but
also enhances performance by reducing interconnect lengths, minimizing power
consumption, and improving thermal management.
BEYOND MOORE’S LAW
Moore’s Law Definition
The exponential increase in the number of transistors on integrated circuits over time is referred to as Moore’s law. According to
this, a chip transistor count tends to double every two years or so, resulting in higher processing power and better performance.

LIMITATIONS:
As transistor sizes near atomic scales, further scaling becomes impractical, threatening the $4 trillion
electronics industry and many sectors reliant on it.
Free performance gains through hardware scaling are no longer guaranteed.

Emerging innovations:
3D integration-----Stacks multiple layers of chips [Link] Improves performance by
reducing data travel distance and increasing density.
Photonic computing-----Uses light (photons) instead of electricity (electrons) for data
[Link] and more energy-efficient, especially for data-heavy tasks.
Neuromorphic systems------Highly efficient for AI tasks like pattern recognition and
[Link]-efficient design for real-time data processing.
Quantum computing -------Specialized tasks: cryptography, AI, protein modeling, and
complex problem-solving.
CONCLUSION

The wafer-to-chip fabrication process is complex but essential for the

production of integrated circuits (ICs).
Understanding the steps such as oxidation, photolithography, doping, and
metallization is crucial to mastering VLSI fabrication.
Emerging technologies like FinFETs, SiGe, and 3D ICs are shaping the
future of semiconductor manufacturing.
Although Moore's Law is reaching its limits, innovation continues to drive
new advancements in the industry.