IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 61, NO.

6, JUNE 2014 2665

An Adjustable-Speed PFC Bridgeless Buck–Boost

Converter-Fed BLDC Motor Drive
Vashist Bist, Student Member, IEEE, and Bhim Singh, Fellow, IEEE

Abstract—This paper presents a power factor corrected (PFC) Power quality problems have become important issues to
bridgeless (BL) buck–boost converter-fed brushless direct current be considered due to the recommended limits of harmonics in
(BLDC) motor drive as a cost-effective solution for low-power supply current by various international power quality standards
applications. An approach of speed control of the BLDC motor
by controlling the dc link voltage of the voltage source inverter such as the International Electrotechnical Commission (IEC)
(VSI) is used with a single voltage sensor. This facilitates the 61000-3-2 [7]. For class-A equipment (< 600 W, 16 A per
operation of VSI at fundamental frequency switching by using the phase) which includes household equipment, IEC 61000-3-2
electronic commutation of the BLDC motor which offers reduced restricts the harmonic current of different order such that the
switching losses. A BL configuration of the buck–boost converter is total harmonic distortion (THD) of the supply current should
proposed which offers the elimination of the diode bridge rectifier,
thus reducing the conduction losses associated with it. A PFC be below 19% [7]. A BLDC motor when fed by a diode bridge
BL buck–boost converter is designed to operate in discontinuous rectifier (DBR) with a high value of dc link capacitor draws
inductor current mode (DICM) to provide an inherent PFC at peaky current which can lead to a THD of supply current of the
ac mains. The performance of the proposed drive is evaluated order of 65% and power factor as low as 0.8 [8]. Hence, a DBR
over a wide range of speed control and varying supply voltages followed by a power factor corrected (PFC) converter is utilized
(universal ac mains at 90–265 V) with improved power quality
at ac mains. The obtained power quality indices are within the for improving the power quality at ac mains. Many topologies
acceptable limits of international power quality standards such of the single-stage PFC converter are reported in the literature
as the IEC 61000-3-2. The performance of the proposed drive is which has gained importance because of high efficiency as
simulated in MATLAB/Simulink environment, and the obtained compared to two-stage PFC converters due to low component
results are validated experimentally on a developed prototype of count and a single switch for dc link voltage control and PFC
the drive.
operation [9], [10].
Index Terms—Bridgeless (BL) buck–boost converter, brushless The choice of mode of operation of a PFC converter is a
direct current (BLDC) motor, discontinuous inductor current critical issue because it directly affects the cost and rating of
mode (DICM), power factor corrected (PFC), power quality.
the components used in the PFC converter. The continuous
I. I NTRODUCTION conduction mode (CCM) and discontinuous conduction mode
(DCM) are the two modes of operation in which a PFC con-

E FFICIENCY and cost are the major concerns in the de-

velopment of low-power motor drives targeting household
applications such as fans, water pumps, blowers, mixers, etc.
verter is designed to operate [9], [10]. In CCM, the current in
the inductor or the voltage across the intermediate capacitor
remains continuous, but it requires the sensing of two voltages
[1], [2]. The use of the brushless direct current (BLDC) motor (dc link voltage and supply voltage) and input side current
in these applications is becoming very common due to features for PFC operation, which is not cost-effective. On the other
of high efficiency, high flux density per unit volume, low main- hand, DCM requires a single voltage sensor for dc link voltage
tenance requirements, and low electromagnetic-interference
control, and inherent PFC is achieved at the ac mains, but at
problems [1]. These BLDC motors are not limited to household
the cost of higher stresses on the PFC converter switch; hence,
applications, but these are suitable for other applications such
DCM is preferred for low-power applications [9], [10].
as medical equipment, transportation, HVAC, motion control,
The conventional PFC scheme of the BLDC motor
and many industrial tools [2]–[4].
drive utilizes a pulsewidth-modulated voltage source inverter
A BLDC motor has three phase windings on the stator and
(PWM-VSI) for speed control with a constant dc link voltage.
permanent magnets on the rotor [5], [6]. The BLDC motor is
This offers higher switching losses in VSI as the switching
also known as an electronically commutated motor because
losses increase as a square function of switching frequency. As
an electronic commutation based on rotor position is used
the speed of the BLDC motor is directly proportional to the
rather than a mechanical commutation which has disadvantages
applied dc link voltage, hence, the speed control is achieved by
like sparking and wear and tear of brushes and commutator
the variable dc link voltage of VSI. This allows the fundamental
assembly [5], [6].
frequency switching of VSI (i.e., electronic commutation) and
offers reduced switching losses.
Manuscript received January 10, 2013; revised March 25, 2013; accepted
June 19, 2013. Date of publication July 24, 2013; date of current version Singh and Singh [11] have proposed a buck–boost converter
December 20, 2013. feeding a BLDC motor based on the concept of constant
The authors are with the Department of Electrical Engineering, Indian dc link voltage and PWM-VSI for speed control which has
Institute of Technology Delhi, New Delhi 110016, India (e-mail: [Link]@
[Link]; bsingh@[Link]). high switching losses. A single-ended primary-inductance con-
Digital Object Identifier 10.1109/TIE.2013.2274424 verter (SEPIC)-based BLDC motor drive has been proposed by

0278-0046 © 2013 IEEE

2666 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 61, NO. 6, JUNE 2014

Fig. 1. Proposed BLDC motor drive with front-end BL buck–boost converter.

Gopalarathnam and Toliyat [12] but has higher losses in VSI TABLE I
C OMPARATIVE A NALYSIS OF P ROPOSED BL B UCK –B OOST C ONVERTER
due to PWM switching and a higher number of current and volt- W ITH E XISTING T OPOLOGIES
age sensors which restricts its applicability in low-cost applica-
tion. Singh and Singh [8] have proposed a Cuk converter-fed
BLDC motor drive with the concept of variable dc link voltage.
This reduces the switching losses in VSI due to the fundamental
switching frequency operation for the electronic commutation
of the BLDC motor and to the variation of the speed by control-
ling the voltage at the dc bus of VSI. A CCM operation of the
Cuk converter has been utilized which requires three sensors
and is not encouraged for low cost and low power rating.
For further improvement in efficiency, bridgeless (BL) con-
verters are used which allow the elimination of DBR in the front
end [13]–[21]. A buck–boost converter configuration is best
suited among various BL converter topologies for applications
requiring a wide range of dc link voltage control (i.e., bucking
and boosting mode). Jang and Jovanović [13] and Huber et al.
[14] have presented BL buck and boost converters, respectively.
These can provide the voltage buck [13] or voltage boost [14], of BLDC motor is achieved by the dc link voltage control
[15] which limits the operating range of dc link voltage control. of VSI using a BL buck–boost converter. This reduces the
Wei et al. [16] have proposed a BL buck–boost converter switching losses in VSI due to the low frequency operation
but use three switches which is not a cost-effective solution. of VSI for the electronic commutation of the BLDC motor.
A new family of BL SEPIC and Cuk converters has been The performance of the proposed drive is evaluated for a wide
reported in the literature [17]–[21] but requires a large number range of speed control with improved power quality at ac mains.
of components and has losses associated with it. Moreover, the effect of supply voltage variation at universal
This paper presents a BL buck–boost converter-fed BLDC ac mains is also studied to demonstrate the performance of
motor drive with variable dc link voltage of VSI for improved the drive in practical supply conditions. Voltage and current
power quality at ac mains with reduced components. stresses on the PFC converter switch are also evaluated for
determining the switch rating and heat sink design. Finally, a
hardware implementation of the proposed BLDC motor drive is
II. P ROPOSED PFC BL B UCK –B OOST C ONVERTER -F ED
carried out to demonstrate the feasibility of the proposed drive
BLDC M OTOR D RIVE
over a wide range of speed control with improved power quality
Fig. 1 shows the proposed BL buck–boost converter-based at ac mains.
VSI-fed BLDC motor drive. The parameters of the BL A brief comparison of various configurations reported in the
buck–boost converter are designed such that it operates in literature is tabulated in Table I. The comparison is carried out
discontinuous inductor current mode (DICM) to achieve an on the basis of the total number of components (switch—Sw ,
inherent power factor correction at ac mains. The speed control diode—D, inductor—L, and capacitor—C) and total number
BIST AND SINGH: ADJUSTABLE-SPEED PFC BRIDGELESS BUCK–BOOST CONVERTER-FED BLDC MOTOR DRIVE 2667

of components conducting during each half cycle of supply

voltage. The BL buck [13] and boost [14], [15] converter
configurations are not suitable for the required application due
to the requirement of high voltage conversion ratio.
The proposed configuration of the BL buck–boost converter
has the minimum number of components and least number of
conduction devices during each half cycle of supply voltage
which governs the choice of the BL buck–boost converter for
this application.

III. O PERATING P RINCIPLE OF PFC BL

B UCK –B OOST C ONVERTER
The operation of the PFC BL buck–boost converter is clas-
sified into two parts which include the operation during the
positive and negative half cycles of supply voltage and during
the complete switching cycle.

A. Operation During Positive and Negative Half Cycles of

Supply Voltage
In the proposed scheme of the BL buck–boost converter,
switches Sw1 and Sw2 operate for the positive and negative half
cycles of the supply voltage, respectively. During the positive
half cycle of the supply voltage, switch Sw1 , inductor Li1 ,
and diodes D1 and Dp are operated to transfer energy to dc
link capacitor Cd as shown in Fig. 2(a)–(c). Similarly, for the
negative half cycle of the supply voltage, switch Sw2 , inductor
Li2 , and diodes D2 and Dn conduct as shown in Fig. 3(a)–(c).
In the DICM operation of the BL buck–boost converter, the
current in inductor Li becomes discontinuous for a certain
duration in a switching period. Fig. 2(d) shows the waveforms
of different parameters during the positive and negative half
cycles of supply voltage.

B. Operation During Complete Switching Cycle

Three modes of operation during a complete switching cycle
are discussed for the positive half cycle of supply voltage as
shown hereinafter.
Mode I: In this mode, switch Sw1 conducts to charge the
inductor Li1 ; hence, an inductor current iLi1 increases in this
mode as shown in Fig. 2(a). Diode Dp completes the input side Fig. 2. Operation of the proposed converter in different modes (a)–(c) for
a positive half cycle of supply voltage and (d) the associated waveforms.
circuitry, whereas the dc link capacitor Cd is discharged by the (a) Mode I. (b) Mode II. (c) Mode III. (d) Waveforms for positive and negative
VSI-fed BLDC motor as shown in Fig. 3(d). half cycles of supply voltage.
Mode II: As shown in Fig. 2(b), in this mode of operation,
switch Sw1 is turned off, and the stored energy in inductor
Similarly, for the negative half cycle of the supply voltage,
Li1 is transferred to dc link capacitor Cd until the inductor is
switch Sw2 , inductor Li2 , and diodes Dn and D2 operate for
completely discharged. The current in inductor Li1 reduces and
voltage control and PFC operation.
reaches zero as shown in Fig. 3(d).
Mode III: In this mode, inductor Li1 enters discontinuous
conduction, i.e., no energy is left in the inductor; hence, current
IV. D ESIGN OF PFC BL B UCK –B OOST C ONVERTER
iLi1 becomes zero for the rest of the switching period. As shown
in Fig. 2(c), none of the switch or diode is conducting in this A PFC BL buck–boost converter is designed to operate in
mode, and dc link capacitor Cd supplies energy to the load; DICM such that the current in inductors Li1 and Li2 becomes
hence, voltage Vdc across dc link capacitor Cd starts decreasing. discontinuous in a switching period. For a BLDC of power
The operation is repeated when switch Sw1 is turned on again rating 251 W (complete specifications of the BLDC motor are
after a complete switching cycle. given in the Appendix), a power converter of 350 W (Po ) is
2668 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 61, NO. 6, JUNE 2014

Fig. 4. Supply current at the rated load on BLDC motor for different values
of input side inductors with supply voltage as 220 V and dc link voltage as 50 V.

The proposed converter is designed for dc link voltage con-

trol from 50 V (Vdc min ) to 200 V (Vdc max ) with a nominal
value (Vdc des ) of 100 V; hence, the minimum and the maxi-
mum duty ratio (dmin and dmax ) corresponding to Vdc min and
Vdc max are calculated as 0.2016 and 0.5025, respectively.

A. Design of Input Inductors (Li1 and Li2 )

The value of inductance Lic1 , to operate in critical conduc-
tion mode in the buck–boost converter, is given as [23]
R(1 − d)2
Lic1 = (3)
2fs
where R is the equivalent load resistance, d is the duty ratio,
and fs is the switching frequency.
Now, the value of Lic1 is calculated at the worst duty ratio
of dmin such that the converter operates in DICM even at very
low duty ratio. At minimum duty ratio, i.e., the BLDC motor
operating at 50 V (Vdc min ), the power (Pmin ) is given as 90 W
(i.e., for constant torque, the load power is proportional to
speed). Hence, from (4), the value of inductance Lic min cor-
responding to Vdc min is calculated as

min (1 − dmin ) 502 (1 − 0.2016)2

2 2
Vdc
Lic min = =
Fig. 3. Operation of the proposed converter in different modes (a)–(c) for Pmin 2fs 90 2 × 20000
a negative half cycle of supply voltage and (d) the associated waveforms.
(a) Mode I. (b) Mode II. (c) Mode III. (d) Waveforms during complete switching
= 442.67 μH. (4)
cycle.
The values of inductances Li1 and Li2 are taken less than
1/10th of the minimum critical value of inductance to ensure
designed. For a supply voltage with an rms value of 220 V, the a deep DICM condition [24]. The analysis of supply current
average voltage appearing at the input side is given as [24] at minimum duty ratio (i.e., supply voltage as 220 V and dc
√ √ link voltage as 50 V) is carried out for different values of the
2 2Vs 2 2 × 220 inductor (Li1 and Li2 ). Fig. 4 shows the supply current at
Vin = = ≈ 198 V. (1)
π π the input inductor’s value as Lic , Lic /2, Lic /5, and Lic /10,
respectively. The supply current at higher values of the input
The relation governing the voltage conversion ratio for a side inductor is highly distorted due to the inability of the
buck–boost converter is given as [22] converter to operate in DICM at peak values of supply voltages.
Hence, the values of inductors Li1 and Li2 are selected around
Vdc 1/10th of the critical inductance and are taken as 35 μH. It
d= . (2)
Vdc + Vin reduces the size, cost, and weight of the PFC converter.
BIST AND SINGH: ADJUSTABLE-SPEED PFC BRIDGELESS BUCK–BOOST CONVERTER-FED BLDC MOTOR DRIVE 2669

B. Design of DC Link Capacitor (Cd ) where fc is the cutoff frequency of the designed filter which is
selected as [25]
The design of the dc link capacitor is governed by the amount
of the second-order harmonic (lowest) current flowing in the fL < fc < fsw . (12)
capacitor and is derived as follows.
For the PFC operation, the supply current (is ) is in phase Hence, a value of fc is taken as fsw /10.
with the supply voltage (vs ). Hence, the input power Pin is Finally, a low-pass filter with inductor and capacitor of
given as [22] 1.6 mH and 330 nF is selected for this particular application.
√ √
Pin = 2VS Sinωt ∗ 2IS Sinωt = VS IS (1 − Cos2ωt) (5)
V. C ONTROL OF PFC BL B UCK –B OOST C ONVERTER -F ED
where the latter term corresponds to the second-order harmonic, BLDC M OTOR D RIVE
which is reflected in the dc link capacitor as
The control of the PFC BL buck–boost converter-fed BLDC
VS I S
iC (t) = − Cos2ωt. (6) motor drive is classified into two parts as follows.
Vdc
The dc link voltage ripple corresponding to this capacitor A. Control of Front-End PFC Converter:
current is given as [22] Voltage Follower Approach

1 Id
ΔVdc = iC (t)dt = − Sin2ωt. (7) The control of the front-end PFC converter generates the
Cd 2ωCd PWM pulses for the PFC converter switches (Sw1 and Sw2 ) for
For a maximum value of voltage ripple at the dc link capaci- dc link voltage control with PFC operation at ac mains. A single
tor, Sin(ωt) is taken as 1. Hence, (7) is rewritten as voltage control loop (voltage follower approach) is utilized
Id for the PFC BL buck–boost converter operating in DICM. A
Cd = . (8) ∗
reference dc link voltage (Vdc ) is generated as
2ωΔVdc
∗
Now, the value of the dc link capacitor is calculated for Vdc = kv ω ∗ (13)
the designed value Vdc des with permitted ripple in the dc link
voltage (ΔVdc ) taken as 3% as where kv and ω ∗ are the motor’s voltage constant and the
reference speed, respectively.
Id Po /Vdc des 350/100 The voltage error signal (Ve ) is generated by comparing the
Cd= = = =1857.7 μF. ∗
2ωΔVdc 2ωΔVdc 2×314×0.03×100 reference dc link voltage (Vdc ) with the sensed dc link voltage
(9) (Vdc ) as
Hence, the nearest possible value of dc link capacitor Cd is
∗
selected as 2200 μF. Ve (k) = Vdc (k) − Vdc (k) (14)

where k represents the kth sampling instant.

C. Design of Input Filter (Lf and Cf )
This error voltage signal (Ve ) is given to the voltage
A second-order low-pass LC filter is used at the input side to proportional–integral (PI) controller to generate a controlled
absorb the higher order harmonics such that it is not reflected output voltage (Vcc ) as
in the supply current. The maximum value of filter capacitance
is given as [25] Vcc (k) = Vcc (k − 1) + kp {Ve (k) − Ve (k − 1)} + ki Ve (k)
(15)
Ipeak 350 1
Cmax = tan(θ) = √ tan(1◦ ) where kp and ki are the proportional and integral gains of the
ωL Vpeak 220 314 × 220 2
= 401.98 nF (10) voltage PI controller.
Finally, the output of the voltage controller is compared with
where Ipeak , Vpeak , ωL , and θ represent the peak value of a high frequency sawtooth signal (md ) to generate the PWM
supply current, peak value of supply voltage, line frequency in pulses as
radians per second, and displacement angle between the supply  
voltage and supply current, respectively. if md < Vcc then Sw1 = ‘ON’
For vs > 0;
Hence, a value of Cf is taken as 330 nF. Now, the value of if md ≥ Vcc then Sw1 = ‘OFF’
inductor Lf is calculated as follows.  
if md < Vcc then Sw2 = ‘ON’
The value of the filter inductor is designed by considering For vs < 0; (16)
if md ≥ Vcc then Sw2 = ‘OFF’
the source impedance (Ls ) of 4%–5% of the base impedance.
Hence, the additional value of inductance required is given as where Sw1 and Sw2 represent the switching signals to the
  2 switches of the PFC converter.
1 1 Vs
Lf = Lreq + Ls ⇒ = L req + 0.04
4π 2 fc2 Cf ωL Po
  2
 B. Control of BLDC Motor: Electronic Commutation
1 1 220
Lreq = 2 −0.04
4π × 20002 × 330 × 10−9 314 350 An electronic commutation of the BLDC motor includes the
= 1.57 mH (11) proper switching of VSI in such a way that a symmetrical
2670 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 61, NO. 6, JUNE 2014

Fig. 5. Operation of a VSI-fed BLDC motor when switches S1 and S4 are

conducting.

TABLE II
S WITCHING S TATES FOR ACHIEVING E LECTRONIC C OMMUTATION OF
BLDC M OTOR BASED ON H ALL -E FFECT P OSITION S IGNALS

dc current is drawn from the dc link capacitor for 120◦ and

placed symmetrically at the center of each phase. A Hall-effect
position sensor is used to sense the rotor position on a span of
60◦ , which is required for the electronic commutation of the Fig. 6. Steady-state performance of the proposed BLDC motor drive at rated
conditions.
BLDC motor. The conduction states of two switches (S1 and
S4 ) are shown in Fig. 5. A line current iab is drawn from the Moreover, power quality indices such as power factor (PF),
dc link capacitor whose magnitude depends on the applied dc displacement power factor (DPF), crest factor (CF), and THD
link voltage (Vdc ), back electromotive forces (EMFs) (ean and of supply current are analyzed for determining power quality at
ebn ), resistances (Ra and Rb ), and self-inductance and mutual ac mains.
inductance (La , Lb , and M) of the stator windings. Table II
shows the different switching states of the VSI feeding a BLDC
A. Steady-State Performance
motor based on the Hall-effect position signals (Ha − Hc ). A
brief modeling of the BLDC motor is given in the Appendix. The steady-state behavior of the proposed BLDC motor drive
for two cycles of supply voltage at rated condition (rated dc link
voltage of 200 V) is shown in Fig. 6. The discontinuous induc-
VI. S IMULATED P ERFORMANCE OF P ROPOSED
tor currents (iLi1 and iLi2 ) are obtained, confirming the DICM
BLDC M OTOR D RIVE
operation of the BL buck–boost converter. The performance of
The performance of the proposed BLDC motor drive is the proposed BLDC motor drive at speed control by varying
simulated in MATLAB/Simulink environment using the Sim- dc link voltage from 50 to 200 V is tabulated in Table III. The
Power-System toolbox. The performance evaluation of the pro- harmonic spectra of the supply current at rated and light load
posed drive is categorized in terms of the performance of the conditions, i.e., dc link voltages of 200 and 50 V, are also shown
BLDC motor and BL buck–boost converter and the achieved in Fig. 7(a) and (b), respectively, which shows that the THD
power quality indices obtained at ac mains. The parameters of supply current obtained is under the acceptable limits of
associated with the BLDC motor such as speed (N), electro- IEC 61000-3-2.
magnetic torque (Te ), and stator current (ia ) are analyzed for
the proper functioning of the BLDC motor. Parameters such as
B. Dynamic Performance of Proposed BLDC Motor Drive
supply voltage (Vs ), supply current (is ), dc link voltage (Vdc ),
inductor’s currents (iLi1 , iLi2 ), switch voltages (Vsw1 , Vsw2 ), The dynamic behavior of the proposed drive system during
and switch currents (isw1 , isw2 ) of the PFC BL buck–boost a starting at 50 V, step change in dc link voltage from 100 to
converter are evaluated to demonstrate its proper functioning. 150 V, and supply voltage change from 270 to 170 V is shown
BIST AND SINGH: ADJUSTABLE-SPEED PFC BRIDGELESS BUCK–BOOST CONVERTER-FED BLDC MOTOR DRIVE 2671

TABLE III
P ERFORMANCE OF PFC BL B UCK –B OOST C ONVERTER -F ED
BLDC M OTOR D RIVE U NDER S PEED C ONTROL

Fig. 7. Harmonic spectra of supply current at rated supply voltage and rated
loading on BLDC motor for a dc link voltage of (a) 200 V and (b) 50 V.

in Fig. 8. A smooth transition of speed and dc link voltage

is achieved with a small overshoot in supply current under
the acceptable limit of the maximum allowable stator winding
current of the BLDC motor. The controller gains are given in
the Appendix.

C. Performance Under Supply Voltage Variation

The behavior of the proposed BLDC motor drive in practical
supply conditions is demonstrated, and the performance is also
evaluated for supply voltage from 90 to 270 V. Table IV shows
different power quality indices with variation in supply voltage. Fig. 8. Dynamic performance of proposed BLDC motor drive during
(a) starting, (b) speed control, and (c) supply voltage variation at rated
The THD of supply current obtained is within the limits of conditions.
IEC 61000-3-2. Fig. 9(a) and (b) shows the harmonic spectra
of supply current at ac mains at rated conditions of dc link
D. Stress on PFC Converter Switches
voltage and load on the BLDC motor with supply voltage as
90 and 270 V, respectively. An acceptable THD of supply Voltage and current stresses on PFC switches for different
current is obtained for both the cases which show an improved loading on the BLDC motor are tabulated in Table V. The
power quality operation of the proposed BLDC motor drive at switch’s peak voltage (Vsw ) and peak current (ipeak ) and the
universal ac mains. rms current (irms ) flowing through the switch are tabulated
2672 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 61, NO. 6, JUNE 2014

TABLE IV
P ERFORMANCE OF PFC B UCK –B OOST C ONVERTER -F ED BLDC M OTOR
D RIVE U NDER VARYING S UPPLY VOLTAGE

Fig. 9. Harmonic spectra of supply current at rated loading on BLDC motor

with dc link voltage as 200 V and supply voltage as (a) 90 V and (b) 270 V.

TABLE V Fig. 10. Steady-state performance of the proposed BLDC motor drive at rated
VOLTAGE AND C URRENT S TRESSES U NDER D IFFERENT L OADING conditions with dc link voltage as (a) 200 V and (b) 50 V.

state switches is developed using the optocoupler 6N136. A

prefiltering and isolation circuit for the Hall-Effect sensor is
also developed for sensing the Hall-effect position signals. Test
results are discussed in the following sections.

A. Steady-State Performance
Fig. 10(a) and (b) shows the operation of the proposed
BLDC motor drive showing supply voltage (vs ), supply current
(is ), dc link voltage (Vdc ), and stator current (ia ) for the
dc link voltages of 200 and 50 V, respectively. A sinusoidal
for load variation on the BLDC motor from 10% to 100% supply current in phase with the supply voltage is achieved for
of the rated load. The switch’s peak voltage and peak current operation at both dc link voltages which shows a near unity
are required for selecting the PFC switch rating while the power factor at ac mains. The variation of speed and the dc
rms current flowing through the switch decides the size of the link voltage with input reference voltage at the analog-to-digital
required heat sink. The simulated performance of the proposed converter of DSP is tabulated in Table VI.
drive is found to be satisfactory in all aspects.
B. Operation of PFC BL Buck–Boost Converter
VII. H ARDWARE VALIDATION OF P ROPOSED
Fig. 11(a) and (b) shows the currents flowing in inductors
BLDC M OTOR D RIVE
Li1 and Li2 and its enlarged waveforms, each appearing for
A digital signal processor (DSP) based on TI-TMS320F2812 the positive and negative half cycles of the supply voltage for
is used for the development of the proposed PFC BL the necessary operation of the BL buck–boost converter. It
buck–boost converter-fed BLDC motor drive. The necessary clearly demonstrates the DICM operation of the BL buck–boost
circuitry for isolation between DSP and gate drivers of solid- converter.
BIST AND SINGH: ADJUSTABLE-SPEED PFC BRIDGELESS BUCK–BOOST CONVERTER-FED BLDC MOTOR DRIVE 2673

TABLE VI
VARIATION OF DC L INK VOLTAGE AND S PEED
W ITH R EFERENCE VOLTAGE

Fig. 12. (a) Stress on PFC converter switches and (b) its enlarged waveforms
during the operation of proposed BLDC motor drive at rated conditions.

for change in dc link voltage and supply voltage as shown in

Fig. 13(b) and (c), respectively. The controller gains are given
in the Appendix.

E. PFC and Improved Power Quality Operation

The performance parameters and the power quality indices
Fig. 11. (a) Variation of inductor’s currents (iLi1 and iLi2 ) and (b) its
enlarged waveforms with supply voltage and supply current. such as supply voltage (vs ), supply current (is ), active (Pac ),
reactive (Pr ), and apparent (Pa ) powers, PF, DPF, and THD of
supply current are measured on a “Fluke” make power quality
C. Stress on PFC Converter Switches
analyzer. Fig. 14(a)–(c) and (d)–(f) shows the obtained indices
Fig. 12(a) and (b) shows the switch currents (isw1 , isw2 ) at rated condition of the BLDC motor with dc link voltages as
and voltages (Vsw1 , Vsw2 ) appearing for each half cycle and its 200 and 50 V, respectively. Moreover, Fig. 14(g)–(i) and (j)–(l)
enlarged waveforms, respectively. A peak voltage of 500 V and shows the performance at supply voltages of 90 and 270 V,
a current stress of 28 A are achieved, which is quite acceptable respectively. An improved power quality is obtained in all
and in accordance with the simulated results. these conditions with power quality indices within the limits of
IEC 61000-3-2 [7].
D. Dynamic Performance of Proposed BLDC Motor Drive
VIII. C OMPARATIVE A NALYSIS OF
The dynamic performance of the proposed BLDC motor
D IFFERENT C ONFIGURATIONS
drive during starting, speed control, and supply voltage varia-
tion is shown in Fig. 13. As shown in Fig. 13(a), a limited inrush A comparative analysis of the proposed BL buck–boost
current is obtained during the starting of the BLDC motor at converter-fed BLDC motor drive is carried out with conven-
50 V. Moreover, a limited transient in supply current is obtained tional schemes. Two conventional schemes of the DBR-fed
2674 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 61, NO. 6, JUNE 2014

Fig. 14. Power quality indices and performance parameters (vs , is , Pac , Pa ,
Pr , PF, DPF, CF, and harmonic spectrum of is ) of proposed BLDC motor drive
at rated load on BLDC motor with (a)–(c) dc link voltage as 200 V and supply
voltage as 220 V, (d)–(f) dc link voltage as 50 V and supply voltage as 220 V,
(g)–(i) dc link voltage as 200 V and supply voltage as 90 V, and (j)–(l) dc link
voltage as 200 V and supply voltage as 270 V.

an increase in the efficiency of the proposed system as shown in

Fig. 13. Dynamic behavior of the proposed BLDC motor drive during Fig. 15(b). The conventional scheme of the BLDC motor drive
(a) starting at dc link voltage of 50 V, (b) step change in dc link voltage from
100 to 150 V, and (c) supply voltage variation. with PFC has the lowest efficiency due to the high amount of
losses in the VSI as well as in the DBR and PFC converter.
BLDC motor drive and a single-switch PFC using a constant dc
bus voltage are used for comparative performance evaluation.
B. Comparison on Basis of Power Quality
The analysis is classified into two subcategories as follows.
Fig. 16(a) shows the THD of supply current at ac mains
with output power for both the conventional and the proposed
A. Comparison on Basis of Losses and Efficiency
scheme of the BL buck–boost converter-fed BLDC motor drive.
The losses in the complete BLDC motor drive are classified The harmonic distortion in a conventional scheme of the DBR-
as losses in various sections such as DBR, PFC converter, VSI, fed BLDC motor drive is as high as 80%–100%, which is not
and the BLDC motor. The losses in different parts of the BLDC a recommended solution as per the guidelines of IEC 61000-
motor are measured for three different configurations of the 3-2 [7]. Fig. 16(b) shows the power factor with output power
BLDC motor drive. As shown in Fig. 15(a), the losses in two for these three different configurations. The harmonic distortion
conventional schemes of the BLDC motor drive are higher in and power factor in a conventional scheme using a single-
VSI due to the use of PWM-based switching of VSI which switch PFC are also under the acceptable limits but have higher
increases the switching losses in the system. This accounts for losses associated with it as shown in Fig. 15(a).
BIST AND SINGH: ADJUSTABLE-SPEED PFC BRIDGELESS BUCK–BOOST CONVERTER-FED BLDC MOTOR DRIVE 2675

Fig. 16. Comparative analysis of (a) THD of supply current at ac mains

Fig. 15. Comparative analysis of (a) losses and (b) the efficiency of the and (b) power factor variation with output power for the conventional and the
conventional and the proposed configuration. proposed configuration.

Table VII shows a comparative analysis of three different TABLE VII

configurations of the BLDC motor drive. The evaluation is C OMPARATIVE A NALYSIS OF P ROPOSED C ONFIGURATION
W ITH C ONVENTIONAL S CHEMES
based on the control requirement, sensor requirement, and
losses in the PFC converter and VSI-fed BLDC motor. The
proposed scheme has shown a minimum amount of sensing
requirement and cost with the highest efficiency among the
three configurations, and hence, it is a recommended solution
for low-power applications.

IX. C ONCLUSION
A PFC BL buck–boost converter-based VSI-fed BLDC mo-
tor drive has been proposed targeting low-power applications.
A new method of speed control has been utilized by controlling
the voltage at dc bus and operating the VSI at fundamental
frequency for the electronic commutation of the BLDC motor
for reducing the switching losses in VSI. The front-end BL
buck–boost converter has been operated in DICM for achieving
an inherent power factor correction at ac mains. A satisfactory
performance has been achieved for speed control and supply
A PPENDIX
voltage variation with power quality indices within the accept-
able limits of IEC 61000-3-2. Moreover, voltage and current BLDC Motor Rating: four poles, Prated (rated power) =
stresses on the PFC switch have been evaluated for determining 251.32 W, Vrated (rated dc link voltage) = 200 V, Trated (rated
the practical application of the proposed scheme. Finally, an ex- torque) = 1.2 N · m, ωrated (rated speed) = 2000 r/min, Kb
perimental prototype of the proposed drive has been developed (back EMF constant) = 78 V/kr/min, Kt (torque constant) =
to validate the performance of the proposed BLDC motor drive 0.74 N · m/A, Rph (phase resistance) = 14.56 Ω, Lph (phase
under speed control with improved power quality at ac mains. inductance) = 25.71 mH, and J (moment of inertia) = 1.3 ×
The proposed scheme has shown satisfactory performance, and 10−4 N·m/A2 .
it is a recommended solution applicable to low-power BLDC Controller Gains: kp = 0.4, ki = 3 (simulation); kp = 0.4,
motor drives. ki = 0.001 (experimental).
2676 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 61, NO. 6, JUNE 2014

Dynamic Model of BLDC Motor: A dynamic model of the By rearranging (24), the speed derivative is expressed as
BLDC motor is developed in terms of time derivative of current,
(Te − Tl − Bωr )
speed, and position. The per-phase voltages (Van , Vbn , and Vcn ) pωr = . (25)
of the BLDC motor are given as [6] J
⎡ ⎤ ⎡ ⎤⎡ ⎤ The position derivative is expressed as [6]
Van 1 0 0 ian
⎣ Vbn ⎦ = Rs ⎣ 0 1 0 ⎦ ⎣ ibn ⎦ d
(θ) = ωr ⇒ pθ = ωr . (26)
Vcn 0 ⎡0 1 icn ⎤ ⎡ ⎤ ⎡ ⎤ dt
L M M ian ean Equations (20), (25), and (26) represent the current, speed,
+ ⎣ M L M ⎦ p ⎣ ibn ⎦ + ⎣ ebn ⎦ (17) and position derivative of the BLDC motor and, hence, the
M M L icn ecn dynamic model of the BLDC motor drive.
where ian , ibn , and icn are the phase currents, ean , ebn , and ecn Now, at any instance of time, two switches, one each from
are the phase back EMFs, Rs is the per-phase resistance, L is the upper and the lower leg, remain in the “ON” state other than
the self-inductance, M is the mutual inductance of the stator’s the switches in the same leg. As shown in Fig. 5, during the ON
winding of the BLDC motor, and p is the time differential state of switches S1 and S4 , dc link voltage Vdc is applied to line
operator. “a-b.” The per-phase voltages Vao , Vbo , and Vco with respect to
The sum of the currents in three phases is zero for a three- terminal “o” are given as [6]
⎡ ⎤ ⎡ ⎤
phase star-connected BLDC motor given as Vao (S1 − S2 )  
⎣ Vbo ⎦ = ⎣ (S3 − S4 ) ⎦ Vdc (27)
ian + ibn + icn = 0. (18) 2
Vco (S5 − S6 )
Now, substituting (18) in (17), the VA relation is obtained as
⎡ ⎤ ⎡ ⎤⎡ ⎤ where S1 –S6 are the switching states of the VSI’s switches and
Van 1 0 0 ian are replaced by “1” or “0” for the “on” and “off” positions of
⎣ Vbn ⎦ = R ⎣ 0 1 0 ⎦ ⎣ ibn ⎦
the switch, respectively.
V⎡
cn 0 0 1 icn ⎤ ⎡ ⎤ ⎡ ⎤ Table II shows the corresponding switching states and per-
L−M 0 0 ian ean phase voltages with respect to terminal “o” based on the rotor
+⎣ 0 L−M 0 ⎦ p ⎣ ibn ⎦ + ⎣ ebn ⎦ . (19) position as sensed by Hall-effect position sensors.
0 0 L−M icn ecn The neutral voltage Vno , where terminals “n” and “o” are
Now, by rearranging (19), the current derivatives are ob- shown in Fig. 5, is given as [8]
tained as (Vao + Vao + Vao ) − (exn + exn + exn )
⎡ ⎤ ⎡ ⎤−1 Vno = . (28)
ian L−M 0 0 3
p ⎣ ibn ⎦ = ⎣ 0 L−M 0 ⎦ Moreover, the phase voltages of the BLDC motor are also
icn
⎛⎡ 0
⎤ ⎡ ⎤ 0 ⎡ L − M ⎤⎡ ⎤⎞ expressed as
Van ean 1 0 0 ian ⎡ ⎤ ⎡ ⎤ ⎡ ⎤
× ⎝⎣ Vbn ⎦ − ⎣ ebn ⎦ − Rs ⎣ 0 1 0 ⎦ ⎣ ibn ⎦⎠ . (20) Van (Vao − Von ) (Vao + Vno )
⎣ Vbn ⎦ = ⎣ (Vbo − Von ) ⎦ = ⎣ (Vbo + Vno ) ⎦ . (29)
Vcn ecn 0 0 1 icn
Vcn (Vco − Von ) (Vco + Vno )
The electromagnetic torque Te is expressed as [6]
Equation (29) is used with (27) and (28) to obtain the per-
ean ian + ebn ibn + ecn icn
Te = . (21) phase voltage which is finally used in (20) to determine the
ωr current derivative for obtaining the dynamic model of the
Moreover, back EMF is also defined as [6] BLDC motor.

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