Chapter 9: Main Memory

Operating System Concepts – 10th Edition Silberschatz, Galvin and Gagne ©2018
 Objectives

 To provide a detailed description of various ways of organizing memory

hardware

 To discuss various memory-management techniques, including paging

and segmentation

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 Background

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 Base and Limit Registers
 A pair of base and limit registers define the logical address space

 CPU must check every memory access generated in user mode to be

sure it is between base and limit for that user

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 Hardware Address Protection

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 Binding of Instructions and Data to Memory

 Address binding of instructions and data to memory addresses can

happen at three different stages:

 Compile time: If memory location is known a priori, absolute code

can be generated; must recompile code if starting location changes

 Load time: Must generate relocatable code if memory location is

not known at compile time

 Execution time: Binding delayed until run time if the process can
be moved during its execution from one memory segment to
another
 Need hardware support (e.g., base and limit registers)

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 Multi-step Processing of a User Program

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 Logical vs. Physical Address Space

 The concept of a logical address space that is bound to a separate

physical address space is central to proper memory management
 Logical address – generated by the CPU; also referred to as
virtual address
 Physical address – address seen by the memory unit

 Logical and physical addresses are the same in compile-time and load-
time address-binding schemes; logical (virtual) and physical addresses
differ in execution-time address-binding scheme

 Logical address space is the set of all logical addresses generated by

a program

 Physical address space is the set of all physical addresses generated

by a program

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 Memory-Management Unit (MMU)
 Hardware device that at run time maps virtual to physical address

 Many mapping methods possible, covered in the rest of this chapter

 The user program deals with logical addresses; it never sees the real
physical addresses
 Execution-time binding occurs when reference is made to location in
memory
 Logical address bound to physical addresses

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 Swapping

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 Swapping
 A process can be swapped temporarily out of memory to a backing
store, and then brought back into memory for continued execution
 Total physical memory space of processes can exceed physical
memory

 Backing store – fast disk large enough to accommodate copies of all

memory images for all users; must provide direct access to these
memory images

 Roll out, roll in – swapping variant used for priority-based scheduling

algorithms; lower-priority process is swapped out so higher-priority
process can be loaded and executed

 Major part of swap time is transfer time; total transfer time is directly
proportional to the amount of memory swapped

 System maintains a ready queue of ready-to-run processes which have

memory images on disk

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 Schematic View of Swapping

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 Context Switch Time including Swapping

 If next processes to be put on CPU are not in memory, need to swap

out a process and swap in target process

 Context switch time can then be very high

 100MB process swapping to hard disk with transfer rate of 50MB/sec

 Swap out time of 2000 ms
 Plus swap in of same sized process
 Total context switch swapping component time of 4000ms (4
seconds)

 Can be reduced by reducing the size of memory swapped – by knowing

how much memory really being used
 System calls to inform OS of memory use via request_memory()
and release_memory()

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 Contiguous Memory Allocation

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 Contiguous Allocation
 Main memory must support both OS and user processes

 Memory is a limited resource, must be allocated efficiently

 Contiguous allocation is an early method

 Main memory has two partitions:

 Resident operating system, usually held in low memory with
interrupt vector
 User processes then held in high memory
 Each process contained in single contiguous section of memory

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 Contiguous Allocation (Cont.)
 Relocation registers used to protect user processes from each
other, and from changing operating-system code and data

 Base register contains value of smallest physical address

 Limit register contains range of logical addresses – each

logical address must be less than the limit register

 MMU maps logical address dynamically

 Can then allow actions such as kernel code being transient

and kernel changing size

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 Hardware Support for Relocation and Limit Registers

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 Multiple-partition allocation
 Multiple-partition allocation
 Degree of multiprogramming limited by number of partitions
 Variable-partition sizes for efficiency (sized to a given process’ needs)
 Hole – block of available memory; holes of various size are scattered
throughout memory
 When a process arrives, it is allocated memory from a hole large enough to
accommodate it
 Process exiting frees its partition, adjacent free partitions combined
 Operating system maintains information about:
a) allocated partitions b) free partitions (hole)

Operating System Concepts – 10th Edition 9.18 Silberschatz, Galvin and Gagne ©2018
 Dynamic Storage-Allocation Problem
How to satisfy a request of size n from a list of free holes?

 First-fit: Allocate the first hole that is big enough

 Best-fit: Allocate the smallest hole that is big enough; must

search entire list, unless ordered by size
 Produces the smallest leftover hole

 Worst-fit: Allocate the largest hole; must also search entire list
 Produces the largest leftover hole

First-fit and best-fit better than worst-fit in terms of speed and storage
utilization

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 Fragmentation

Operating System Concepts – 10th Edition 9.20 Silberschatz, Galvin and Gagne ©2018
 Fragmentation
 External Fragmentation – total memory space exists to satisfy a
request, but it is not contiguous

 Internal Fragmentation – allocated memory may be slightly larger

than requested memory; this size difference is memory internal to a
partition, but not being used

 First-fit analysis reveals that given N blocks allocated, 0.5 N blocks lost
due to fragmentation
 1/3 may be unusable  50-percent rule

Operating System Concepts – 10th Edition 9.21 Silberschatz, Galvin and Gagne ©2018
 Fragmentation (Cont.)

 Reduce external fragmentation by compaction

 Shuffle memory contents to place all free memory together in one
large block
 Compaction is possible only if relocation is dynamic, and is done at
execution time

 Now consider that backing store has same fragmentation problems

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 First Fit

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 Best Fit

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Operating System Concepts – 10th Edition 9.31 Silberschatz, Galvin and Gagne ©2018
 Non-contiguous Memory Allocation

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 Segmentation

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 Segmentation
 Memory-management scheme that supports user view of memory

 A program is a collection of segments

 A segment is a logical unit such as:

main program
procedure
function
method
object
local variables, global variables
common block
stack
symbol table
array

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 User’s View of a Program

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 Logical View of Segmentation

4
1

3 2
4

user space physical memory space

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 Segmentation Architecture
 Logical address consists of a tuple:
<segment-number, offset>,

 Segment table – maps two-dimensional physical addresses; each

table entry has:
 base – contains the starting physical address where the segments
reside in memory
 limit – specifies the length of the segment

 Segment-table base register (STBR) points to the segment table’s

location in memory

 Segment-table length register (STLR) indicates number of segments

used by a program;
segment number s is legal if s < STLR

Operating System Concepts – 10th Edition 9.37 Silberschatz, Galvin and Gagne ©2018
 Segmentation Architecture (Cont.)
 Protection
 With each entry in segment table associate:
 validation bit = 0  illegal segment
 read/write/execute privileges

 Protection bits associated with segments; code sharing occurs at

segment level

 Since segments vary in length, memory allocation is a dynamic storage-

allocation problem

 A segmentation example is shown in the following diagram

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 Segmentation Hardware

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 Segment Table

Base Limit
Address

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 Paging

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 Paging
 Physical address space of a process can be noncontiguous; process is
allocated physical memory whenever the latter is available
 Avoids external fragmentation
 Avoids problem of varying sized memory chunks

 Divide physical memory into fixed-sized blocks called frames

 Size is power of 2, between 512 bytes and 16 Mbytes

 Divide logical memory into blocks of same size called pages

 Keep track of all free frames

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 Paging (Cont.)
 To run a program of size N pages, need to find N free frames and load
program

 Set up a page table to translate logical to physical addresses

 Backing store likewise split into pages

 Still have internal fragmentation

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 Address Translation Scheme
PA = 14 = (1110)
 Address generated by CPU is divided into:
p = (11) = 3

 Page number (p) – used as an index intoda page

= (10) =2
table which
contains base address of each page in physical memory

 Page offset (d) – combined with base address to define the

physical memory address that is sent to the memory unit

page number page offset

• p = the high-order m−n bits of LA
p d
• d = n low-order bits
m -n n

 For given logical address space of 2m and page size of 2n

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 Paging Hardware

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 Paging Model of Logical and Physical Memory

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 Paging Example

n=2 and m=4 32-byte memory and 4-byte pages

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 4 = page size

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 Paging (Cont.)

 Calculating internal fragmentation

 Page size = 2,048 bytes
 Process size = 72,766 bytes
 35 pages + 1,086 bytes
 Internal fragmentation of 2,048 - 1,086 = 962 bytes
 Worst case fragmentation = 1 frame – 1 byte
 On average fragmentation = 1 / 2 frame size
 So small frame sizes desirable?
 But each page table entry takes memory to track
 Page sizes growing over time
 Solaris supports two page sizes – 8 KB and 4 MB
 Process view and physical memory now very different
 By implementation process can only access its own memory

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 • PT?

• LA 136  PA?

• Fragmentation? = 50
• (FRAME #11)

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 • Job 1 contains 900 lines

• Frame size = 512 lines

• LA 518  PA?

• Fragmentation?

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 Free Frames

Before allocation After allocation

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 Implementation of Page Table
 Page table is kept in main memory

 Page-table base register (PTBR) points to the page table

 Page-table length register (PTLR) indicates size of the page table

 In this scheme every data/instruction access requires two memory

accesses
 One for the page table and one for the data / instruction

 The two memory access problems can be solved by the use of a special
fast-lookup hardware cache called associative memory or translation
look-aside buffers (TLBs)

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 Implementation of Page Table (Cont.)
 Some TLBs store address-space identifiers (ASIDs) in each TLB
entry – uniquely identifies each process to provide address-space
protection for that process
 Otherwise need to flush at every context switch

 TLBs typically small (64 to 1,024 entries)

 On a TLB miss, value is loaded into the TLB for faster access next time
 Replacement policies must be considered
 Some entries can be wired down for permanent fast access

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 Associative Memory

 Associative memory – parallel search

Page # Frame #

 Address translation (p, d)

 If p is in associative register, get frame # out
 Otherwise get frame # from page table in memory

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 Paging Hardware With TLB

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 Effective Access Time
 Associative Lookup =  time unit
 Can be < 10% of memory access time
 Hit ratio = 
 Hit ratio – percentage of times that a page number is found in the
associative registers; ratio related to number of associative
registers
 Consider  = 80%,  = 20ns for TLB search, 100ns for memory access
 Effective Access Time (EAT)
EAT = (1 + )  + (2 + )(1 – )
=2+–
 Consider  = 80%,  = 20ns for TLB search, 100ns for memory access
 EAT = 0.80 x 100 + 0.20 x 200 = 120ns
 Consider more realistic hit ratio ->  = 99%,  = 20ns for TLB search,
100ns for memory access
 EAT = 0.99 x 100 + 0.01 x 200 = 101ns

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 Memory Protection
 Memory protection implemented by associating protection bit with each
frame to indicate if read-only or read-write access is allowed
 Can also add more bits to indicate page execute-only, and so on

 Valid-invalid bit attached to each entry in the page table:

 “valid” indicates that the associated page is in the process’ logical
address space, and is thus a legal page
 “invalid” indicates that the page is not in the process’ logical
address space
 Or use page-table length register (PTLR)

 Any violations result in a trap to the kernel

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 Valid (v) or Invalid (i) Bit In A Page Table

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 End of Chapter 9

Operating System Concepts – 10th Edition Silberschatz, Galvin and Gagne ©2018