Username:arunkumarvrn
Password:Arun198212@
Work Entry
http://192.168.1.47:8086/Design/DesignEntry
Attendence
http://192.168.1.47:8081/
As you requested earlier, we are planning to provide you with the pilot project RTL
design to evaluate the power reduction using your IP.
As we are progressing to close the design, we may need 6w time to give you the
synthesized RTL code.
Note: This is a SoC product which we are designing from concept to GDSII with the
support from GF using lower techological node.
We will share more details once we clear few milestones. Thanks for your patience.
Thanks for sharing the quote. We will go through it and let you know if we have any
queries.
Thanks for the call this morning. As we discussed, I have consolidated couple of
our questions below, kindly help to clarify.
Additionally, I have managed to get the responses for your questions.
The request came from one of the organizations of Indian govt sector, and they have
indicated that the end application of this bare die is getting into a civilian
application.
Our end customer is not ready to reveal the details of the MCU due to their
organization’s CCI.
Please see if you can still support here.
Looking forward to your prompt response. Appreciate your support!!
Dear Chandramohan,
Thank you for your patience and understanding as we work to free up our time here.
As advised by our boss – Suresh, we are more inclined to pursue our authentic SoC
design rather than employing standard test cases.
This will enable us to ascertain the optimization potential of your IP more
effectively. I trust you have no objections to this idea.
Furthermore, in accordance with our corporate policy, we are mandated to conduct
all communications via official email or meeting bridge.
Your cooperation in this regard is highly appreciated.
Architecture design for Microcontroller :-
Architecture consists of three modules
1. Fetch Module - Fetch the instruction and perform the specific functions with the
support of Mux, adder, Program counter, program memory amd instruction decoder.
2. Decoder Module - It contains various sub-modules like control logic, data memory
and data register.
3. Execute Module - It performs various calculations like addition, subtraction and
mulplication and decision making with the support of ALU, mux, accumulator and
status register.
Karthika:
As we discussed, develop a tool to generate scripts for RTL synthesis and
various stages of physical design rather than the project dependent.
The requirements are listed below:
1. Point the path location for library, HDL, reports to be dumped and constraint
file.
2. Naming convention such as name of the top module
1. RTL Code Progress update:
As advised earlier, plan to develop the pilot project RTL design to evaluate the
power reduction joined together with FPGA team .
Project details: Shared the high level block digram and specification for each
modules such as microcontroller and various communication interface protocols like
I2C, UART and GPIO .
Progress update:
1. FPGA team has developed the UART, I2C module and verified the functionality
through simulation .
Under progress:
Now the team is involved in developing the code for microcontroller with
various sub-modules and need to integrate with interface protocols.
Have to verify the SoC such as timing closure and power analysis whether it
meets the specification after the integration is done.
Timeline: 2 weeks
2. Concerns:
As we discussed with Umapathy, shared the timeline (6Weeks) to provide the
synthesized RTL code.
He pleased us to provide access for subsystem for RTL code, environment to
understand the tool flow, methodology and library access from Global foundry
(12nm).
Tool Access
As we discussed earlier, plan to develop the pilot project RTL design in
collaboration with the FPGA team to evaluate power reduction.
Project details: We have shared the high-level block diagram and specifications for
each module, including the microcontroller and various communication interface
protocols like I2C, UART, and GPIO.
Progress update: The FPGA team has developed the UART, I2C and ALU sub-block in
microcontroller and its functionality were verified .
Under progress: FPGA team is currently developing the remaining sub-modules for the
microcontroller and needs to integrate it with the interface protocols.
Verification of timing closure and power analysis will be done
after the integration of microcontroller and interface protocols.
Our plan is to complete the task in 3W timeline and deliver the
same to BRES for validating their power optimization IP.
Concerns:
We have conveyed to Chandramohan that, will share the synthesized RTL code in
6Weeks timeline for validating their power optimization IP.
Yesterday, he asked to share the following details to progress his optimization
flow parallely.
1. Type of IP
2. RTL code sub-system
3. Access for the environment to understand the tool flow
4. Methodology
5. Library access from Global Foundries (12nm-lib & LEF)
Please provide us with guidance on this concern..
Please let me know if any corrections are needed.
module tb_and_gate;
// Declare variables for inputs and outputs
reg a;
reg b;
wire y;
// Instantiate the AND gate
and_gate uut (
.a(a),
.b(b),
.y(y)
);
// Initial block to apply test vectors
initial begin
// Apply test vectors
a = 0; b = 0; #10;
a = 0; b = 1; #10;
a = 1; b = 0; #10;
a = 1; b = 1; #10;
// End simulation
$stop;
end
endmodule
