www.ti.

com Table of Contents

Application Note
Avoid Common Mistakes When Selecting And Designing
With Power MOSFETs

John Wallace
ABSTRACT
Power MOSFETs are used in a wide variety of applications from switch-mode power supplies to e-bikes and
audio amplifiers. The high current carrying capability, ease of driving and fast switching characteristics makes
power MOSFETs an essential tool in the design engineers toolbox. When selecting a power MOSFET for an
application, a thorough review of the application requirements and the FET data sheet can help avoid some
common mistakes.

Table of Contents
1 Introduction.............................................................................................................................................................................2
2 Review the Data Sheet Limits................................................................................................................................................2
3 Application-specific FETs...................................................................................................................................................... 2
4 Gate Drive Voltage Specifications.........................................................................................................................................4
4.1 Absolute maximum VGS .................................................................................................................................................... 4
4.2 Gate-to-source Threshold Voltage, VGS(th) ........................................................................................................................5
5 High-side and Low-side Switches.........................................................................................................................................7
5.1 Driving a High-side N-channel FET....................................................................................................................................7
5.2 Driving a Low-side N-channel FET.................................................................................................................................... 7
5.3 Driving a High-side P-channel FET....................................................................................................................................7
6 Use a Gate-to-source Resistor.............................................................................................................................................. 8
7 Lowest RDS(on)≠ Lowest Power Loss.................................................................................................................................... 8
8 Summary................................................................................................................................................................................. 8
9 References.............................................................................................................................................................................. 8
Trademarks
All trademarks are the property of their respective owners.

SLPA021 – NOVEMBER 2024 Avoid Common Mistakes When Selecting And Designing With Power 1
Submit Document Feedback MOSFETs
Copyright © 2024 Texas Instruments Incorporated
Introduction www.ti.com

1 Introduction
To assist the designer, TI has published a series of technical articles, application notes and tools for selecting
and using MOSFETs: MOSFET Support and Training Tools application note. Once the FET has been chosen,
there is more work to do to make sure the FET works as expected in the application.
2 Review the Data Sheet Limits
During FET selection, a review of the application and the data sheet is necessary to make sure the device is
operating within the data sheet limits. This is especially true for the absolute maximum ratings which define
the electrical and thermal limitations of the device. Exceeding the absolute maximum ratings can result in
catastrophic failure of the FET. Most engineers derate from the limits in the data sheet to make sure there
is enough margin in the design for unexpected events such as voltage spikes, transients, fault conditions,
overloads, short circuits and etc. For example, a FET with abs max VDS = 30V is typically derated to 24V
maximum operating voltage.
3 Application-specific FETs
Some FETs are optimized for switch-mode applications while others are better suited for static switching. Some
can work in either application type. The first thing to do is review the FET data sheet. On page 1, TI FET
data sheets include information on applications the FET is optimized for. For example, Figure 3-1 shows the
CSD16570Q5B data sheet and this FET is optimized for ORing and hot swap applications.

Figure 3-1. CSD16570Q5B Data Sheet

2 Avoid Common Mistakes When Selecting And Designing With Power SLPA021 – NOVEMBER 2024
MOSFETs Submit Document Feedback
Copyright © 2024 Texas Instruments Incorporated
www.ti.com Application-specific FETs

Likewise, Figure 3-2 shows an excerpt from the CSD18541F5 data sheet. This device is optimized for load
switch and general purpose switching applications.

Figure 3-2. CSD18541F5 Data Sheet

Digging further into the data sheet dynamic characteristics, the CSD16570Q5B is not a good candidate for
switch-mode applications as the charge ratio, Qgd/Qgs > 1. This makes the MOSFET more susceptible to CdV/dt
induced turn-on when used as the low side FET in a synchronous buck converter. Similarly, the CSD18541F5
has a charge ratio > 1, but the typical internal series gate resistance is RG = 1200Ω. This limits the switching
speed and this FET is not the best for switch-mode applications. If there are some questions whether a FET can
be used in a particular application, then review the Applications section and Dynamic Characteristics section in
the data sheet. If there are further questions, then contact your FET vendor for more information.

SLPA021 – NOVEMBER 2024 Avoid Common Mistakes When Selecting And Designing With Power 3
Submit Document Feedback MOSFETs
Copyright © 2024 Texas Instruments Incorporated
Gate Drive Voltage Specifications www.ti.com

4 Gate Drive Voltage Specifications

A common mistake is driving the FET gate at the incorrect voltage. Often VGS is too low to achieve RDS(on)
specified in the data sheet. More information on this topic is described later in the document.
Multiple specifications for VGS are included in the FET data sheet. There is a specification for absolute maximum
VGS, a specification for gate-to-source threshold voltage, VGS(th), and a specification for RDS(on) at one or more
values of VGS. The next section reviews each of these items and how the specifications are used when selecting
a FET.
4.1 Absolute maximum VGS
The absolute maximum VGS rating can be a single value or separate positive and negative values depending
on the gate structure. As detailed in the What type of ESD protection does your MOSFET include? technical
article, TI FETs can have single-ended, back-to-back or no gate ESD protection. FETs with a single-ended ESD
structure only have a single value for absolute maximum VGS. Applying a voltage of the opposite polarity forward
biases the gate-to-source ESD diode allowing current to flow into the gate and clamping VGS at a junction drop.
An external gate resistor can be added to limit the gate current and prevent damaging the FET.
Devices with back-to-back or no ESD protection have separate positive and negative absolute maximum VGS
values that can be symmetric (that is, ±20V) or asymmetric (that is, -12V/+16V). Never operate the FET with VGS
in excess of the absolute maximum specifications or the FET can be damaged.
Table 4-1, Table 4-2, and Table 4-3 show examples of the absolute maximum ratings for the following TI
N-channel MOSFETs:
Table 4-1. CSD17581Q5A Absolute Maximum Ratings
TA = 25°C VALUE UNIT
VDS Drain-to-source voltage 30 V
VGS Gate-to-source voltage ±20 V
Continuous drain current (package limited) 60
ID Continuous drain current (silicon limited), TC = 25°C 123 A
Continuous drain current 24
IDM Pulsed drain current 256 A
Power dissipation 3.1
PD W
Power dissipation, TC = 25°C 83
TJ,
Operating junction temperature and storage temperature –55 to 150 °C
Tstg
Avalanche energy, single pulse
EAS 76 mJ
ID = 39A, L = 0.1 mH, RG = 25Ω

Table 4-2. CSD17381F4 Absolute Maximum Ratings

TA = 25°C unless otherwise stated VALUE UNIT
VDS Drain-to-source voltage 30 V
VGS Gate-to-source voltage 12 V
ID Continuous drain current, TA = 25°C 3.1 A
IDM Pulsed Drain Current, TA = 25°C 12 A
Continuous gate clamp current 35
IG mA
Pulsed gate clamp current 350
PD Power dissipation 500 mW
Human body model (HBM) 4 kV
ESD Rating
Charged device model (CDM) 2 kV
TJ,
Operating junction and storage temperature range –55 to 150 °C
Tstg
Avalanche energy, single pulse ID = 7.4A,
EAS 2.7 mJ
L = 0.1mH, RG = 25Ω

4 Avoid Common Mistakes When Selecting And Designing With Power SLPA021 – NOVEMBER 2024
MOSFETs Submit Document Feedback
Copyright © 2024 Texas Instruments Incorporated
www.ti.com Gate Drive Voltage Specifications

Table 4-3. CSD16415Q5 Absolute Maximum Ratings

TA = 25°C VALUE UNIT
VDS Drain-to-source voltage 25 V
VGS Gate-to-source voltage –12 to 16 V
Continuous drain current (package limited) 100
ID Continuous drain current (silicon limited), TC = 25°C 261 A
Continuous drain current 38
IDM Pulsed drain current, TA = 25°C 200 A
Power dissipation 3.2
PD W
Power dissipation, TC = 25°C 156
TJ,
Operating junction temperature and storage temperature –55 to 150 °C
Tstg
Avalanche energy, single-pulse
EAS 500 mJ
ID = 100A, L = 0.1mH, RG = 25Ω

4.2 Gate-to-source Threshold Voltage, VGS(th)

The gate-to-source threshold voltage, VGS(th) is specified at ID = 250µA in TI FET data sheets. This is where the
FET just begins to conduct current and is lower than the minimum VGS where RDS(on) is specified in the data
sheet. For example, as shown in Table 4-4, typical VGS(th) = 1.75V for the CSD18541F5 60V N-channel FET but
the minimum VGS = 4.5V where RDS(on) is specified in the data sheet.
Table 4-4. CSD18541F5 Electrical Characteristics
TA = 25°C (unless otherwise stated)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
STATIC CHARACTERISTICS
BVDSS Drain-to-source voltage VGS = 0V, IDS = 250μA 60 V
IDSS Drain-to-source leakage current VGS = 0V, VDS = 48V 1 µA
IGSS Gate-to-source leakage current VDS = 0V, VGS = 20V 10 µA
VGS(th) Gate-to-source threshold voltage VDS = VGS, IDS = 250μA 1.4 1.75 2.2 V
VGS = 4.5V, IDS = 1A 57 75
RDS(on) Drain-to-source on-resistance mΩ
VGS = 10V, IDS = 1A 54 65
gfs Transconductance VDS = 6V, IDS = 1A 7.7 S
DYNAMIC CHARACTERISTICS
Ciss Input capacitance 598 777 pF
VGS = 0V, VDS = 30V,
Coss Output capacitance 47 61 pF
ƒ = 1MHz
Crss Reverse transfer capacitance 8.1 10.5 pF
RG Series gate resistance 1200 1600 Ω
Qg Gate charge total (10V) 11 14 nC
Qgd Gate charge gate-to-drain 1.6 nC
VDS = 30V, IDS = 1A
Qgs Gate charge gate-to-source 1.5 nC
Qg(th) Gate charge at Vth 0.8 nC
Qoss Output charge VDS = 30V, VGS = 0V 3.2 nC
td(on) Turnon delay time 572 ns
tr Rise time VDS = 30V, VGS = 4.5V, 540 ns
td(off) Turnoff delay time IDS = 1A, RG = 0Ω 1076 ns
tf Fall time 496 ns
DIODE CHARACTERISTICS
VSD Diode forward voltage ISD = 1A, VGS = 0V 0.8 1 V

SLPA021 – NOVEMBER 2024 Avoid Common Mistakes When Selecting And Designing With Power 5
Submit Document Feedback MOSFETs
Copyright © 2024 Texas Instruments Incorporated
Gate Drive Voltage Specifications www.ti.com

A common mistake is assuming as long as VGS≥ VGS(th), the FET is on and operates as intended in the
application. This is not always the case. To ensure RDS(on) meets the data sheet limits, VGS must always be
greater than or equal to the minimum value where RDS(on) is specified in the data sheet. This is often overlooked
and can cause unexpected problems in the application. A customer using the CSD18541F5 had to change the
design because the application used VGS = 3.3V instead of VGS = 4.5V. As shown in Figure 4-1, operating the
CSD18541F5 with VGS < 4.5V, the slope of the curve is almost vertical and small changes in VGS(th) can result in
exponential changes in RDS(on).
120
TC = 25°C, ID = 1 A

RDS(on) - On-State Resistance (m:)

110 TC = 125°C, ID = 1 A

100

90

80

70

60

50

40
0 2 4 6 8 10 12 14 16 18 20
VGS - Gate-to-Source Voltage (V) D007

Figure 4-1. CSD18541F5 RDS(on) vs. VGS

6 Avoid Common Mistakes When Selecting And Designing With Power SLPA021 – NOVEMBER 2024
MOSFETs Submit Document Feedback
Copyright © 2024 Texas Instruments Incorporated
www.ti.com High-side and Low-side Switches

5 High-side and Low-side Switches

Power MOSFETs are used as both high-side and low-side switches. What is the difference and how is the gate
driven? A high-side switch places the FET between the input supply and the load. A low-side switch places the
FET between the load and ground. Simplified examples are shown in Figure 5-1 and Figure 5-2.

IIN ILOAD IIN Load ILOAD

D S
- D
+ VGS +

VIN + Load VIN Gate Drive G

G
VG
- - Control +
VG VGS
- S
Gate Drive
Control

Figure 5-1. N-channel FET High Side Switch Figure 5-2. N-channel FET Low Side Switch

5.1 Driving a High-side N-channel FET

The gate of a high-side N-channel FET must to be driven to a voltage higher than the input by at least the
minimum value of VGS where RDS(on) is specified in the data sheet. This is because the drain and source are at
approximately the same voltage when the FET is on and VGS = VG – VS = VG – VIN. For example, when using
the CSD18541F5 as a high switch with VIN = 24V, VG≥ VIN + VGS(min) = 24V + 4.5V = 28.5V.
5.2 Driving a Low-side N-channel FET
Driving a low-side N-channel FET is much simpler since the source is grounded and the gate only needs to be
driven to the minimum value of VGS where RDS(on) is specified in the data sheet.
5.3 Driving a High-side P-channel FET
As shown in Figure 5-3, P-channel FETs are mainly used as high-side switches due to the simplicity of driving
the gate. To turn the device on, the gate is pulled down to GND. To turn the device off, the gate is pulled up to
VIN. To avoid damaging the FET, always check the data sheet to make sure that the input voltage, VIN≤ abs max
VGS.
IIN ILOAD

S D
-
+
VGS G
VIN Load
+
-
VG

Gate Drive
Control

Figure 5-3. P-channel FET High Side Switch

SLPA021 – NOVEMBER 2024 Avoid Common Mistakes When Selecting And Designing With Power 7
Submit Document Feedback MOSFETs
Copyright © 2024 Texas Instruments Incorporated
Use a Gate-to-source Resistor www.ti.com

6 Use a Gate-to-source Resistor

A floating or open gate can be a recipe for FET failures. When the gate of the FET is left open, the gate can
charge up to a voltage that unintentionally causes drain current, ID, to flow. This can lead to unwanted behavior
up to and including, catastrophic failure of the FET. As shown in Figure 6-1, adding a 10kΩ to 1MΩ resistor from
gate-to-source is an easy way to make sure the FET is off if the gate is floating.

ID

D
+

G
VDS
+
+ VGS
-
S
RGS -

VGATE

Figure 6-1. N-channel FET with Gate-to-source Resistor, RGS

7 Lowest RDS(on)≠ Lowest Power Loss

Does the MOSFET with the lowest RDS(on) result in the lowest power loss? This depends on the application and
how the FET is being used. Conduction or I2R loss is directly proportional to RDS(on) and, for those applications
such as hot swap, load switch, and OR’ing, where the FET is not switching at 10s or 100s of kHz, the lowest on
resistance device results in the lowest power loss.
In switch-mode applications such as DC-DC converters, switching loss can be a significant portion of the total
MOSFET power loss. RDS(on) is a function of the FET die size and a larger die results in lower RDS(on) for a given
MOSFET process technology and voltage rating. A larger die also has higher charge and capacitance, which
results in increased switching loss. Selecting a FET for a switch-mode application must balance conduction loss
and switching loss to achieve the lowest overall power loss in the FET.
TI has released a number of Excel-based FET selection tools for various applications that take this into account.
For example, the synchronous buck FET selection tool allows the user to input the requirements and compare
up to three different TI FET designs based on power loss, package and 1ku pricing.
8 Summary
Power MOSFETs are versatile devices that are used in a multitude of applications. This article presented some
common mistakes to avoid when selecting and designing with FETs.
9 References
The following documents are further references to learn more about TI MOSFETs:
• Texas Instruments, MOSFET Support and Training Tools, application note
• Texas Instruments, What type of ESD protection does your MOSFET include?, technical article

8 Avoid Common Mistakes When Selecting And Designing With Power SLPA021 – NOVEMBER 2024
MOSFETs Submit Document Feedback
Copyright © 2024 Texas Instruments Incorporated
 IMPORTANT NOTICE AND DISCLAIMER
TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATA SHEETS), DESIGN RESOURCES (INCLUDING REFERENCE
DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, regulatory or other requirements.
These resources are subject to change without notice. TI grants you permission to use these resources only for development of an
application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license
is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you
will fully indemnify TI and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these
resources.
TI’s products are provided subject to TI’s Terms of Sale or other applicable terms available either on ti.com or provided in conjunction with
such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for
TI products.
TI objects to and rejects any additional or different terms you may have proposed. IMPORTANT NOTICE

Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2024, Texas Instruments Incorporated