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DEMP-QP Comprehensive

The document outlines the examination pattern for the M. Tech (Software Engineering) comprehensive exam at Birla Institute of Technology & Science, Pilani. It includes details such as course number, title, exam type, weightage, duration, and specific questions related to digital electronics and microprocessors. The paper serves as a reference and is not fixed, featuring various design and programming tasks for students to complete.

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32 views2 pages

DEMP-QP Comprehensive

The document outlines the examination pattern for the M. Tech (Software Engineering) comprehensive exam at Birla Institute of Technology & Science, Pilani. It includes details such as course number, title, exam type, weightage, duration, and specific questions related to digital electronics and microprocessors. The paper serves as a reference and is not fixed, featuring various design and programming tasks for students to complete.

Uploaded by

Everything is Here
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd

Question Paper Pattern is NOT fixed.

The paper is for reference only

Birla Institute of Technology & Science, Pilani


Work Integrated Learning Programmes Division
M. Tech (Software Engineering) at Wipro Technologies (WASE)
Comprehensive Examination (Regular)

Course Number : SEWP ZC261


Course Title : DIGITAL ELECTRONICS & MICROPROCESSORS
Type of Exam : Open Book No. of Pages: 2
Weightage : 60 % No. of Questions: 6
Duration : 3 Hours
Date of Exam : Session: AN( 2 to 5 PM)

1.(a).An input line x to a serial-to-parallel converter receives a long sequence of binary


digits that must be distributed into four different output [Link] a circuit for
the requirement using decoder and logic gates and show the circuit diagram
(5M)
(b)An assembly line has 3 failsafe sensors and 1 emergency shutdown switch. The Line should keep
moving unless any of the following conditions arise:
 If the emergency switch is pressed.
 If sensor 1 and sensor 2 are activated at the same time.
 If sensor 2 and sensor 3 are activated at the same time.
 If all three sensors are activated at the same time.
(a) Derive the truth table for this system. (3M)
(b) Design, using K-Map techniques, a minimum AND-OR gate network for this system. (2M)
(c) Draw the resulting digital circuit diagram using NAND gates only (2M)

2. Design an interface between CPU 8086 and two chips of 32K X 8 ROM and four chips of 32 K X 8
RAM according to the following memory map (10M)

ROM 1and ROM2 -F0000H-FFFFFH

RAM1 and RAM2-D0000H-DFFFFH

RAM3 and RAM4-E0000H-EFFFFH

3. (a) Write an 8086 ALP to set Carry flag reset Parity flag and keep all other flags unaffected (6M)

(b) The 8 data bytes are stored from memory location E000H to E007H. Write 8086 ALP to transfer
the block of data to new location B001H to B008H.. (4M)

4. (a) Explain the addressing modes and physical address of the following instruction if DS= 1000h
SS= 2000h,BX = 300h ,SI = 200h (4M)
a) MOV [BX+SI], BP
b) MOV CL,[BX+4]

(b)WAP to find out largest number from an array of 16 nos (8-bit) stored sequentially in the memory
locations starting at offset 0500H in the segment 2000H (6M)
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Question Paper Pattern is NOT fixed. The paper is for reference only

5. (a)In m/c language program 8A0Dh code appears, find the instruction corresponding to this
machine instruction code (3M)

(b) For the instruction MOV DL, [SI+30], find Machine Code (3M)
(c) Explain the following (4M)
a) JMP WORD PTR[SI]
b) JMP DWORD PTR[SI]

6. Analyze the synchronous circuit of Fig. (the clock is not shown, but is implicit).
(a) Write down the excitation and output functions.
(3M)
(b) Form the excitation and state tables and state diagram.
(3M)
(c) Give a word description of the circuit operation.
(2M)

XXXXXXX

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