CS3691 EMBEDDED SYSTEMS AND IOT L T P C

3 0 2 4
COURSE OBJECTIVES:
 To learn the internal architecture and programming of an embedded processor.
 To introduce interfacing I/O devices to the processor.
 To introduce the evolution of the Internet of Things (IoT).
 To build a small low-cost embedded and IoT system using Arduino/Raspberry Pi/ open platform.
 To apply the concept of Internet of Things in real world scenario.

UNIT I 8-BIT EMBEDDED PROCESSOR 9

8-Bit Microcontroller – Architecture – Instruction Set and Programming – Programming Parallel Ports –
Timers and Serial Port – Interrupt Handling.
UNIT II EMBEDDED C PROGRAMMING 9
Memory And I/O Devices Interfacing – Programming Embedded Systems in C – Need For RTOS –
Multiple Tasks and Processes – Context Switching – Priority Based Scheduling Policies.
UNIT III IOT AND ARDUINO PROGRAMMING 9
Introduction to the Concept of IoT Devices – IoT Devices Versus Computers – IoT Configurations – Basic
Components – Introduction to Arduino – Types of Arduino – Arduino Toolchain – Arduino Programming
Structure – Sketches – Pins – Input/Output From Pins Using Sketches – Introduction to Arduino Shields –
Integration of Sensors and Actuators with Arduino.
UNIT IV IOT COMMUNICATION AND OPEN PLATFORMS 9
IoT Communication Models and APIs – IoT Communication Protocols – Bluetooth – WiFi – ZigBee –
GPS – GSM modules – Open Platform (like Raspberry Pi) – Architecture – Programming – Interfacing –
Accessing GPIO Pins – Sending and Receiving Signals Using GPIO Pins – Connecting to the Cloud.
UNIT V APPLICATIONS DEVELOPMENT 9
Complete Design of Embedded Systems – Development of IoT Applications – Home Automation – Smart
Agriculture – Smart Cities – Smart Healthcare.
45 PERIODS

PRACTICAL EXERCISES: 30 PERIODS

1. Write 8051 Assembly Language experiments using simulator.

2. Test data transfer between registers and memory.
3. Perform ALU operations.
4. Write Basic and arithmetic Programs Using Embedded C.
5. Introduction to Arduino platform and programming
6. Explore different communication methods with IoT devices (Zigbee, GSM, Bluetooth)
7. Introduction to Raspberry PI platform and python programming.
8. Interfacing sensors with Raspberry PI
9. Communicate between Arduino and Raspberry PI using any wireless medium
10. Setup a cloud platform to log the data
11. Log Data using Raspberry PI and upload to the cloud platform
12. Design an IOT based system
COURSE OUTCOMES:

CO1: Explain the architecture of embedded processors.

CO2: Write embedded C programs.
CO3: Design simple embedded applications.
CO4: Compare the communication models in IOT
CO5: Design IoT applications using Arduino/Raspberry Pi /open platform.
TOTAL:75 PERIODS

TEXTBOOKS :

1. Muhammed Ali Mazidi, Janice Gillispie Mazidi, Rolin D. McKinlay, “The 8051 Microcontroller
and Embedded Systems”, Pearson Education, Second Edition, 2014
2. Robert Barton, Patrick Grossetete, David Hanes, Jerome Henry, Gonzalo Salgueiro, “IoT
Fundamentals: Networking Technologies, Protocols, and Use Cases for the Internet of Things”,
CISCO Press, 2017.

REFERENCES :

1. Michael J. Pont, “Embedded C”, Pearson Education, 2007.

2. Wayne Wolf, “Computers as Components: Principles of Embedded Computer System Design”,
Elsevier, 2006.
3. Andrew N Sloss, D. Symes, C. Wright, “Arm System Developer's Guide”, Morgan Kauffman/
Elsevier, 2006.
4. Arshdeep Bahga, Vijay Madisetti, “Internet of Things – A hands-on approach”, Universities Press, 2015
 Subject Code & Name: CS3691- EMBEDDED SYSTEMS AND IOT

Year/Branch: III YEAR IT Semester: V

UNIT I 8-BIT EMBEDDED PROCESSOR

8-Bit Microcontroller – Architecture – Instruction Set and Programming – Programming Parallel

Ports – Timers and Serial Port – Interrupt Handling.

ARCHITECTURE OF 8051 MICROCONTROLLER

Features:

4K bytes internal ROM

128 bytes internal RAM

Four 8-bit I/O ports (P0 - P3).

Two 16-bit timers/counters

One serial interface

only 1 On chip oscillator (external crystal)

6 interrupt sources (2 external , 3 internal, Reset)

64K external code (program) memory(only read)PSEN

64K external data memory(can be read and write) by RD,WR

Code memory is selectable by EA (internal or external)

External memory can be interfaced when data and code storage capacity
exceed size of the internal memory.

ALU - Arithmetic Logical Unit: This unit is used for the arithmetic calculations.
A-Accumulator: This register is used for arithmetic operations. This is also bit addressable and8
bit register.
B-Register: This register is used in only two instructions MUL AB and DIV AB. This is also
bitaddressable and 8 bit register.
PC-Program Counter:
  Points to the address of next instruction to be executed from ROM
 It is 16 bit register means the 8051 can access program address from 0000H to FFFFH. A
total of 64KB of code.
  Initially PC has 0000H
 PC is incremented after each instruction.
Flag Bits and PSW Register:
→ Used to indicate the Arithmetic condition of Accumulator (ACC).
→ Flag register in 8051 is called as program status word (PSW). This special function register
 PSW is also bit addressable and 8 bit wide means each bit can be set or reset independently.

Structure of RAM or 8051 Register Bank and Stack:

  128 byte RAM is available in 8051.
  Address range of RAM is 00H to 7FH.
 In MC8051, 128 byte visible or user accessible RAM is available which is shown in
 figure.
 Extra 128B RAM which is not user accessible. 80H to FFH used for storage of SFR
(special function register)
Four Register Banks:
 There are four register banks, in each register bank there are eight 8 bit register
 available from R0 to R7
 By default Bank 0 is selected. For Bank 0, R0 has address 00H and R1 has 07H
 For selecting banks we use RS0 and RS1 bit of PSW.
Stack in 8051: RAM locations from 08H to 1FH can be used as stack. Stack is used to store the
data temporarily. Stack is last in first out (LIFO)
 8bit register
 It indicates current RAM address available for stack or it points the top of stack.
  Initially by default at 07H because first location of stack is 08H.
 After each PUSH instruction the SP is incremented by one while in
Microprocessor after PUSH instruction SP is decremented.
 After each POP instruction the SP is decremented
 PIN DIAGRAM

8051 microcontroller IC is a 40 Pin Dual Inline Package IC

PIN Details
• The 8051 has an on-chip oscillator but requires an external clock to run it
 A quartz crystal oscillator is connected to inputs XTAL1 (pin19) and XTAL2 (pin18)
 • RESET pin is an input and is active high (normally low)
• Upon applying a high pulse to this pin, the microcontroller will reset and terminate
 allactivities
• EA‟,“external access’’, is an input pin and must be connected to Vcc or GND
• Normally EA pin is connected to Vcc
• EA pin must be connected toGNDto indicate that the code or data isstored externally.
 
• PSEN,“program store enable’’, is an output pin
 • This pin is connected to theOEpin of the external memory.
• For External Code Memory, PSEN‟ = 0
 • For External Data Memory, PSEN‟ = 1
• ALE pin is used for demultiplexing the address and data.
• The four 8-bit I/O ports P0, P1, P2 and P3 each uses 8 pins.
• Port 0 is also designated as AD0-AD7.
• When connecting an 8051 to an external memory, port 0 provides both address and data.
• The 8051 multiplexes address and data through port 0 to save pins.
• ALE indicates if P0 has address or data.
• When ALE=0, it provides data D0-D7
• When ALE=1, it has address A0-A7
• Port 2 must be used along with P0 to provide the 16-bit address for the external memory.
• P0 provides the lower 8 bits via A0 – A7.
• P2 is used for the upper 8 bits of the 16-bit address, designated as A8 – A15, and it cannot
be used for I/O.

I/O & Port PIN Configuration

 Port 0- Alternate function: Multiplexed Address/data bus (AD0-AD7)
Port 1- Alternate function: Only I/O Ports
Port 2- Alternate function: Higher order address bus (A8-A15)
Port 3- Alternate function: Multiple functions.

PORT 0
 Port 0 pins may serve as inputs, outputs, or, when used together, as a bi-directional low
 order address and data bus for external memory.
 When a pin is to be used as an input, a „1‟ must be written to the corresponding port 0 latch
 by the program, thus turning both of the output transistors off,
 When port 0 is used as an address bus to external memory, internal control signals
switch the address lines to the gates of the Field Effect Transistors (FETs).

PORT 1
  Port 1 pins have no dual functions.
 When a pin is to be used as an input, a „1‟ must be written to the corresponding port 1 latch
by the program, thus turning both of the output transistors off.
 To aid in speeding up switching times when the pin is used as an output. the internal FET
pull up has another FET in parallel with it.

PORT 2
 Port 2 may be used as an input/output port similar in operation to port 1.
 The alternate use of port 2 is to supply a high-order address byte in conjunction with
the port 0 low-order byte to address external memory.
 Port 2 pins are momentarily changed by the address control signals when supplying the
high byte of a 16- bit address.

PORT 3
  Port 3 is an input/output port similar to port 1
 The input and output functions can be programmed under the control of the P3 latches or
 under the control of various other special function registers.
 The port 3 alternate uses are shown in the following table
ADDRESSING MODES OF 8051
An "addressing mode" refers to the way of specifying operand in the instruction. In
summary, the addressing modes are as follows, with an example of each:

Immediate Addressing MOV A,#20h

Internal Direct Addressing MOV A,30h
Internal Indirect Addressing MOV A,@R0
External indirect MOVX A,@DPTR

Each of these addressing modes provides important flexibility.

The addressing modes in 8051 are as follows:
Register addressing : e.g., MOV A,R3
Direct byte addressing : e.g., ADD A,50H
Register indirect addressing : e.g., MOV A,@R0
Immediate addressing : e.g., MOV A,#52H
Register Specific : e.g., SWAP A
Index : e.g., MOVC A,@A+DPTR

Immediate Addressing: Immediate addressing is so-named because the value to be stored in

memory immediately follows the operation code in memory. That is to say, the instruction
itself dictates what value will be stored in memory. For example, the instruction: MOV A,#20h

This instruction uses Immediate Addressing because the Accumulator will be loaded with the
value that immediately follows; in this case 20 (hexadecimal). Immediate addressing is very fast
since the value to be loaded is included in the instruction. However, since the value to be loaded
is fixed at compile-time it is not very flexible.

Direct Addressing: Direct addressing is so-named because the value to be stored in memory
is obtained by directly retrieving it from another memory location. For example: MOV A,30h

This instruction will read the data out of Internal RAM address 30 (hexadecimal) and store it in the
Accumulator. Direct addressing is generally fast since, although the value to be loaded is not
included in the instruction, it is quickly accessible since it is stored in the 8051s Internal RAM. It
is also much more flexible than Immediate Addressing since the value to be loaded is whatever is
found at the given address--which may be variable. Also, it is important to note that when using
direct addressing any instruction which refers to an address between 00h and 7Fh is referring to
Internal Memory. Any instruction which refers to an address between 80h and FFh is referring to
the SFR control registers that control the 8051 microcontroller itself.

Indirect Addressing: Indirect addressing is a very powerful addressing mode which in many
cases provides an exceptional level of flexibility. Indirect addressing is also the only way to access
the extra 128 bytes of Internal RAM found on an 8052. Indirect addressing appears as follows:
MOV A,@R0
This instruction causes the 8051 to analyze the value of the R0 register. The 8051 will then load
the accumulator with the value from Internal RAM which is found at the address indicated by R0.
For example, lets say R0 holds the value 40h and Internal RAM address 40h holds the value 67h.

External Indirect
External memory can also be accessed using a form of indirect addressing.
MOVX A,@DPTR and MOVX @DPTR,A
Both commands utilize DPTR. In these instructions, DPTR must first be loaded with the address
of external memory. Once DPTR holds the correct external memory address, the first command
will move the contents of that external memory address into the Accumulator. The second
command will do the opposite: it will allow to write the value of the Accumulator to the external
memory address pointed to by DPTR.
INSTRUCTION SET OF 8051 MICROCONTROLLER

DATA TRANSFER INSTRUCTIONS:

Data transfer instructions move the content of one register to another. The register the content
of which is moved remains unchanged. If they have the suffix “X” (MOVX), the data is
exchanged with external memory.

Data Transfer Instructions

Mnemonic Description Byte Cycle
MOV A,Rn Moves the register to the accumulator 1 1
MOV A,direct Moves the direct byte to the accumulator 2 2
MOV A,@Ri Moves the indirect RAM to the accumulator 1 2
MOV A,#data Moves the immediate data to the accumulator 2 2
MOV Rn,A Moves the accumulator to the register 1 2
MOV Rn,direct Moves the direct byte to the register 2 4
MOV Rn,#data Moves the immediate data to the register 2 2
MOV direct,A Moves the accumulator to the direct byte 2 3
MOV direct,Rn Moves the register to the direct byte 2 3
MOV direct,direct Moves the direct byte to the direct byte 3 4
MOV direct,@Ri Moves the indirect RAM to the direct byte 2 4
MOV direct,#data Moves the immediate data to the direct byte 3 3
MOV @Ri,A Moves the accumulator to the indirect RAM 1 3
MOV @Ri,direct Moves the direct byte to the indirect RAM 2 5
MOV @Ri,#data Moves the immediate data to the indirect RAM 2 3
MOV DPTR,#data Moves a 16-bit data to the data pointer 3 3

MOVC Moves the code byte relative to the DPTR to the accumulator
A,@A+DPTR (address=A+DPTR) 1 3
Moves the code byte relative to the PC to the accumulator
MOVC A,@A+PC (address=A+PC) 1 3
MOVX A,@Ri Moves the external RAM (8-bit address) to the accumulator 1 3-10
MOVX A,@DPTR Moves the external RAM (16-bit address) to the accumulator 1 3-10
MOVX @Ri,A Moves the accumulator to the external RAM (8-bit address) 1 4-11
MOVX @DPTR,A Moves the accumulator to the external RAM (16-bit address) 1 4-11
PUSH direct Pushes the direct byte onto the stack 2 4
POP direct Pops the direct byte from the stack 2 3
XCH A,Rn Exchanges the register with the accumulator 1 2
XCH A,direct Exchanges the direct byte with the accumulator 2 3
XCH A,@Ri Exchanges the indirect RAM with the accumulator 1 3
XCHD A,@Ri Exchanges the low-order nibble indirect RAM with the accumulator 1 3
ARITHMETIC INSTRUCTIONS
Arithmetic instructions perform several basic operations such as addition, subtraction,
division, multiplication etc. After execution, the result is stored in the first operand. For
example:
ADD A,R1 - The result of addition (A+R1) will be stored in the accumulator.
Mnemonic Description
ADD A,Rn Adds the register to the accumulator
ADD A,direct Adds the direct byte to the accumulator
ADD A,@Ri Adds the indirect RAM to the accumulator
ADD A,#data Adds the immediate data to the accumulator
ADDC A,Rn Adds the register to the accumulator with a carry flag
ADDC A,direct Adds the direct byte to the accumulator with a carry flag
ADDC A,@Ri Adds the indirect RAM to the accumulator with a carry flag
ADDC A,#data Adds the immediate data to the accumulator with a carry flag
SUBB A,Rn Subtracts the register from the accumulator with a borrow
SUBB A,direct Subtracts the direct byte from the accumulator with a borrow
SUBB A,@Ri Subtracts the indirect RAM from the accumulator with a borrow
SUBB A,#data Subtracts the immediate data from the accumulator with a borrow
INC A Increments the accumulator by 1
INC Rn Increments the register by 1
INC direct Increments the direct byte by 1
INC @Ri Increments the indirect RAM by 1
DEC A Decrements the accumulator by 1
DEC Rn Decrements the register by 1
DEC direct Decrements the direct byte by 1
DEC @Ri Decrements the indirect RAM by 1
INC DPTR Increments the Data Pointer by 1
MUL AB Multiplies A and B
DIV AB Divides A by B
DA A Decimal adjustment of the accumulator according to BCD code
LOGIC INSTRUCTIONS:
Logic instructions perform logic operations upon corresponding bits of two registers.
After execution, the result is stored in the first operand.

Mnemonic Description
ANL A,Rn AND register to accumulator
ANL A,direct AND direct byte to accumulator
ANL A,@Ri AND indirect RAM to accumulator
ANL A,#data AND immediate data to accumulator
ANL direct,A AND accumulator to direct byte
ANL direct,#data AND immediae data to direct register
ORL A,Rn OR register to accumulator
ORL A,direct OR direct byte to accumulator
ORL A,@Ri OR indirect RAM to accumulator
ORL direct,A OR accumulator to direct byte
ORL direct,#data OR immediate data to direct byte
XRL A,Rn Exclusive OR register to accumulator
XRL A,direct Exclusive OR direct byte to accumulator
XRL A,@Ri Exclusive OR indirect RAM to accumulator
XRL A,#data Exclusive OR immediate data to accumulator
XRL direct,A Exclusive OR accumulator to direct byte
XRL direct,#data Exclusive OR immediate data to direct byte
CLR A Clears the accumulator
CPL A Complements the accumulator (1=0, 0=1)
SWAP A Swaps nibbles within the accumulator
RL A Rotates bits in the accumulator left
RLC A Rotates bits in the accumulator left through carry
RR A Rotates bits in the accumulator right
RRC A Rotates bits in the accumulator right through carry

ROTATE AND SWAP INSTRUCTIONS:

SWAP A Swaps nibbles within the accumulator

RL A Rotates bits in the accumulator left
RLC A Rotates bits in the accumulator left through carry
RR A Rotates bits in the accumulator right
RRC A Rotates bits in the accumulator right through carry

SWAP A - Swaps nibbles within the accumulator

Description: A nibble refers to a group of 4 bits within one register (bit0-bit3 and bit4-bit7).
This instruction interchanges high and low nibbles of the accumulator.
Syntax: SWAP A;
Byte: 1 (instruction code);
STATUS register flags: No flags are affected;
EXAMPLE:
Before execution: A=E1h (11100001)bin.
After execution: A=1Eh (00011110)bin.
RL A - Rotates the accumulator one bit left
Description: Eight bits in the accumulator are rotated one bit left, so that the bit 7 is rotated
into the bit 0 position.
Syntax: RL A;
Byte: 1 (instruction code);
STATUS register flags: No flags affected;

EXAMPLE:
Before execution: A= C2h (11000010 Bin.)
After execution: A=85h (10000101 Bin.)

RLC A - Rotates the accumulator one bit left through the carry flag
Description: All eight bits in the accumulator and carry flag are rotated one bit left. After
this operation, the bit 7 is rotated into the carry flag position and the carry flag is rotated into the bit
0 position.
Syntax: RLC A;
Byte: 1 (instruction code); STATUS register flags: C; EXAMPLE:
Before execution: A= C2h (11000010 Bin.) C=0
After execution: A= 85h (10000100 Bin.) C=1

RR A - Rotates the accumulator one bit right

Description: All eight bits in the accumulator are rotated one bit right so that the bit 0 is
rotated into the bit 7 position.
Syntax: RR A;
Byte: 1 (instruction code);
STATUS register flags: No flags affected;
EXAMPLE:
Before execution: A= C2h (11000010 Bin.)
After execution: A= 61h (01100001 Bin.)
RRC A - Rotates the accumulator one bit right through the carry flag Description: All eight
bits in the accumulator and carry flag are rotated one bit right. After
this operation, the carry flag is rotated into the bit 7 position and the bit 0 is rotated into the
carry flag position.

Syntax: RRC A;
Byte: 1 (instruction code); STATUS register flags: C; EXAMPLE:
Before execution: A= C2h (11000010 Bin.) C=0
After execution: A= 61h (01100001 Bin.) C=0

BRANCH INSTRUCTIONS OR CONTROL TRANSFER INSTRUCTIONS:

There are two kinds of branch instructions:
Unconditional jump instructions: a jump to a new program location is executed without any
condition. Conditional jump instructions: a jump to a new program location is executed only
if a specified condition is met. Otherwise, the program normally proceeds with the next
instruction. Program Control Instructions
The 8051 supports three kind of jump instructions:
1. LJMP (long jump)
2. SJMP (short jump)
LCALL:
This instruction is used to call a subroutine at a specified address. The address is 16 bits long
so the call can be made to any location within the 64KByte memory space. When a LCALL
instruction is executed the current PC content is automatically pushed onto the stack of the PC.
When the program returns from the subroutine the PC contents is returned from the stack so
that the program can resume operation from the point where the LCALL was made The return
from subroutine is achieved using the RET instruction, which simply pops the PC back from
the stack.
ACALL:

The ACALL instruction is logically similar to the LCALL but has a limited address range
similar to the AJMP instruction. CALL is a generic call instruction supported by many 8051
assemblers. The assembler will decide which type of call instruction, LCALL or ACALL, to
use so as to choose the most efficient instruction.

Mnemonic Description
ACALL addr11 Absolute subroutine call
LCALL addr16 Long subroutine call
RET Returns from subroutine
RETI Returns from interrupt subroutine
AJMP addr11 Absolute jump
LJMP addr16 Long jump
Short jump (from –128 to +127 locations relative to the following instruction)
SJMP rel
JC rel Jump if carry flag is set. Short jump.
JNC rel Jump if carry flag is not set. Short jump.
JB bit,rel Jump if direct bit is set. Short jump.
JBC bit,rel Jump if direct bit is set and clears bit. Short jump.
JMP @A+DPTR Jump indirect relative to the DPTR
JZ rel Jump if the accumulator is zero. Short jump.
JNZ rel Jump if the accumulator is not zero. Short jump.
Compares direct byte to the accumulator and jumps if not equal. Short jump.
CJNE A,direct,rel
Compares immediate data to the accumulator and jumps if not equal. Short jump.
CJNE A,#data,rel
CJNE Rn,#data,rel Compares immediate data to the register and jumps if not equal. Short jump.
CJNE Compares immediate data to indirect register and jumps if not equal. Short jump.
@Ri,#data,rel
DJNZ Rn,rel Decrements register and jumps if not 0. Short jump.
DJNZ Rx,rel Decrements direct byte and jump if not 0. Short jump.
NOP No operation
PROGRAMS
8 Bit Addition (Immediate Addressing)
LABEL MNEMONIC OPERAND COMMENTS
CLR C Clear CY Flag
MOV A, data1 Get the data1 in Accumulator
ADDC A, # data 2 Add the data1 with data2
MOV DPTR, #4500H Initialize the memory location
MOVX @ DPTR, A Store the result in memory location
L1 SJMP L1 Stop the program

8 Bit Subtraction (Immediate Addressing)

LABEL MNEMONIC OPERAND COMMENTS
CLR C Clear CY flag
MOV A, # data1 Store data1 in accumulator
SUBB A, # data2 Subtract data2 from data1
MOV DPTR, # 4500 Initialize memory location
MOVX @ DPTR, A Store the difference in memory
location
L1 SJMP L1 Stop

8 Bit Multiplication
LABEL MNEMONIC OPERAND COMMENTS
MOV A ,#data1 Store data1 in accumulator
MOV B, #data2 Store data2 in B reg
MUL A,B Multiply both
MOV DPTR, # Initialize memory location
4500H
MOVX @ DPTR, A Store lower order result
INC DPTR Go to next memory location
MOV A,B Store higher order result
MOV @ DPTR, A
STOP SJMP STOP Stop

8 Bit Division
LABEL MNEMONIC OPERAND COMMENTS
MOV A, # data1 Store data1 in accumulator
MOV B, # data2 Store data2 in B reg
DIV A,B Divide
MOV DPTR, # 4500H Initialize memory location
MOVX @ DPTR, A Store remainder
INC DPTR Go to next memory location
MOV A,B Store quotient
MOV @ DPTR, A
STOP SJMP STOP Stop
 Timer Classification
The 8051 has two timers/counters. They can be used either
as timers to generate a time delay or as counters to count
events happening outside the microcontroller. The 8051 has
two timers:

• Timer 0,
• Timer 1.

They can be used either as timers or as event counters.

Basic registers of the timer: Both Timer 0 and Timer 1 are 16

bits wide. Since the 8051has an 8-bit architecture, each 16-
bit timer is accessed as two separate registers of low byte
and high byte.
8051 Timer / Counter
 TMOD Register

GATE
• Gating control when set. Timer/counter is enable only while the INTx pin is high and
the TRx control pin is set. When cleared, the timer is enabled whenever the TRx
control bit is set.
 Timers of 8051 do starting and stopping by either software or hardware control.
 In using software to start and stop the timer where GATE=0
 The start and stop of the timer are controlled by way of software by the
TR(timer start) bits TR0 and TR1
 To start Timer, TR0 or TR1 must be high. or To stop Timer, TR0 or TR1 must be low.
These instructions start and stop the timers as long as GATE=0 in the TMOD register
 The hardware way of starting and stopping the timer by an external source is
achieved by making GATE=1 in the TMOD register
 TMOD Register

C/T
 Timer or counter selected Cleared for timer operation (input from internal
system clock). Set for counter operation (input from Tx input pin).
 If C/T = 0, it is used as a timer for time delay generation. The clock source for
the time delay is the crystal frequency of the 8051.
 If C/T = 1, it is used as a counter for event counters to count events
happening outside the microcontroller
TMOD Register
TCON Register
Timers – Mode of Operations
Timer 0
Timer 0 – Mode 0
Timer 0 – Mode 1
Timer 0 – Mode 2
Timer 0 – Mode 3
Timer 1
Timer 1 – Mode 0
Timer 1 – Mode 1
Timer 1 – Mode 2
Interrupts
Interrupts
Interrupts
6 Interrupts in 8051
6 Interrupts in 8051
IE Register
Interrupt Priority
Interrupt Priority Register
 Serial Interface
 The serial port of 8051 is full duplex, i.e., it can transmit
and receive simultaneously.
 The register SBUF is used to hold the data. The special
function register SBUF is physically two registers. One is,
write-only and is used to hold data to be transmitted out
of the 8051 via TXD.
 The other is, read-only and holds the received data from
external sources via RXD. Both mutually exclusive
registers have the same address 099H.
Serial Interface
8051 Serial Port
SBUF Register
SCON Register
8051 Serial Port – Mode 0
8051 Serial Port – Mode 1
8051 Serial Port – Mode 2
8051 Serial Port – Mode 3
UNIT - 2 EMBEDDED C PROGRAMMING
Interfacing a Microcontroller to Keyboard
When you press a key on your computer, you are activating a switch. There are
many different ways of making these switches. An overview of the construction and
operation of some of the most common types.
 Mechanical key switches: In mechanical-switch keys, two pieces of metal are
pushed together when you press the key. The actual switch elements are often made of a
phosphor-bronze alloy with gold platting on the contact areas. The key switch usually
contains a spring to return the key to the nonpressed position and perhaps a small piece of
foam to help damp out bouncing.
Some mechanical key switches now consist of a molded silicon dome with a small
piece of conductive rubber foam short two trace on the printed-circuit board to produce the
key pressed signal.
Mechanical switches are relatively inexpensive but they have several disadvantages.
First, they suffer from contact bounce. A pressed key may make and break contact several
times before it makes solid contact.
Second, the contacts may become oxidized or dirty with age so they no longer make
a dependable connection.
Higher- quality mechanical switches typically have a rated life time of about 1
million keystrokes. The silicone dome type typically last 25 million keystrokes.
 Membrane key switches: These switches are really a special type of mechanical
switches. They consist of a three-layer plastic or rubber sandwich.
The top layer has a conductive line of silver ink running under each key position.
The bottom layer has a conductive line of silver ink running under each column of keys.

Fig .5.1 Mechanical key and its response to key press

The key board interfaced is a matrix keyboard. This key board is designed with a
particular rows and columns. These rows and columns are connected to the microcontroller
through its ports of the micro controller 8051. We normally use 8*8 matrix key board. So
only two ports of 8051 can be easily connected to the rows and columns of the key board.
Whenever a key is pressed, a row and a column gets shorted through that pressed
key and all the other keys are left open. When a key is pressed only a bit in the port goes
high which indicates microcontroller that the key is pressed. By this high on the bit key in
the corresponding column is identified.
Once we are sure that one of key in the key board is pressed next our aim is to identify that
key. To do this we firstly check for particular row and then we check the corresponding
column the key board.
To check the row of the pressed key in the keyboard, one of the row is made high by making
one of bit in the output port of 8051 high . This is done until the row is found out.
Once we get the row next out job is to find out the column of the pressed key. The
column is detected by contents in the input ports with the help of a counter. The content of
the input port is rotated with carry until the carry bit is set.
The contents of the counter is then compared and displayed in the display. This display is
designed using a seven segment display and a BCD to seven segment decoder IC 7447. The
BCD equivalent number of counter is sent through output part of 8051 displays the number
of pressed key.

Fig 5.2 Interfacing Keyboard to 8051 Microcontroller

Fig. 5.3 Interfacing To Alphanumeric Displays

• To give directions or data values to users, many microprocessor-controlled instruments

and machines need to display letters of the alphabet and numbers. In systems where a large
amount of data needs to be displayed a CRT is used to display the data. In system where
only a small amount of data needs to be displayed, simple digit-type displays are often used.
• There are several technologies used to make these digit-oriented displays but we are
discussing only the two major types.
• These are light emitting diodes (LED) and liquid-crystal displays (LCD).
• LCD displays use very low power, so they are often used in portable, battery-powered
instruments. They do not emit their own light, they simply change the reflection of available
light. Therefore, for an instrument that is to be used in low-light conditions, you have to
include a light source for LCDs or use LEDs which emit their own light.
6.3 PRIORITY-BASED SCHEDULING
Now that we have a priority-based context switching mechanism, we have to
determine an algorithm by which to assign priorities to processes. After assign-
ing priorities, the OS takes care of the rest by choosing the highest-priority ready
process. There are two major ways to assign priorities: static priorities that do not
change during execution and dynamic priorities that do change. We will look at
examples of each in this section.

6.3.1 Rate-Monotonic Scheduling

Rate-monotonic scheduling (RMS), introduced by Liu and Layland [Liu73], was
one of the first scheduling policies developed for real-time systems and is still very
widely used. RMS is a static scheduling policy. It turns out that these fixed priorities
are sufficient to efficiently schedule the processes in many situations.
The theory underlying RMS is known as rate-monotonic analysis (RMA).This
theory, as summarized below, uses a relatively simple model of the system.
■ All processes run periodically on a single CPU.
■ Context switching time is ignored.
 ■ There are no data dependencies between processes.
■ The execution time for a process is constant.
■ All deadlines are at the ends of their periods.
■ The highest-priority ready process is always selected for execution.
The major result of RMA is that a relatively simple scheduling policy is opti-
mal under certain conditions. Priorities are assigned by rank order of period, with
the process with the shortest period being assigned the highest priority. This
fixed-priority scheduling policy is the optimum assignment of static priorities to
processes, in that it provides the highest CPU utilization while ensuring that all
processes meet their deadlines.
Example 6.3 illustrates RMS.

Example 6.3
Rate-monotonic scheduling
Here is a simple set of processes and their characteristics.

Process Execution time Period

P1 1 4
P2 2 6
P3 3 12

Applying the principles of RMA, we give P1 the highest priority, P2 the middle priority,
and P3 the lowest priority. To understand all the interactions between the periods, we need to
construct a time line equal in length to hyperperiod, which is 12 in this case.

P3

P2

P1

0 2 4 6 8 10 12
Time

All three periods start at time zero. P1’s data arrive first. Since P1 is the highest-priority
process, it can start to execute immediately. After one time unit, P1 finishes and goes out
of the ready state until the start of its next period. At time 1, P2 starts executing as the
highest-priority ready process. At time 3, P2 finishes and P3 starts executing. P1’s next iteration
starts at time 4, at which point it interrupts P3. P3 gets one more time unit of execution between
the second iterations of P1 and P2, but P3 does not get to finish until after the third iteration
of P1.
Consider the following different set of execution times for these processes, keeping the
same deadlines.

Process Execution time Period

P1 2 4
P2 3 6
P3 3 12

In this case, we can show that there is no feasible assignment of priorities that guarantees
scheduling. Even though each process alone has an execution time significantly less than its
period, combinations of processes can require more than 100% of the available CPU cycles.
For example, during one 12 time-unit interval, we must execute P1 three times, requiring
6 units of CPU time; P2 twice, costing 6 units of CPU time; and P3 one time, requiring 3 units
of CPU time. The total of 6 + 6 + 3 = 15 units of CPU time is more than the 12 time units
available, clearly exceeding the available CPU capacity.

Liu and Layland [Liu73] proved that the RMA priority assignment is optimal
using critical-instant analysis. We define the response time of a process as the
time at which the process finishes. The critical instant for a process is defined
as the instant during execution at which the task has the largest response time. It
is easy to prove that the critical instant for any process P, under the RMA model,
occurs when it is ready and all higher-priority processes are also ready—if we
change any higher-priority process to waiting, then P’s response time can only go
down.
We can use critical-instant analysis to determine whether there is any feasible
schedule for the system. In the case of the second set of execution times in
Example 6.3,there was no feasible schedule. Critical-instant analysis also implies that
priorities should be assigned in order of periods. Let the periods and computation
times of two processes P1 and P2 be ␶1 , ␶2 and T1 , T2 , with ␶1 < ␶2 . We can
generalize the result of Example 6.3 to show the total CPU requirements for the
two processes in two cases. In the first case, let P1 have the higher priority. In the
worst case we then execute P2 once during its period and as many iterations of P1
as fit in the same interval. Since there are ␶2 /␶1  iterations of P1 during a single
period of P2 , the required constraint on CPU time, ignoring context switching
overhead, is
 
␶2
T1  T2  ␶2 . (6.4)
␶1
 If, on the other hand, we give higher priority to P2 , then critical-instant analysis
tells us that we must execute all of P2 and all of P1 in one of P1 ’s periods in the
worst case:

T1  T2  ␶1 . (6.5)

There are cases where the first relationship can be satisfied and the second
cannot, but there are no cases where the second relationship can be satisfied and
the first cannot. We can inductively show that the process with the shorter period
should always be given higher priority for process sets of arbitrary size. It is also
possible to prove that RMS always provides a feasible schedule if such a schedule
exists.
The bad news is that,although RMS is the optimal static-priority schedule,it does
not always allow the system to use 100% of the available CPU cycles. In the RMS
framework, the total CPU utilization for a set of n tasks is

n
Ti
U  . (6.6)
␶i
i1

The fraction Ti /␶i is the fraction of time that the CPU spends executing task i.
It is possible to show that for a set of two tasks under RMS scheduling, the CPU
utilization U will be no greater than 2(21/2  1)  ∼ 0.83. In other words, the CPU
will be idle at least 17% of the time. This idle time is due to the fact that priorities
are assigned statically; we see in the next section that more aggressive scheduling
policies can improve CPU utilization. When there are m tasks with fixed priorities,
the maximum processor utilization is
U  m(21/m  1). (6.7)

As m approaches infinity, the least upper bound to CPU utilization is ln 2 

0.69—the CPU will be idle 31% of the time. This does not mean that we can never
use 100% of the CPU. If the periods of the tasks are arranged properly, then we can
schedule tasks to make use of 100% of the CPU. But the least upper bound of 69%
tells us that RMS can in some cases deliver utilizations significantly below 100%.
The implementation of RMS is very simple. Figure 6.12 shows C code for an
RMS scheduler run at the OS’s timer interrupt. The code merely scans through the
list of processes in priority order and selects the highest-priority ready process
to run. Because the priorities are static, the processes can be sorted by priority
in advance before the system starts executing. As a result, this scheduler has an
asymptotic complexity of O(n), where n is the number of processes in the system.
(This code assumes that processes are not created dynamically. If dynamic process
creation is required, the array can be replaced by a linked list of processes, but
the asymptotic complexity remains the same.) The RMS scheduler has both low
asymptotic complexity and low actual execution time, which helps minimize the
discrepancies between the zero-context-switch assumption of RMA and the actual
execution of an RMS system.
 /* processes[] is an array of process activation records,
stored in order of priority, with processes[0] being
the highest-priority process */
Activation_record processes[NPROCESSES];

void RMA(int current) { /* current ⫽ currently executing

process */
int i;
/* turn off current process (may be turned back on) */
processes[current].state ⫽ READY_STATE;
/* find process to start executing */
for (i ⫽ 0; i < NPROCESSES; i⫹⫹)
if (processes[i].state ⫽⫽ READY_STATE) {
/* make this the running process */
processes[i].state ⫽⫽ EXECUTING_STATE;
break;
}
}

FIGURE 6.12
C code for rate-monotonic scheduling.

6.3.2 Earliest-Deadline-First Scheduling

Earliest deadline first (EDF) is another well-known scheduling policy that was
also studied by Liu and Layland [Liu73]. It is a dynamic priority scheme—it changes
process priorities during execution based on initiation times. As a result, it can
achieve higher CPU utilizations than RMS.
The EDF policy is also very simple: It assigns priorities in order of deadline. The
highest-priority process is the one whose deadline is nearest in time,and the lowest-
priority process is the one whose deadline is farthest away. Clearly, priorities must
be recalculated at every completion of a process. However, the final step of the OS
during the scheduling procedure is the same as for RMS—the highest-priority ready
process is chosen for execution.
Example 6.4 illustrates EDF scheduling in practice.

Example 6.4
Earliest-deadline-first scheduling
Consider the following processes:

Process Execution time Period

P1 1 3
P2 1 4
P3 2 5

The hyperperiod is 60. In order to be able to see the entire period, we write it as a table:
Time Running process Deadlines

0 P1
1 P2
2 P3 P1
3 P3 P2
4 P1 P3
5 P2 P1
6 P1
7 P3 P2
8 P3 P1
9 P1 P3
10 P2
11 P3 P1, P2
12 P1
13 P3
14 P2 P1, P3
15 P1 P2
16 P2
17 P3 P1
18 P1
19 P3 P2, P3
20 P2 P1
21 P1
22 P3
23 P3 P1, P2
24 P1 P3
25 P2
26 P3 P1
27 P1 P2
28 P3
29 P2 P1, P3
30 idle
31 P1 P2
32 P3 P1
33 P3
34 P1 P3
35 P2 P1, P2
36 P1
37 P2
38 P3 P1
39 P3 P2, P3
40 P1

(Continued )
 Time Running process Deadlines

41 P2 P1
42 P1
43 P3 P2
44 P3 P1, P3
45 P1
46 P2
47 P3 P1, P2
48 P3
49 P1 P3
50 P2 P1
51 P1 P2
52 P3
53 P3 P1
54 P2 P3
55 P1 P2
56 P2 P1
57 P1
58 P3
59 P3 P1, P2, P3

There is one time slot left at t  30, giving a CPU utilization of 59/60.

Liu and Layland showed that EDF can achieve 100% utilization. A feasible sched-
ule exists if the CPU utilization (calculated in the same way as for RMA) is 1. They
also showed that when an EDF system is overloaded and misses a deadline, it will
run at 100% capacity for a time before the deadline is missed.
The implementation of EDF is more complex than the RMS code. Figure 6.13
outlines one way to implement EDF. The major problem is keeping the processes
sorted by time to deadline—since the times to deadlines for the processes change
during execution, we cannot presort the processes into an array, as we could for
RMS. To avoid resorting the entire set of records at every change, we can build a
binary tree to keep the sorted records and incrementally update the sort. At the end
of each period,we can move the record to its new place in the sorted list by deleting
it from the tree and then adding it back to the tree using standard tree manipulation
techniques. We must update process priorities by traversing them in sorted order,
so the incremental sorting routines must also update the linked list pointers that let
us traverse the records in deadline order. (The linked list lets us avoid traversing the
tree to go from one node to another,which would require more time.) After putting
in the effort to building the sorted list of records, selecting the next executing
process is done in a manner similar to that of RMS. However, the dynamic sorting
adds complexity to the entire scheduling process. Each update of the sorted list
 Deadline_tree

... ...

Activation_record Activation_record

Data structure
/* linked list, sorted by deadline */
Activation_record *processes;
/* data structure for sorting processes */
Deadline_tree *deadlines;

void expired_deadline(Activation_record *expired){

remove(expired); /* remove from the deadline-sorted list */
add(expired,expired->deadline); /* add at new deadline */
}

Void EDF(int current) { /* current ⫽ currently executing process */

int i;
/* turn off current process (may be turned back on) */
processes->state ⫽ READY_STATE;
/* find process to start executing */
for (alink = processes; alink !⫽ NULL; alink ⫽ alink->next_deadline)
if (processes->state ⫽⫽ READY_STATE) {
/* make this the running process */
processes->state ⫽⫽ EXECUTING_STATE;
break;
}
}
Code

FIGURE 6.13
C code for earliest-deadline-first scheduling.

requires O(log n) steps. The EDF code is also significantly more complex than the
RMS code.
Examples:
 Priority-based scheduling
Preemptive Scheduling:
Preemptive scheduling is used when a process switches from the running
state to the ready state or from the waiting state to the ready state. The
resources (mainly CPU cycles) are allocated to the process for a limited
amount of time and then taken away, and the process is again placed back in
the ready queue if that process still has CPU burst time remaining. That
process stays in the ready queue till it gets its next chance to execute.

Preemptive scheduling has a number of advantages and disadvantages.

The following are preemptive scheduling’s benefits and drawbacks:
Advantages
1. Because a process may not monopolize the processor, it is a more
reliable method.
2. Each occurrence prevents the completion of ongoing tasks.
3. The average response time is improved.
4. Utilizing this method in a multi-programming environment is more
advantageous.
5. The operating system makes sure that every process using the CPU is
using the same amount of CPU time.
Disadvantages
1. Limited computational resources must be used.
2. Suspending the running process, change the context, and dispatch the
new incoming process all take more time.
3. The low-priority process would have to wait if multiple high-priority
processes arrived at the same time.
Non-Preemptive Scheduling:

Non-preemptive Scheduling is used when a process terminates, or a

process switch from running to the waiting state. In this scheduling, once
the resources (CPU cycles) are allocated to a process, the process holds the
CPU till it gets terminated or reaches a waiting state. In the case of non-
preemptive scheduling does not interrupt a process running CPU in the
middle of the execution. Instead, it waits till the process completes its CPU
burst time, and then it can allocate the CPU to another process.

Non-preemptive scheduling has both advantages and disadvantages. The

following are non-preemptive scheduling’s benefits and drawbacks:
Advantages
1. It has a minimal scheduling burden.
2. It is a very easy procedure.
3. Less computational resources are used.
4. It has a high throughput rate.
Disadvantages
1. Its response time to the process is super.
2. Bugs can cause a computer to freeze up.
Examples:
UNIT 3 IOT AND ARDUINO PROGRAMMING
 ggggg

What is Arduino? Explain its feature. Discuss types of

Arduino board.
Explain in details about Arduino Programming with examples.

Pot-Fading Led:
void setup()
{
pinMode(LED_BUILTIN, OUTPUT);
pinMode(10, OUTPUT);
pinMode(A0, INPUT);
[Link](9600);
}
void loop()
{
int sensorValue = analogRead(A0);
[Link](sensorValue);
int brightness = map(sensorValue, 0, 1023, 0, 255);
analogWrite(10, brightness);
delay(50);
}
To Control Servo Motor:
#include <Servo.h>
Servo myservo; // create servo object to control a servo
int pos = 0;
void setup() {
[Link](9);
}
void loop() {
/* goes from 0 degrees to 180 degrees in steps of 1 degree tell servo to go to position in
variable 'pos' waits 15ms for the servo to reach the position */
for (pos = 0; pos <= 180; pos += 1) {
[Link](pos);
delay(15);
}
/* goes from 180 degrees to 0 degrees tell servo to go to position in variable 'pos' waits
15ms for the servo to reach the position */
for (pos = 180; pos >= 0; pos -= 1)
{
[Link](pos);
delay(15);
}
}
 UNIT 4
IOT COMMUNICATION
AND
OPEN PLATFORMS
 IoT Communication Protocols
Explain in detail about BLUETOOTH.
Nov/Dec 2011/April/May 2011/ April/May 2013 /May/June 2014/Nov/Dec 2017
It is a wireless LAN technology designed to connect devices of different functions such as
telephones, computers, mobiles or cell phones, cameras and printers so [Link] LAN is an adhoc
network, which means that the network is formed spontaneously find each other and make a network
called piconet.

Architecture: Bluetooth defines 2 types of networks:

 Piconet
 Scattered Net
i) Piconet
It is a small net. It has up to 8 stations, one of which is called the primary and rest is [Link]
communication between these two is one to one or one to more. The 8 stations is parked state and
synchronized with primary.

ii) Scattered Net:

Piconets can be combined as scattered net. A secondary station in one piconet can be the primary in
another piconet.

Scattered Net
Bluetooth devices:

It has a built in short range radio transmitter. The current data rate is 1mbps with 2.4 GHz
bandwidth.

Bluetooth layers

Radio layer: It is roughly equivalent to physical layer. Bluetooth are low power have a range of 10
meters.

Band: Bluetooth uses a 2.4 GHz band divided into 79 channels of 1 MHz each. Bluetooth uses FHSS
(Frequency Flopping Spread Spectrum Technique) and to transmit bits to a signal a Bluetooth uses the
FSK is called Gaussian FSK (GFSK).

Base Band Layer:It is roughly equivalent to the MAC sub layer in LAN. The access method is
TDMA. The communication each other that is primary & secondary is using time slots.

Single Secondary Communication: If the piconet has only one secondary, the TDMA operation is
very simple. The time is divided into slots of 625 µsec. The primary & secondary communication is
half duplex mode.
Multiple – Secondary Communication:The process is little more, if there is more than one secondary
in the piconet.

Physical link:

There are 2 types of links can be carried between primary & secondary.

i) SCO link (Synchronous Connection Oriented)

It is used when avoiding latency (delay in data delivery) and is more important than
integrity (error free delivery).

ii) ACL link (Asynchronous Connectionless Link)

It is used when data integrity is more important than latency.

Frame Format Types:

Access code: It is an identifier of the primary to distinguish the frames of one piconet from another.
Header: Address: It consist of source & destination information (address 3 bit field)

Type: It defines the type of data coming from upper layer.

 F: It is flow control (1bit)
 A: Acknowledgement (1bit field)
 S: It holds a sequence number (1 bit field)
 HEC: Header Error Correction and detection field.
L2 CAP layer: (LL CAP Layer)

i) It is a logical link control and adaptation protocol.

ii) It is used for data exchange on an ACL link.

i) The duties of L2 CAP are multiplexing, segmentation & reassembling, quality of

services (QoS) & group management.
Explain in detail about WiFi.
Internet Access
Explain in detail about Zigbee technology with neat diagrams
UNIT 5 APPLICATIONS DEVELOPMENT