WSEAS TRANSACTIONS on ELECTRONICS

DOI: 10.37394/232017.2023.14.8 Yashu Swami

Design Guidelines for Low Power Embedded Systems using Low Power
Electronics

YASHU SWAMI
Department of ECE,
Aditya Engineering College (A),
Surampalem,
INDIA

Abstract: - The design of Low Power Embedded Systems (LPES) and IoT products may include a variety of
power management techniques, or they may incorporate sophisticated on-chip capabilities that assist in reduced
power usage. The power management and low power consumption of embedded systems are also enabled by
complex algorithms, and every Low Power System (LPS) may require a mix of approaches to avoid using extra
battery power. There are several strategies we may use when creating an LPES that must be extremely power
efficient while simultaneously offering the necessary degree of computational capability. It all depends on the
design specifications that must be met. Then, if at all feasible, choose the appropriate low-power components
from Low Power Electronics (LPE). After studying and reviewing multiple LPES real-time projects, we
compiled a list of a few strategies we may use to approach low-power design and consumption for embedded
systems. Following the analysis of numerous LPES real-time projects, we came up with a list of a few
approaches to low-power design for embedded systems using LPE. There are additional benefits of LPES
design. Less heat is generated through LPES, which is better for the environment. For 1000 LPES devices, one
watt of power saved per device equals one KWH i.e. we can save 1 unit of electricity. Design with low power
increases the component and system reliability. The embedded system's operating life is enhanced. In many
instances, LPES designs may result in a reduction in production costs. The LPE components chosen are more
affordable and inexpensive. Hence, the low-wattage power supply, LPES design is easier and less expensive.

Key-Words: - low power embedded system, low power design, low power PCB, low power electronic
components, power management, battery management, algorithm optimization.

Received: April 21, 2022. Revised: August 18, 2023. Accepted: October 15, 2023. Published: November 20, 2023.

1 Introduction 1.2 Calculate the Electricity Usage

The LPES Design is on the rise. An embedded The LPES design should be represented in a block
system's low power consumption is crucial for diagram. We can identify the key components and
building a battery-powered device. There isn't a their power requirements using this block diagram.
single guideline that applies to all types of use Datasheets and application notes include
scenarios. System design, circuit design, firmware information about device power consumption.
design, and trade-offs are all mixed together in this The LPES design engineer will be able to
situation to develop LPES, [1], [2], [3], [4], [5], [6]. develop the best power-saving approach to meet the
We discuss a few design guidelines for LPES using goal with the aid of the power budget and predicted
LPE. These guidelines will be very helpful for power consumption based on high-level LPES
designing LPES. Initially, there are two things to design, [10], [11], [12], [13]. This will also assist the
undertake before starting the design work on the design engineer in determining if the supplied
LPES, [7], [8], [9]. battery capacity is adequate or not (early in the
design process). Always take into account the
1.1 Be Aware of the Electricity Budget battery's self-discharge and practical capacity when
Know your LPES design's entire power budget. For utilizing the battery instead of the capacity shown
instance, it should not draw more than 500 mA. It on the datasheet. There are numerous strategies to
should be well-known how long of a backup period save power, but not all of them may be appropriate
is needed if it is battery-powered. for all use cases.

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DOI: 10.37394/232017.2023.14.8 Yashu Swami

2 LPES Design Requirements power supply since it is the most essential predictor
Gathering requirements of LPES is the initial step in of usability. Is our LPES battery-powered or do we
every effective project design execution. We must need a wall outlet? How long will it run on battery
create criteria around our need for power efficiency. power before needing to be recharged? When
Prolonging battery life, guaranteeing overall power choosing hardware, this ought to be the initial place
efficiency and design reliability are likely to be our to look. Some designers prefer to work in the
high goals, [14], [15], [16], [17], [18], [19]. We opposite direction. It is critical to select processing
need to make decisions on a few of the following power and memory (RAM and Flash) to ensure that
things to achieve our goals: the LPES program can operate with the lowest
• How long can our battery-operated system be computation time. This will further restrict your
deployed before it has to be recharged? system's power requirements, but it may impair
• How much computing power does our system functionality. The LPES mobile gadget to be created
require to function properly? may not be mobile since it requires regular
• What power management strategies or features are recharging, a huge battery, or continual wall power.
supported by our electronic components? Our next LPES, the LP-PCB design for an IoT
• Are there any high-power consumption circuit device will almost certainly have many DC-DC
blocks or power-hungry peripherals that need converters. The upstream regulator must be directly
intermittent power? connected to our power source and can be utilized to
We can devise a plan to create a successful control DC-DC converters. These IoT converters
LPES design if we know the answers to these typically operate at the order of hundreds of kHz to
questions. Selecting crucial parts and peripherals a few MHz. They can be an issue for both radiated
that might need to be combined with a power and conducted EMI. The LP-PCB stack-up design is
management algorithm is the first step in the design critical for shielding and reducing radiated
process. We may decide how to best apply a power emissions. It prevents switching noise from
management plan at the system level once we've interfering with downstream components. And
selected the crucial LPE components. validate that the electrical component is in the
The current trend in emerging IoT devices is to correct location.
incorporate more features into a smaller form factor, LPES active devices (MCUs, FPGAs,
while also increasing computing power, wireless SoCs/SoMs, and any other IC that processes or
connection protocols, and processing manipulates data) should be selected such that they
speed/memory. More engineers are becoming only give the necessary processing capabilities
specialists in High-Density Interconnect (HDI) while consuming the least amount of power. Several
design, low-EMI stack-up design, RF layout and MCUs that provide processing power for data-
routing, and other formerly complex areas of PCB intensive applications, as well as other SoCs for
design as a result of this trend. Several design teams signal processing and other functions, have a sleep
are also being driven to become acquainted with mode. When a component enters sleep mode, it
LPES software packages, operating systems, UI/UX effectively halts and uses the least amount of power
design, and algorithm design as a result of this. while waiting for a wake-up notification.
Whatever capabilities your next IoT device has, Once we've determined the size of our battery,
it must be built with low power consumption, maximum power consumption, and needed supply
reliable power management with near zero power voltages in various components, we must choose
fluctuations, low conducted and radiated EMI, and components that deliver steady power as the device
lots of sensors/HMI to communicate with the real functions. Steady power is a key aspect of power
world. Arguably, the most important of these integrity in LPES, while it is closely tied to EMI
aspects is Low Power-PCB (LP-PCB) design; if the issues both within and outside the device, as well as
device can’t operate for more than an hour, then it signal integrity. Addressing all of these problems at
will never last in the market. once necessitates making the proper PCB design
choices. This comprises LP-PCB stack-up design,
power delivery block network design, and routing
and layout isolation. The LP-PCB stack-up design,
3 LP-PCB Design for LPES layout, and routing are explored below.
LP-PCB design entails more than just selecting
electronic components with low power
consumption, however, this is a significant design
consideration. Our design should begin with the

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DOI: 10.37394/232017.2023.14.8 Yashu Swami

3.1 LP-PCB Stack-up Design Selection for planes and signal layers. The nearby ground planes
LPES will offer a short return route with a low loop
The LP-PCB stack-up will play a significant role in inductance, providing shielding and aiding in the
LPES power integrity and isolation in designs. A reduction of ringing.
minimum of six layers will be used in advanced LP- Another thing to think about is routing between
PCB design for LPES IoT devices. PLDs with a LP-PCB layers, particularly as the board's
high pin count on densely packed boards can easily component and trace density grows. HDI design
span several dozen layers. To meet our form factor techniques gain appeal as more devices achieve
needs, we may employ a flex or rigid-flex board for higher densities. Traces themselves don't alter much
LPES. For example, the latest iPhone employs over in terms of design, but fanout techniques for high
two dozen flex boards to make place for a bigger pin-count components and via design do. The two
battery. main choices when creating a fanout plan are
The main problem in developing LP-PCB stack- dogbone fanout and via-in-pad. Figure 2 below
up is giving an area for stripline routing and placing depicts three potential variations for fanout/escape
our power and ground planes on nearby levels, routing.
regardless of how many layers we include in the
board.

Fig. 2: Approaches for HDI fanout for high-density

BGAs in LP-PCB design for LPES.

3.2 LP-PCB Design and EMI/EMC

Only through the filtration process, we can
effectively fight conducted EMI from switching
noise in LPES PCB designs. Switching noise on a
regulator circuit is significantly decreased by the
output capacitance. However, switching regulators
also generate radiated EMI, which can cause a
nearby device to experience a significant voltage
change. Switching regulators/converters that
Fig. 1: Sample of 10-layer firm stack-up generate a few Amps of current can cause a
guaranteeing the power integrity in IoT/mobile neighboring circuit to generate a few Volts of noise.
device LP-PCB design for LPES. Where a switching regulator induces voltage, vias,
and circuits with high loop inductance can pose
Figure 1 depicts one of the LP-PCB stack-up challenges.
designs for LPES. It is beneficial for a variety of The LPES power converter circuitry should be
factors. The neighboring power and ground planes positioned farthest away from the most delicate
will have a sizable interplane capacitance even on a circuits, antenna components, analog circuitry, and
typical 1.57 mm board. It aids in lowering the power any other digital signals that operate at a low level
delivery block network of the LPES design's overall (less than 3.3 V). This will make sure that any
comparable impedance. We should have a very emitted EMI that does get to these components,
stable power distribution in this board with causes less noise to be produced. Where to position
negligibly low ringing once a few decoupling the output inductor and input/output capacitance for
capacitors are added for key components. We might converter ICs is another thing to think about. These
prefer working with a greater layer count on a shouldn't be routed through vias and should be
thinner board if we are working at lower signal positioned as near to the converters as feasible. The
levels. This will increase interplane capacitance and input/output capacitors are an important caveat. To
bring the power and ground planes closer together. minimize loop inductance, the ground pin on these
Second, stripline routing is possible in inner layers capacitors needs to be routed through a via and back
thanks to the arrangement of alternating ground to the neighboring ground.

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To reduce radiated EMI between the power 4.1 Begin with Necessities
section and antennas, analog circuits, and any other A certain processor or peripheral might be one of
components that operate with low supply voltage, the critical essential components. Find the lowest
we should consider using some shielding methods in power alternative that meets the essential functional
severe LPES PCB design situations when dealing criteria of that component.
with an IoT/mobile device that provides high
current. Can shielding be one solution? The power 4.2 Peripheral Architecture
control portion of the LPES PCB can readily be Consider the interactions between peripheral blocks,
housed in grounded shielding cans. Figure 3 shows the host processor, and the environment. Incorporate
the shielding for mobile and IoT devices that this knowledge to design your LPES architecture.
maintain power and transmission fidelity. The other
choice is to use ground pour and via barriers to 4.3 Interfaces and Receivers
separate various functional blocks; this approach I2C, SPI, GPIO, and other low-speed digital
may be most effective with miniature form factor protocols can all have various power outputs. To use
flex/rigid-flex boards. Typically, they are made to less power overall in LPES, receivers and converters
produce an image charge at a particular frequency. like ADCs may be made to operate at a lower
Ground pour, on the other hand, will offer sample rate.
broadband shielding and separation but attenuation.
Verifying isolation methods and ensuring that any 4.4 Devices with Sleep/Hibernate Modes
induced noise does not surpass noise margins in In LPES, some critical CPUs and other low-power
circuits will require the use of some LPES PCB IC blocks include sleep modes. The current is only
design post-layout simulation tools. delivered to important functional blocks. In these
modes, the current can fall considerably below 0.01
mA to reduce power consumption and leakage.

4.5 Power Control

After choosing each essential LPE component, it's
time to consider power regulation. Opt for the
power regulation method with the maximum
possible efficiency. Power conversion efficiency
may be maintained at levels much above 95% by
carefully designing the regulatory phases of LPES.

5 Power Management Techniques

By selecting the proper components of LPES,
Fig. 3: IoT/mobile device shielding to safeguard component-level power usage is simple to handle.
the power/signal integrity. However, there are circumstances in which a
specialized high-power component is a must in our
system. The system should now be built with battery
4 LPES Component Selection charge management, algorithm optimization, and
The power consumption is greatly influenced by the the ability to toggle on and off specific peripherals.
LPES components like the primary CPU, analog
front-end, and peripherals like monitors, and 5.1 Peripherals
displays. Numerous processor units (MCUs, One method for ensuring that power is only utilized
FPGAs, MPUs, etc.) and other components are when it is required is for the host controller to
expressly advertised as low-power devices, and they switch peripherals on and off as needed. When a
can make it possible for LPES to employ a novel component is not actively processing data, it may
power management strategy. Here are some accomplish this on-chip, turning off groups of
guidelines we may use to design LPES power interfaces and lowering the core voltage. Figure 4
system architecture when choosing components. represents the block diagram view of power to
peripherals managed by switching with a bus
topology. Note that this might require digital/analog
switch components. Many inexpensive MCUs of

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LPES have this functionality, which is very popular. power if background activities and services are
However, there could be system blocks that are not removed, along with any unneeded computing
directly linked to the master processor at the system operations.
level. Simply shutting off power to the peripheral
block or placing a slave CPU in sleep mode might
turn them off. 6 Conclusion
In this paper, we presented some of the recent
research work being carried out in the field of Low
Power Embedded Systems (LPES). We present the
basic design guidelines for LPES using Low Power
Electronics (LPE). It covers practical techniques on
key low power issues such as design requirements,
PCB selection, LPE components and I/O
considerations, sleep/wake-up issues, power
management, and general design issues. There are
several strategies to save power, but not all of them
are appropriate for every application. However, the
designers would be able to reduce the real power for
LPES in most of the defined cases. He will be able
to develop a successful LPES following the
Fig. 4: Power to peripherals can be managed by described design guidelines of LPE. He must
switching with a bus topology. Note that this might employ power management strategies, make wise
require digital/analog switch components. selections when selecting LPES components, and
follow crucial design guidelines while designing
5.2 Battery Management LP-PCBs.
Not all battery packs will support this tactic,
however, it is beneficial for multi-cell battery packs
connected in series. Implementing a battery References:
management algorithm with a balancing mechanism [1] Guo, Hui, A Structural Customization
is one technique to ensure the charge is spread Approach for Low Power Embedded Systems
equally across cells and avoid excessive power from Design, 2010 IEEE/ACM International
being extracted from a single cell. The Texas Conference on Green Computing and
Instruments BQ769x0 series is one potential Communications.
component for putting a standard balancing [2] Swami, Yashu, and Sanjeev Rai, Comparative
algorithm into practice for LPES design. A methodical assessment of established
microcontroller, FPGA, CPU, or MPU may balance MOSFET threshold voltage extraction
low current across cells with little power loss in this methods at 10-nm technology node, Circuits
LPES design strategy. and Systems 7.13 (2016): 4248.
[3] Zhou, Yu and Guo Hui, Application Specific
5.3 Algorithm Optimization Low Power ALU Design, 2008 IEEE/IFIP
Designers of LPES should make sure that any International Conference on Embedded and
specialized algorithms in their firmware are Ubiquitous Computing.
optimized to reduce computation operations. [4] Swami Y, Rai S, Modeling, simulation, and
Enterprise-level software developers frequently analysis of novel threshold voltage definition
have to take into account how many logical for nano-MOSFET, Journal of
operations are required to execute an algorithm and Nanotechnology. 2017 Jan 1; 2017.
must look for ways to reduce the number of [5] Asaduzzaman, N. Limbachiya, I. Mahgoub, F.
operations required to accomplish a computational Sibai, Evaluation of ICache Locking
activity. Technique for Real-Time Embedded Systems,
The same is required of LPES firmware and Proc. IEEE Int. Conf. on Innovations in Info.
software developers for their respective systems. Technology (IIT'07), 2007.
Lowering the algorithm complexity reduces the host [6] Swami, Yashu, and Sanjeev Rai, Modeling
processor's power requirements. The CPU will run and analysis of sub-surface leakage current in
fewer tasks for the operation. Hence, it uses less nano-MOSFET under cutoff regime,

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Superlattices and Microstructures 102 (2017): [17] Kumar, Amrish, Yashu Swami, and Sanjeev
259-272. Rai, Modeling of surface potential and fringe
[7] Jong Wook Kwak; Ju Hee Choi; Selective capacitance of selective buried oxide
Access to Filter Cache for Low-Power junctionless transistor, Silicon 13.2 (2021):
Embedded Systems, 43rd Hawaii 389-397.
International Conference on System Sciences [18] Swami, Yashu, and Sanjeev Rai, Physical
(HICSS), pp. 1-8, 2010. Parameter Variation Analysis on the
[8] Swami, Yashu, and Sanjeev Rai, Proposing an Performance Characteristics of Nano DG-
enhanced approach of threshold voltage MOSFETs, Circuits and Systems 12.4 (2021):
extraction for nano MOSFET, 2017 IEEE 39-53.
Asia Pacific Conference on Postgraduate [19] G. Eason, B. Noble, and I. N. Sneddon, On
Research in Microelectronics and Electronics certain integrals of Lipschitz-Hankel type
(PrimeAsia). IEEE, 2017. involving products of Bessel functions, Phil.
[9] M. Alipour, M. E. Salehi and K. Moshari, Trans. Roy. Soc. London, vol. A247, pp. 529–
Cache Power and Performance Tradeoffs for 551, April 1955.
Embedded Applications, 11 International
Conference on Computer Applications and
Industrial Electronics (ICCAIE 2011), DOI: Contribution of Individual Authors to the
10.1109/ICCAIE.2011.6162098 Creation of a Scientific Article (Ghostwriting
[10] Swami, Yashu, and Sanjeev Rai, Modeling Policy)
and characterization of inconsistent behavior The author contributed in the present research, at all
of gate leakage current with threshold voltage stages from the formulation of the problem to the
for Nano MOSFETs, American Journal of final findings and solution.
Modern Physics 7.4 (2018): 166-172.
[11] Asaduzzaman, F.N.Sibai, Investigating Cache Sources of Funding for Research Presented in a
Parameters and Locking in Predictable and Scientific Article or Scientific Article Itself
Low Power Embedded Systems, 22nd No funding was received for conducting this study.
International Conference on Microelectronics.
[12] Swami, Yashu, and Sanjeev Rai, A novel SCE Conflict of Interest
independent threshold voltage hybrid The author has no conflict of interest to declare.
extrapolation extraction method for nano
MOSFETs, 2017 International Conference on Creative Commons Attribution License 4.0
Energy, Communication, Data Analytics and (Attribution 4.0 International, CC BY 4.0)
Soft Computing (ICECDS). IEEE, 2017. This article is published under the terms of the
[13] T.S. Rajesh Kumar, C.P. Ravikumar, R. Creative Commons Attribution License 4.0
Govindarajan, Memory Architecture https://creativecommons.org/licenses/by/4.0/deed.en
Exploration Framework for Cache Based _US
Embedded SoC, 21st International Conference
on VLSI Design.
[14] Swami, Yashu, and Sanjeev Rai,
Comprehending and Analyzing the Quasi-
Ballistic Transport in Ultra Slim Nano-
MOSFET through Conventional Scattering
Model, Journal of Nanoelectronics and
Optoelectronics 14.1 (2019): 80-91.
[15] Ji Gu, Hui Guo and Patrick Li, ROBTIC: An
On-Chip Instruction Cache Design for Low
Power Embedded Systems, 2009 15th IEEE
International Conference on Embedded and
Real-Time Computing Systems and
Applications.
[16] Swami, Yashu, and Sanjeev Rai, Ultra-thin
high-K dielectric profile based NBTI compact
model for nanoscale bulk MOSFET, Silicon
11.3 (2019): 1661-1671.

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