Low-Power & Low-Voltage

Analog Integrated Circuits

Carlos Galup-Montoro, Márcio Cherem Schneider

[Link]

Universidade Federal de Santa Catarina

EMICROPB LP-LV Analog ICs 1

 Acknowledgments

Ana Isabela A. Cunha

Universidade Federal da Bahia

EMICROPB LP-LV Analog ICs 2

Contents
1. Why low-power & low-voltage
2. Fundamental limitations in analog integrated
circuits
3. Components of the CMOS technology
4. MOSFET modeling
5. The basic gain stage
6. The current mirror
7. A self-biased current source
EMICROPB LP-LV Analog ICs 3
Contents
1. Why low-power & low-voltage
2. Fundamental limitations in analog integrated
circuits
3. Components of the CMOS technology
4. MOSFET modeling
5. The basic gain stage
6. The current mirror
7. A self-biased current source
EMICROPB LP-LV Analog ICs 4
1.1. The Microelectronics Revolution

The invention of the transistor (1947)

Source: Wikipedia

EMICROPB LP-LV Analog ICs 5

1.1. The Microelectronics Revolution

Jack Kilby’s integrated circuit

The invention of the
integrated circuit (1958-
1959)

Source: Wikipedia Source: R. Jaeger, Microelectronic

Circuit Design, McGraw-Hill, 1997

Jack Kilby (Texas Instruments) – 1958

Robert Noyce (Fairchild Semiconductor) - 1959
EMICROPB LP-LV Analog ICs 6
1.1. The Microelectronics Revolution
Transistors (3)
The first commercial IC:
3-input NOR gate – RTL
Fairchild (1961)

Connection metal

Resistors (4)

~ 1 mm
EMICROPB LP-LV Analog ICs 7
1.1. The Microelectronics Revolution

Moore’s law
The number of transistors on
integrated circuits doubles every
two years

EMICROPB LP-LV Analog ICs 8

1.1. The Microelectronics Revolution

Source: Intel

EMICROPB LP-LV Analog ICs 9

1.1. The Microelectronics Revolution

Moore’s law slope

Source: Intel

Source: Intel

EMICROPB LP-LV Analog ICs 10

1.1. The Microelectronics Revolution

EMICROPB LP-LV Analog ICs Source: Intel 11

1.2. Low Power Microelectronics
The early electronic computers
ENIAC (1946)

17.468 vacuum tubes

7.200 diodes
1.500 relays
70.000 resistors
10.000 capacitors
Weight: 27 ton
Dimensions: 2.6 m×0.9 m×
26 m (60 m3)
Power: 150 kW

Source: Wikipedia

EMICROPB LP-LV Analog ICs 12

1.2. Low Power Microelectronics

Historically demanding applications of LP microelectronics

(long-life autonomous portable equipment): wrist
watches, hearing aids, implantable cardiac pacemakers, pocket
calculators, pagers. Until the early 90’s, power was not an issue
for most of the ICs.

Behind-the-ear hearing Artificial pacemaker with

aid – Amplivox The first implantable electrode for
pacemaker transvenous insertion.
Source: Wikipedia

EMICROPB LP-LV Analog ICs 13

1.2. Low Power Microelectronics

Source: Rabaey

EMICROPB LP-LV Analog ICs 14

1.2. Low Power Microelectronics

Source: Rabaey

EMICROPB LP-LV Analog ICs 15

1.2. Low Power Microelectronics

(OPS)

Source: Rabaey

EMICROPB LP-LV Analog ICs 16

 1.2. Low Power Microelectronics

11.3 mm

26.7 mm

X. Chen et al, IEEE Trans. Biomedical Circ. And

Syst., vol. 3, no. 1, Feb 2009

EMICROPB LP-LV Analog ICs 17

[Link] low-power & low-voltage
J. Rabaey, Low Power Design Essentials, Springer, 2009.
C. Piguet (ed.), Low-Power Electronics Design, CRC Press, 2005
J. D. Meindl, “Low Power Microelectronics: Retrospect and Prospect,” Proc. of the
IEEE, vol.83, no.4, pp. 619-635, Apr. 1995.
J. Rabaey, A. Chandrakasan, and B. Nikolic, Digital Integrated Circuits – A
Design Perspective, Prentice-Hall, 2003.

EMICROPB LP-LV Analog ICs 18

Contents
1. Why low-power & low-voltage
2. Fundamental limitations in analog integrated
circuits
3. Components of the CMOS technology
4. MOSFET modeling
5. The basic gain stage
6. The current mirror
7. A self-biased current source
EMICROPB LP-LV Analog ICs 19
2.1 Design specifications

Digital Design:

Time Delay or
Frequency, Power, Energy/operation, Reliability, Rob
ustness, Cost

Analog Design:

Noise, Linearity, Bandwidth (Frequency), Power,

Supply Voltage, Gain, Accuracy, Robustness,
Cost

EMICROPB LP-LV Analog ICs 20

2.2 Noise and Distortion

Thermal noise:
Energy equipartition principle: In thermal equilibrium the mean thermal
energy per degree of freedom is (1/2)kT, where k is the Boltzmann
constant and T is the absolute temperature.

Cvo2,n kT kT
Vo
Noise energy in C= = ⇒ vo2,n =
2 2 C
Dissipative
element C Assume that Vo, s = VP sin ωt
Cvo2, s CVP2
Signal energy in C= =
2 4
VP2 / 2
The signal-to-noise ratio is S / N =
kT / C

EMICROPB LP-LV Analog ICs 21

2.2 Noise and Distortion
Thermal noise :

1 R
G= i 2
R +
_
v2

i2 v2
= 4kTG = 4kTR
∆f ∆f
Norton and Thevenin equivalent Source: Motchenbacher
circuits of a real (noisy) resistor

EMICROPB LP-LV Analog ICs 22

2.2 Noise and Distortion

kT/C noise

Vin Vo 1
Vo = H ( jω ) =
R Vin 1 + jω RC
C

2 2
Von von 2 v
= H ( jω ) = H ( jω )
_
+

Von V ∆f ∆f
v 2 R
C ∞
1 d ω kT
2
von =∫ 2
4kTR =
0 1 + ( ω RC )
2π C

As stated by thermodynamics (energy equipartition

principle).

EMICROPB LP-LV Analog ICs 23

2.2 Noise and Distortion

Power vs. signal-to-noise ratio

+VDD
ID2
M2 io= ID2+ ID1
ID2
io
vo VB VP
vi
ID1 ID1
+
- vi M1
“Idealized” class-B
-VDD transconductor

AV= gm/go
vg vo -20 dB/dec
+ gmvi go C
vi
0 ωu
2 ωb ω(log)
channel in
= 4γ kTg m
noise ∆f

EMICROPB LP-LV Analog ICs 24

2.2 Noise and Distortion

Power vs. signal-to-noise ratio

kT g m
+VDD Output noise voltage vo2,n = γ (i)
C go
M2 VP2 (ii) vo = VP sin ωt
ID2
Output signal voltage vo2, s =
io 2
vo Power delivered by VBVP
ID1 P= go (iii)
+ the supplies is π
- vi M1
VB g m
-VDD From (i) – (iii): P = 4γ ( kT ⋅ ∆f ⋅ S / N )
VP g o
go
with ∆f =
2π C

EMICROPB LP-LV Analog ICs 25

2.2 Noise and Distortion

Distortion – The output signal is limited by the maximum

acceptable nonlinearity. In the previous case, VP/VB<0.5

Dynamic range: Usually defined as the (S/N)max, with the

maximum signal defined as that for which the distortion is
acceptable.

EMICROPB LP-LV Analog ICs 26

2.3 Parasitic capacitors

Power consumption increases due to parasitic

capacitors:

More transconductance (and current) is needed

for keeping the speed;

Phase shift introduced by parasitic capacitances

may require compensation capacitance (and more
current to reach the gain-bandwidth product)

EMICROPB LP-LV Analog ICs 27

2.4 Mismatch & 1/f Noise

Both mismatch and 1/f noise are ~ proportional to

the inverse of the gate area.

If both mismatch (to improve dc accuracy) and 1/f

noise (to improve S/N ratio) are reduced through an
area increase, parasitic capacitances also
increase, giving rise to increased current
consumption to reach the required speed.

& Charge Injection for switched-capacitor circuits

EMICROPB LP-LV Analog ICs 28

2. Fundamental limitations in analog integrated circuits

E. Sánchez-Sinencio and A. G. Andreou (eds.), Low-Voltage/ Low Power Integrated

Circuits and Systems, IEEE Press, New York, 1999.
J. D. Meindl, “Low Power Microelectronics: Retrospect and Prospect,” Proc. of the
IEEE, vol.83, no.4, pp. 619-635, Apr. 1995.
SSCS News, Summer 2008, vol. 13, no. 3 (Issue on the work and impact of Prof. Eric
Vittoz).
C. Toumazou, G. Moschytz, and B. Gilbert (eds.), Trade-offs in Analog Circuit Design –
The Designer’s Companion, Kluwer, 2002 (see the excellent Chapter 10, by E. A.
Vittoz and Y. P. Tsividis).
R. Cavin and W. Liu, Emerging Technologies – Designing Low Power Digital
Systems, Tutorial for 1996 ISCAS, (see Chapter 1.2, by C. C. Enz and E. A. Vittoz).
[Link] (courses on Low-power & Low-voltage)

EMICROPB LP-LV Analog ICs 29

Contents
1. Why low-power & low-voltage
2. Fundamental limitations in analog integrated
circuits
3. Components of the CMOS technology
4. MOSFET modeling
5. The basic gain stage
6. The current mirror
7. A self-biased current source
EMICROPB LP-LV Analog ICs 30
3.1. Resistors

L L 1  L
R=ρ =   = RSH
hW W  hq µ n  W
W
TCR = ( d ρ / ρ ) / dT T =T
h L a

VCR = ( d ρ / ρ ) / dV V =V
ref

Resistor type Ω /sq)

RSH (Ω TCR (ppm/oC) VCR (ppm/V)
n+ Polysilicon 100 -800 50
p+ Polysilicon 200 200 50
n+/ p+ Polysilicon (silicided) 5
n+ Diffusion 50 1500 500
p+ Diffusion 100 1500 500
n-Well 1000 2500 10000

EMICROPB LP-LV Analog ICs 31

 3.1. Resistors

W
R R/2 R/2
h L

C/2 C/2 C/4 C/2 C/4

Substrate Substrate

Single-π and double-π equivalent circuits for a polysilicon resistor

EMICROPB LP-LV Analog ICs 32

3.1. Resistors
The MOSFET as a voltage-controlled resistor R=R(VG)

VD=VQ+Vin µA)
25 ID (µ VG =4.5 V

slope=1/R
ID 3V
IF

VG VQ
0
0 1 2 3 4 5
VD (V)
Vin
VS=VQ
-25

EMICROPB LP-LV Analog ICs 33

3.2. Capacitors
Top c Top plate Desired
plate parasitic capacitor
capacitor
c d

d
Substrate Bottom plate
(or well) parasitic
Bottom
capacitor
plate

(a) (b)
Integrated parallel plate capacitor (a) Simplified structure; (b) equivalent circuit.

Warning: The integrated capacitor is an RC line

EMICROPB LP-LV Analog ICs 34

3.2. Capacitors

Not available in conventional CMOS

(a) Poly-semiconductor and (b) poly-poly capacitors

EMICROPB LP-LV Analog ICs 35

3.2. Capacitors

Gate capacitors in a p-well CMOS technology

EMICROPB LP-LV Analog ICs 36

3.2. Capacitors

experiment

theory

Capacitor in n-well CMOS technology and its corresponding gate

capacitance for VBS=0.
EMICROPB LP-LV Analog ICs 37
3.3. Inductors
Either bond wires or
planar spirals
(a) Cross section, (b) top view
and (c) lumped model of a
planar spiral inductor

(c)

EMICROPB LP-LV Analog ICs 38

 3.4. Bipolar Transistors

Cross section of bipolar lateral

and vertical (substrate) devices
in CMOS technology

CMOS-compatible P. R. Gray, P. Hurst, S. H. Lewis, and R. G. Meyer, Analysis and Design of Analog Integrated
Circuits, 4th. Edn., Wiley, New York, 2001.
bipolar transistors E. A. Vittoz, Micropower Techniques, Chapter 3 in Design of Analog-Digital VLSI Circuits for
Telecommunications and Signal Processing, J. E. Franca and Y. Tsividis (eds.), Prentice-Hall, 1994

EMICROPB LP-LV Analog ICs 39

3.4. Bipolar Transistors

AMS 0.35 um CMOS

technology

βL=IC/IB

βV=IS/IB

EMICROPB LP-LV Analog ICs 40

Contents
1. Why low-power & low-voltage
2. Fundamental limitations in analog integrated
circuits
3. Components of the CMOS technology
4. MOSFET modeling
5. The basic gain stage
6. The current mirror
7. A self-biased current source
EMICROPB LP-LV Analog ICs 41
4.1 The two-terminal MOS structure
 4.1 The two-terminal MOS structure
VG gate-to-bulk voltage

G ′
Cox oxide capacitance per unit area
QG
+ + + + + + + + +
φs surface potential
QI
+
VG - -- - ---Q - -- -
B
QI′ inversion charge per unit area
φs -
- - - - - -
_ -
- - - - QB′ bulk charge per unit area

B VFB flat-band potential

′ (VG −VFB −φs ) = −(QI′ + QB′ )

QG′ = Cox
EMICROPB LP-LV Analog ICs 43
4.2 MOS capacitor voltage balance

G potential VGB
QG
+ + + + + + + + + + +
Qo +
+ + + +
VGB
φox

depth
QC Semiconductor
Flatband charge/area
voltage
NA (acceptors/cm3) φs
Q′c
VGB − VFB =− + φs
B C′ox
Surface
φMS potential
Oxide capacitance/area
EMICROPB LP-LV Analog ICs 44
4.3 Operation regimes
Accumulation
VGB < VFB
G Q′C > 0
QG φs < 0
- - - - - - - - - - -

++++++++++++++
VGB QC
Holes +
accumulate in the P
semiconductor
NA (acceptors/cm3) surface
B
EMICROPB LP-LV Analog ICs 45
4.3 Operation regimes
Depletion VGB > VFB
Q′C < 0
G
0 < φ s < φF
QG
+ + + + + + + + +
Holes evacuate from the P
semiconductor surface and
VGB
- -- - - -Q - -- -
C
acceptor ion charges -
- - - - become uncovered

φF = Fermi potential ≅ φ[Link](NA/ni)

NA = acceptor concentration
B ni = intrinsic concentration
φt = thermal voltage = KT/q
EMICROPB LP-LV Analog ICs 46
4.3 Operation regimes
VGB > VFB
Inversion electrons approach
Q′C < 0
the surface!
φ s > φF
G
QG
+ + + + + + + + +

VGB
- -- - ---Q - -- -
C
-- -- - - - - -
- - -
B
EMICROPB LP-LV Analog ICs 47
4.4 MOS capacitor small-signal equivalent circuit

dQG′ 1
′ =
C gb ′ =
C gb
dVG 1 1 Cc′ = Cb′ + Ci′
+
Cc′ Cox′
dQI′ QI′
Ci′ = − ≅−
dφs φt
kT thermal voltage
φt =
q (26 mV @ 300K)

γ Cox′
Cb′ ≅
2 φs − φt
γ body-effect coefficient
4.5 The linearization surface potential
Determination of φsa = φs Q′ =0 VG
I
QI′ = 0 Cox′
+ _
φs = φsa
Ci′ = 0 _
Potential balance Cb′ QB′
+
VG − VFB = φsa + sgn(φsa )γ φsa + φt e−φsa ( φt
−1 )

dVG Cb′ γ (1 − e−φsa / φt

)
= n = 1+ = 1+
dφsa Cox′ 2sgn (φ ) t ( )
−φ φt
sa φsa + φ e sa
−1

EMICROPB LP-LV Analog ICs 49

4.6 The three-terminal MOS structure
VG
VC
Carrier concentrations in Si
φS substrate follow Boltzmann’s
n+ p law:
n, p ∝ exp(-Energy/kT)

φ-VC)/φ
n =noexp[(φ φt]

inversion no =ni2/NA
charge gate
charge

bulk
charge

EMICROPB LP-LV Analog ICs 50

4.6 Small-signal equivalent capacitive circuit

gate
charge

inversion
charge
bulk
charge

Compact MOSFET models

∂QI′
′
Ci = − Inversion capacitance/area are essentially based on how
∂φ s V the nonlinear capacitances
C

Cb′ & Ci′

∂QB′ Bulk capacitance/area
Cb′ = − are approximated in terms
∂φ s VC of voltages
EMICROPB LP-LV Analog ICs 51
4.7 The pinch-off charge density
The channel charge density corresponding to the effective
channel capacitance times the thermal voltage, or thermal
charge, defines pinch-off

′ = −(Cox′ + Cb′ )φt = −nCox′ φt

QIP

The name pinch-off is retained herein for historical reasons

and means the channel potential corresponding to a small (but
well-defined) amount of carriers in the channel.

EMICROPB LP-LV Analog ICs 52

4.7 The pinch-off voltage VP
The channel-to-substrate voltage (VC) for which the channel
charge density equals the pinch-off charge density is called the
pinch-off voltage VP.

in weak
−QI′ = Cb′φt e(
φsa − 2φF −VC ) /φt
= Cox′ (n − 1)φt e(
φsa − 2φF −VC ) /φt
inversion

QI′ = QIP
′ = −nCox′ φt VC = VP

  n 
V P = φ sa − 2φ F − φ t 1 + ln  
  n − 1 
VP ≅ φsa − 2φF

EMICROPB LP-LV Analog ICs 53

4.8 The threshold voltage VT0
Equilibrium threshold voltage VT0, for VC=0,
gate voltage for which Q’I = Q’IP = -nC’oxφt
(gate voltage for which VP=0 )

VP ≅ φsa − 2φF
Recalling that
′ φsa − φt
VG − VFB = φsa + γ Cox

it follows that VT 0 ≅ VFB + 2φF + γ 2φF

EMICROPB LP-LV Analog ICs 54

Pinch-off voltage and slope factor vs gate voltage

4.0
4,00E+00 2
2.0

dVG γ
n= =1+
pinch-off voltage 3.0
3,00E+00

dVP 2 VP +2φF

slope factor
1,5
1.5

2.0
2,00E+00

1
1.0
1.0
1,00E+00

VP
0.5
0,5

0
0,00E+00

-1.0
-1,00E+00 0
0
0,00E+00 1,00E+00 2,00E+00 3,00E+00 4,00E+00 5,00E+00 6,00E+00

0 1.0 2.0 3.0 4.0 5.0

VG (V)
VT0 (equilibrium
threshold voltage) Useful VG −VT 0
approximation: VP ≅
n
EMICROPB LP-LV Analog ICs 55
4.9 Unified charge control model (UCCM) - 1
Basic approximations:
VS VG VD Cox′ + Cb′ = nCox′
n = n(VG )
n+ n+
p dQI′ = nCox′ d φs

≅−
QI′
< 1 WI QI′
d φs Ci′ ′ φt
nCox Ci′ = −
= φt
dVC Ci′ + Cox
′ + Cb′ SI
≅1

 1 φt 
dVC = dQI′  − 
 nCox′ QI′ 

VS ≤ VC ≤ VD
EMICROPB LP-LV Analog ICs 56
4.9 Unified charge control model (UCCM) - 2
 1 φt 
Integrating dVC = dQI′  −  between VC and VP
 nCox′ QI′ 
yields UCCM

′ − QI′
QIP  QI′ 
VP − VC = + φt ln  
′
nCox ′
 QIP 

′ = − nCox′ φt
QIP Thermal (pinch-off) charge
QI′
′
qI = Normalized inversion charge density
−nCox′ φt

Normalized UCCM VP − VC = φt (qI′ − 1 + ln qI′ )

EMICROPB LP-LV Analog ICs 57
Inversion charge density

Strong
inversion
Moderate
inversion

Weak
inversion

EMICROPB LP-LV Analog ICs 58

4.10 The four-terminal MOS structure
The drain current -1 The Pao-Sah equation
VS VG VD
 xi  dV dV
I D = − µ nW  − q ∫ ndx  C = − µ nWQI′ C
 0  dy dy
n+ n+
p W ′
QID dVC
I D = − µn
L ∫′
QIS
QI′
dQI′
dQI′
VG
QI′
Ci′ = − UCCM ′ − QI′
QIP  QI′ 
φt + φt ln   = VP − VC
nCox′ ′
 QIP 
dVC dφ s
+ _ diff. dQI′ (1/ nCox′ − φt / QI′ ) = dVC
dQI′ UCCM

EMICROPB LP-LV Analog ICs 59

4.10 The four-terminal MOS structure
The drain current -2 The Pao-Sah equation & UCCM
VS VG VD
Integrating between
n+ n+
source & drain
p

µ nW  QIS′ 2 − QID
′ 2   QIS
′ + QID
′   QIS
′ − QID′ 
ID =  − φt ( QIS ′ )  = µ nW 
′ − QID ′ φt  
− nCox 
L  ′
2nCox   2  nC ′
ox L 
drift + diffusion average average
charge field

EMICROPB LP-LV Analog ICs 60

4.10 The four-terminal MOS structure
The drain current -3 The charge-sheet model
VS VG VD drift diffusion
d φs dQI′
I D = − µWQI′ + µW φt
n+ n+ dy dy
p
dQI′ = nCox
′ dφs
Integrating between
source & drain

µ nW  QIS′ 2 − QID
′ 2 
ID =  − φt ( QIS ′ )
′ − QID
L  ′
2nCox 

drift + diffusion
EMICROPB LP-LV Analog ICs 61
4.10 The four-terminal MOS structure

The drain current - 4 µW  QIS′ 2 − QID

′ 2 
ID =  − φt ( QIS ′ )
′ − QID
L  ′
2nCox 
W
Aspect ratio S=
L
φt2
Normalization (specific) current I S = µCox′ n S
2

Sheet normalization (specific) current φt2

I SH = µ Cox′ n
2

I D = I F − I R = I S i f − ir  = SI SH i f − ir 

EMICROPB LP-LV Analog ICs 62

4.11The unified current control model (UICM)
I D = I F − I R = I S i f − ir 
VP − VS ( D ) = φt  qIS′ ( D ) − 1 + ln qIS′ ( D )  Normalized
UCCM
QIS′ ( D )
qIS′ ( D ) =
−nCox′ φt

i f ( r ) = q′IS ( D ) 2 + 2q′IS ( D ) ⇒ qIS′ ( D ) = 1 + i f ( r ) − 1

I F (R) φt2 W
i f (r ) = I S = µCox′ n
IS 2 L
Normalized
VP − VS ( D ) = φt  1 + i f ( r ) − 2 + ln
 ( 1 + i f (r ) )
− 1  UICM

EMICROPB LP-LV Analog ICs 63
Review: The four-terminal MOS structure
1. I D = I D (VG , VS , VD ) VG

Voltages referenced to local VS VD

substrate:
B ID
VG→ VGB VS→ VSB VD→ VDB

2. Symmetry B
V1 ID V2
I D (VG , V1 , V2 ) = − I D (VG , V2 , V1 )

VG

EMICROPB LP-LV Analog ICs 64

Review: The four-terminal MOS structure
Normalization
3. For a long-channel MOSFET
W
I D = I F − I R = I S i f − ir  = I SH  f (VG , VS ) − f (VG , VD ) 
L
D
I F ( R ) = I S q′IS ( D ) 2 + 2q′IS ( D ) 
  ID
q′IS ( D ) = QIS′ ( D ) / ( −nCox′ φt )
i f (r ) = I F ( R) / I S
G IF − IR
2
φ W
W B
I S = µ Cox′ n t
= I SH
2 L L
IS and ISH are the normalization (specific)
current and the “sheet” normalization S
current, slightly dependent on bias.
EMICROPB LP-LV Analog ICs 65
 Review: The four-terminal MOS structure
Forward (IF) and Reverse (IR) currents
Long-channel MOSFET I D = I F − I R = I (VG ,VS ) − I (VG ,VD )

(Forward) Saturation
ID = IF − IR ≅ IF IR=
IF=
Triode
ID = IF − IR

Triode for VDS→0

I F ≅ I R ; I D = I F − I R << I F

EMICROPB LP-LV Analog ICs 66

Review: The four-terminal MOS structure
Specific current
The specific (normalization) current φt2 W W
I S = µ Cox′ n = I SH
2 L L
ISH : design parameter
slightly dependent on
VG

ISH ≈25 nA (p-channel)

ISH ≈75 nA (n-channel)
in 0.35 µm CMOS

EMICROPB LP-LV Analog ICs 67

Review: The four-terminal MOS structure
Pinch-off voltage and slope factor
if=3 at pinch-off VP − VS = 0 =  1 + 3 − 2 + ln
 ( )
1+ 3 −1 


VG − VT 0
VP ≅
n

VP[V]

Pinch-off voltage and slope factor as functions of VG. NMOS

transistor W=20 µm, L=2 µm, 0.18 µm CMOS technology.
EMICROPB LP-LV Analog ICs 68
 Experimental results
The I-V Relationship(UICM) VP − VS = φt  1 + i f − 2 + ln ( 1 + i f − 1) 
1,00E-03
10-3 ID (A) VD
VD = VG
ID
1,00E-04
SI

1,00E-05 VS = 0 V

MI 0.5 VS
10-6
1,00E-06 1.0 VG
1.5
1,00E-07
2.0

1,00E-08 WI 2.5 I D = I F − I R = I S i f − ir  ≅

3.0 ISi f since i f >> ir
10-9
1,00E-09
0,00E+00 5,00E-01 1,00E+00 1,50E+00 2,00E+00 2,50E+00 3,00E+00 3,50E+00 4,00E+00 4,50E+00
0 1 2 3 4 VG (V)

Common-source characteristics
EMICROPB LP-LV Analog ICs 69
 Experimental results
The I-V Relationship (UICM) VP − VS = φt  1 + i f − 2 + ln ( 1 + i f − 1) 

VD
10-3
ID (A) VD = VG ID
SI VG = 4.8 V

VG
MI
VS
10-6

0.8 V I D = I F − I R = I S i f − ir  ≅
WI ISi f since i f >> ir
10-9
0 1 2 3 VS (V)
Common-gate characteristics
VG=0.8, 1.2, 1.6, 2.0, 2.4, 3.0, 3.6, 4.2, and 4.8 V
EMICROPB LP-LV Analog ICs 70
4.12 Weak inversion model

Weak inversion VG − VT 0
if(r)<1 n
− VS ( D ) = φt  1 + i f ( r ) − 2 + ln
 ( )
1 + i f (r) −1 

-1
if(r)/2
 VG −VT 0 
 −VS  / φt W
I D = I0 e n  1 − e −VDS / φt
 I0 = µ n ′ φ t2e1 = 2 I S e1
nCox
  L

EMICROPB LP-LV Analog ICs 71

4.13 Strong inversion model - 1

VG − VT 0
n  (
− VS ( D ) = φt  1 + i f ( r ) − 2 + ln 1 + i f ( r ) − 1 
)
Strong inversion
if(r)>>1 VG − VT 0
− VS ( D ) ≅ φt i f ( r ) = φt I F ( R ) I S
n

W  2 2
′
I D = I F − I R ≅ µ nCox

(VG − VT 0 − nVS ) − (VG − VT 0 − nVD ) 
2nL

Moderate inversion
Both sqrt(.) and ln(.) terms are important
1<if(r) <100

EMICROPB LP-LV Analog ICs 72

4.13 Strong inversion model - 2

ID
VDS

VG
ID/IF

VDSsat=VP=(VG-VT0)/n VDS

Output characteristics at VS=0

EMICROPB LP-LV Analog ICs 73
4.13 Strong inversion model - 3

µ Cox′ W
ID ID = (VG − VT 0 ) µ Cox′ W
2n L
ID ID = (VG − VT 0 − nVS )
2n L

SCE, µ, n,
“model”

VT0 VG
VDD (VG − VT 0 ) n VS
ID
VDD
ID

VG VG
VS

EMICROPB LP-LV Analog ICs 74

4.14 Universal output characteristics

VDS  qIS′   1+ i f −1 
′ ′
= qIS − qID + ln   = 1 + i f − 1 + ir + ln  

φt ′
 qID  1 + i − 1
 r 

(a) if= 4.5x 10-2 (VG=0.7 V).

(b) if= 65(VG= 1.2 V).
(c) if= 9.5x102 (VG= 2.0 V).
(d) if= 3.1x 103 (VG= 2.8 V).
(e) if= 6.8x 103 (VG= 3.6 V).
(f) if= 1.2x 104 (VG= 4.4 V).

(o): measured
(—): model

EMICROPB LP-LV Analog ICs 75

4.15 Saturation voltage
Saturation voltage
(VDSsat): VDS at
which the ratio

q′ID q′IS = ξ

VDSsat ≅ φt  1 + i f + 3

Saturation voltage versus inversion level

 1  (1 − ξ )
VDSsat = φt ln   + (1 − ξ )
 ξ 
( )
1+ i f −1 

is the saturation level

EMICROPB LP-LV Analog ICs 76

4.16 Transconductances - 1
∆I D = g mg ∆VG − g ms ∆VS + g md ∆V D + g mb ∆VB
∂I D ∂I ∂I ∂I
g mg = , g ms = − D , g md = D , g mb = D
∂VG ∂VS ∂VD ∂VB
g mg − g ms + g md + g mb = 0

Calculation of gms I D = I F − I R = I S i f − ir 

∂ ( IF − IR ) ∂ IF di f
g ms = − =− = −IS
∂ VS ∂ VS dVS
W 2I S
g ms
L
′
= − µ QIS =
φt
( 1+ i f −1 )
EMICROPB LP-LV Analog ICs 77
 4.16 Transconductances - 2
W 2I S
gmd
L
′
= −µ QID =
φt
( )
1 + ir −1 Only in triode region

∂ (i f − ir )
g mg = I S
∂VG
∂i f ∂i f g ms − g md
=− g mg =
∂VG n∂VS n
UCCM
∂ir ∂ir g ms in saturation
=− g mg =
∂VG n∂VD n

EMICROPB LP-LV Analog ICs 78

4.16 Transconductances - 3
W
g md = − µ ′
QID Only in triode region
L
In saturation, gmd is determined by short-channel effects

ID Saturation
g md ( g ds ) ≅ ; VA ≅ VE L
VA

ID
gm ∆VG

gmd
VA 0V VDS
DSsat

EMICROPB LP-LV Analog ICs 79

4.16 Transconductances - 4

VDD
ID

VG
VS

Source transconductance VG= 0.8, 1.2, 1.6, 2.0, 2.4, 3.0, 3.6, 4.2, and
4.8 V (W=L=25 µm, tox=280 Å)
EMICROPB LP-LV Analog ICs 80
 4.16 Transconductances - 5

VDD
ID

VG VS

Gate transconductance VS= 0, 0.5, 1.0,1.5, 2.0, 2.5, and 3.0 V

W=L=25 µm, tox=280 Å
EMICROPB LP-LV Analog ICs 81
4.17 The transconductance-to-current ratio - 1

g ms ( d )φ t 2 ≅1 WI (if <1)
Transconductance = 2
-to-current ratio I F (R) 1 + i f (r ) + 1 ≅ SI (if >>1)
100
i f (r )
102
gms/IF

W=25 µm
tox = 28 nm (IS = 26 nA)
Seqüência1
101
10
L=25 µm, tox= 280 Å
tox = 5.5 nm (IS = 111 nA)
Seqüência2

L=20 µm, tox= 55 Å

model
Seqüência3

1001
1,00E-04 1,00E-03 1,00E-02 1,00E-01 1,00E+00 1,00E+01 1,00E+02 1,00E+03 1,00E+04
10-4 10-2 100 102 if 104

EMICROPB LP-LV Analog ICs 82

4.17 The transconductance-to-current ratio - 2

Transconductance g ms ( d )φ t 2 ≅1 WI (if <1)

=
-to-current ratio I F (R) 1 + i f (r ) + 1 2
≅ SI (if >>1)
10 2
1,00E+02 i f (r )
gms/IF

V GB = 1.0 V (IS = 33 nA)

Seqüência1

10 1
1,00E+01

VGB = 2.0 V (IS = 26 nA)

Seqüência2

VGB = 3.0 V (IS = 24 nA)

Seqüência3
W=L=25 µm, tox= 280 Å

model
Seqüência4

10 10 0
1,00E+00
-4 10 -2 10 0 10 2 10 4
1,00E-04 1,00E-03 1,00E-02 1,00E-01 1,00E+00 1,00E+01 1,00E+02
if
1,00E+03 1,00E+04

EMICROPB LP-LV Analog ICs 83

4.17 The transconductance-to-current ratio - 3

Transconductance g ms ( d )φ t 2 ≅1 WI (if <1)

=
-to-current ratio I F (R) 1 + i f (r ) + 1 2
≅ SI (if >>1)
101002 i f (r )
gms/IF

L = 25 µm (IS = 26 nA)
Seqüência1
W=25 µm, tox= 280 Å
10 1
10

L = 2.5 µm (IS = 260 nA)

Seqüência2

model
Seqüência3

1001
1,00E-04 1,00E-03 1,00E-02 1,00E-01 1,00E+00 1,00E+01 1,00E+02 1,00E+03 1,00E+04 1,00E+05
10-4 10-2 100 102 if 104
EMICROPB LP-LV Analog ICs 84
4.18 The low-frequency small-signal model
G

g md v d

id
g mb vb
S D

g ms v s

g mg v g
B

EMICROPB LP-LV Analog ICs 85

 4.18 Small-signal MOSFET model
G
dvDB
gmd vDB + Csd
dt

Cgs dvGB Cgd

gmgvGB − Cm
dt
S D Cgb
dvSB
gmsvSB + Cds Cbd
Cbs dt

B
Cdg − C gd = Cm = (Csd − Cds ) / n
EMICROPB LP-LV Analog ICs 86
 4.18 Intrinsic capacitances

′
Cox = WLCox
n −1
C gb =
n
( Cox − C gs − C gd )
2 1 + 2α q ′IS
C gs = C ox 2
3 (1 + α ) 1 + q ′IS

2 α 2
+ 2α q ′ID
C gd = C ox
3 (1+α ) 2 1 + q′ID
Cbs = ( n − 1)C gs
Cbd = ( n − 1)C gd
VDS= 1 V

Cbg = C gb

4 α + 3α 2 + α 3 q′ID
Csd = − nCox 4 1 + 3α + α 2 q′IS Cdg − C gd = Cm = (Csd − Cds ) / n
15 (1+α )3 1 + q′ID Cds = − nCox
15 (1+α )3 1 + q′IS
1 + q′ID
α= Channel linearity factor
EMICROPB 1 + q′IS LP-LV Analog ICs 87
4.19 Noise & Mismatch

 Predicting accuracy (mismatch & noise) is

fundamental in analog and digital IC design
 Besides DC and AC models, system
designers need information on accuracy ⇒
proper matching and noise models are
required.
 Simple one-equation models provide a useful
tool for hand design also, rather than being
restricted to computer simulation.

EMICROPB LP-LV Analog ICs 88

4.19 Noise & Mismatch
 The spontaneous fluctuations over time of the current
and voltage inside a device, which are basically related
to the discrete nature of electrical charge, are called
electrical noise.
 Time-independent variations between identically
designed devices in an integrated circuit due to the
spatial fluctuations in the technological parameters
and geometries are called mismatch.
 Mismatch (spatial fluctuation) and noise (temporal
fluctuation) are similar phenomena, both being
dependent on the process, device dimensions, and
bias.

EMICROPB LP-LV Analog ICs 89

 4.19 Noise
 NOISE means spontaneous fluctuations in charge, current
or voltage generated in a component.

 NOISE is related to the discrete nature of carriers.

 Fundamental physical concepts behind noise are simple

BUT expressions to compute noise are often obscure.

 NOISE sets lower limits to the strength of signals that can be

processed.

 The understanding of noise is a key factor in low-power/low-

voltage designs.

EMICROPB LP-LV Analog ICs 90

4.19 Thermal noise of resistor/MOSFET

1
G= i2
R i2

i2 i2
= 4kTG = 4γ kTg ms
∆f ∆f

Bias-dependent factor ≈1

EMICROPB LP-LV Analog ICs 91

4.19 Flicker noise (1/f)

β
 Power spectral density (PSD): S(f) = K f β ≅1
 Mainly generated by fluctuations in number of

carriers and mobility due to random trapping-

detrapping of carriers near the surface of the
semiconductor.

 Exact mechanism and statistics of resulting noise

current, and correlation with technological

parameters are not yet clear.

EMICROPB LP-LV Analog ICs 92

 4.19 Flicker noise
Technology 1E-9 7
(Not=2.6x10 cm )
-2

parameter
1E-10

2
ich (flicker) K F g m2 1 1E-11
≅
∆f WLCox ′ f 1E-12
2

1/f Noise
SID/ID

(a)
Gate 1E-13 Thermal Noise
Simulated
(b)
Simulated
area Simulated
1E-14 ([Link] model) Measured
Measured
1E-15
10n 100n 1µ 10µ 100µ 1m 10m

Drain Current [A]

Normalized flicker and thermal PSD at f=1Hz for
saturated NMOS-T (W/L=200/5)
EMICROPB LP-LV Analog ICs 93
4.19 Corner frequency

PSD 100k

1/f noise

fc [Hz]
10k

white noise

Corner Frequency
Corner frequency fc
1k Calculated from measured gm
Calculated from estimated gm
fc Measured

π KF 100
100n 1µ 10µ 100µ
fc ≅ fT Drain Current ID [A]
2 nqφt
fT: MOSFET transition
fT 0.35 um CMOS
fc ≅ technology
frequency 2000
EMICROPB LP-LV Analog ICs 94
 4.20 Mismatch

 Mismatch: differences between identically designed

devices.
 Performance of many analog and also digital circuits
is based on how closely matched components are.
 Consequences of mismatch: offset voltage, current
mirror error, variable gate delay, lower resolution of
converters, deviations in frequency response,…..
 Lower supply voltages contribute to increase the
impact of process fluctuations on electronic systems.

EMICROPB LP-LV Analog ICs 95

4.20 Mismatch

R2
AV=- R2/R1 : gain depends on
R1
ratio (rather than on absolute
-
values of R’s); the relative
+ values of R’s must be matched
for accurate gain.

EMICROPB LP-LV Analog ICs 96

4.20 Dealing with mismatch

 GLOBAL variation ⇒ total variation of a parameter over a

wafer (or batch) caused by equipment variations & spatial
drift, e. g.
 Dimensional errors (photo-mask sizes, lens aberrations)
 Photo-resist thickness variations
 Mechanical strain variation
 Because GLOBAL variations are correlated across die,
they are minimized by design tricks:
 common centroid components
 distance reduction between identically designed pairs
 same orientation, etc.

EMICROPB LP-LV Analog ICs 97

4.20 Dealing with mismatch

 LOCAL variation ⇒ variation in a

component with respect to an identical
adjacent component, caused by atomistic
stochastic effects
 Designers must understand the
limitations imposed by LOCAL variations
on performance.

EMICROPB LP-LV Analog ICs 98

 4.20 Mismatch

R1 *

R2

Identically designed resistors

R2 R2 − R1 + R1 ∆R
= = 1+
R1 R1 R

* [Link]
EMICROPB LP-LV Analog ICs 99
4.20 Mismatch

ID ID
ID1 ID2
M2 M1 M2
M1
+ VGS1 - + VGS2 -

M1≡ M2 but ID1≠ ID2 for the M1≡ M2 but VGS1≠ VGS2 for
same set of voltages the same current

Fluctuations in doping, polysilicon

granularity, interface traps, channel length
& width & oxide thickness roughness,

EMICROPB LP-LV Analog ICs 100

4.20 A simple mismatch model

Mismatch in current
First order model (Vittoz): mismatch is caused by fluctuations in
ID specific current and threshold voltage

M
I D = I S f (VG − VT , VS , VD ) Long-channel MOST

∆ I D ∆I S g m
≅ − ∆VT
ID IS ID
2
σ 2
( I D ) ≅ σ ( I S ) +  gm  σ 2 V
2

Uncorrelated (?) mismatch sources: 2 2   ( T)

ID IS  ID 
Recall that, in saturation gm 2 1
=
I D nφt 1+ if +1
What about σ 2 ( I S ) and σ 2 (VT ) ?
EMICROPB LP-LV Analog ICs 101
4.20 A simple mismatch model

AVT2
ID σ 2
(VT ) ≅
WL M. J. M. Pelgrom, A. C. J. Duinmaijer, and A. P.
[Link], “Matching properties of MOS transistors,” IEEE
M
σ 2 ( IS ) AIS2 JSSC, vol. 24, no. 5, pp. 1433–1440, Oct. 1989.
≅
I S2 WL

0.35 µm n-well technology

Parameter NMOST PMOST Unit
AVT 9 9 mV⋅µm

AIS (Aβ) 1.9 2.25 % µm

EMICROPB LP-LV Analog ICs 102

 4.20 A simple mismatch model

M. J. M. Pelgrom, H. P. Tuinhout, and M.

Vertregt, “Transistor matching in analog CMOS
applications,” in IEDM Tech. Dig., 1998, pp. 915–918.

EMICROPB LP-LV Analog ICs 103

 Mismatch – experimental results

Test circuit
VG VD
IB ID

MREF Mi

VB

Test chip contains 20 samples of

each group of transistors in
0.35 µm CMOS technology

EMICROPB LP-LV Analog ICs 104

Mismatch – experimental results

EMICROPB LP-LV Analog ICs 105

Contents
1. Why low-power & low-voltage
2. Fundamental limitations in analog integrated
circuits
3. Components of the CMOS technology
4. MOSFET modeling
5. The basic gain stage
6. The current mirror
7. A self-biased current source
EMICROPB LP-LV Analog ICs 106
5. The common-source amplifier - 1
VDD ID M2
M1
M2 IB
IL
VO
ID
M1 CL IB VG
+
VI
VDD VO
vo Output characteristics
VDD vo=vi
Vmax
VDSsat2 From UICM we find the dc
Av voltage VTH at the input:
maximum
output VTH − VT 01
Vmin swing n1φt
≅ 1 + i f 1 − 2 + ln ( 1+ i f 1 −1)
VDSsat1
VTH VDD vi
IB
ID = IB ≅ IF1 − I R1; i f 1 ≅
Voltage transfer characteristic I S1
EMICROPB LP-LV Analog ICs
0 107
 5. The common-source amplifier - 2
VDD V-I converter (transconductor)
followed by an I-V converter
M2 IB
IL (output impedance)
vg vo
ID
M1
+
CL vi
+ gmv g go CL
VI

|AV|dB ωb = go / CL
vo  1  1
AV = = − g m   = AV 0 ωu = gm / CL
vi g
 o + sC L  1 + s / ωb |AV0|
-20 dB/dec
− g m1 − g m1 VA1 2
AV 0 = = AV 0 = −
go g ds1 n1φt 1 + 1 + i f 1
IB
g ds1 =
VA1 0 ωb ωu ω
VA1 = VE L1 Voltage gain vs frequency
EMICROPB LP-LV Analog ICs 108
 5. The common-source amplifier - 3
Design example Specifications: ωu , CL , AV 0
vg vo
g m = ωu ⋅ CL
+ 1+ if +1
vi I D = nφt g m How do we choose if ?
gmv g go CL
2

Sizing and biasing: W, L, IB

I D min = IWI = g m nφt
ECF = ( I D − IWI ) / IWI = ( )
1 + if −1 / 2
W gm 1 Power-area
=
L 2 µ Cox′ φt ECF tradeoff
VE L 1 How long can L be?
AV 0 = −
nφt ECF + 1
CIN and transit time are both ECF
proportional to L2 (for constant W/L)! ECF = ( I D − I D min ) / I D min
EMICROPB LP-LV Analog ICs 109
5. The common-source amplifier - 4
MOST noise Thermal 1/f
model 2
ich K F g m2 1  f 
= 4γ kTg ms + ≅ 4γ kTg ms 1 + c 
∆f WLCox ′ f  f 
Bias-dependent
2
ich Corner
factor
frequency
2 1/ 2  π KF
γ = 1 −  fc ≅ fT
Noise current 3  1 + i f + 1  2 nqφt

generator 1/2 (WI) 2/3 (SI) 2
ich / ∆f
Input-referred noise model

en2
Noiseless
- + f
MOST fc

en2 1 ich2 fc ≅
fT
0.35 um CMOS
= 2000
∆f g m2 ∆f technology
EMICROPB LP-LV Analog ICs 110
Contents
1. Why low-power & low-voltage
2. Fundamental limitations in analog integrated
circuits
3. Components of the CMOS technology
4. MOSFET modeling
5. The basic gain stage
6. The current mirror
7. A self-biased current source
EMICROPB LP-LV Analog ICs 111
6. The two-transistor current mirror - 1
VDD iD locus M1: i→v converter
vD=vG M2: v→i converter
ii
io
vo iD1
iD2 vG
M1 M2 +
+ -
vG
-
1:1 vo vD

Error due to difference in VD values Error due to mismatch

I D ≅ I S i f (VG − VT 0 , VS )(1 + VD / VA ) VD > VDsat ∆I D 1  ∂I ∂I 
≅  D ∆I S + D ∆VT 0 
ID I D  ∂I S ∂VT 0 
∆I g
≅ S − m ∆VT 0
IS ID
∆i io − ii vo − vi vo − vi 1  g m  2 
2 2

= ≅ ≅ σ 2 ( ∆I D )  g m  σ 2 ( ∆I S )
ii ii VA VE L
=  σ
2
( ∆VT ) + =   AVT + AIS 
2

I D2  D
I I S2 WL  I D  


EMICROPB LP-LV Analog ICs 112

6. The two-transistor current mirror - 2
VDD ac analysis
C A = Cgs1 + C gb1 + C gs 2 + Cgb 2 + Cdb1 + CB
ii
io ii C A = (1 + A ) ( C gs1 + Cgb1 ) + Cdb1 + Covd 2
CB io Io A C A + CB 1 + A
( s) ≅ τ= ≈
Ii 1+τ s g m1 2π fT
M1 M2 g m1
1:A
+
+ g ds1 CA gm2v
v
Noise analysis - Uncorrelated noise sources
2
g  gm2
ii
( )
io2 = ii2 + i12  m 2  + i22
 g m1  g m1
=A
io
(
io2 = A2 ii2 + i12 + Ai12)
i1 M1 M2 The effect of M1 on noise is A times greater
1:A i2 than that of M2
EMICROPB LP-LV Analog ICs 113
6. Current mirror: gain schemes
VDD
II IO VDD Gain=A Gain=1/(NM)
ii
io==Aii io==ii/(NM)
W/L W/L
W/L ......
1:2 ...
...
ii N
VDD VDD
II IO
ii io==ii/A .....
W/L W/L .
...... M
W/L
1/2:1
Gain= 1/A
EMICROPB LP-LV Analog ICs 114
Contents
1. Why low-power & low-voltage
2. Fundamental limitations in analog integrated
circuits
3. Components of the CMOS technology
4. MOSFET modeling
5. The basic gain stage
6. The current mirror
7. A self-biased current source
EMICROPB LP-LV Analog ICs 115
7. A self-biased current source - 1
SELF-CASCODE MOSFET (SCM)
I S 2 ( i f 2 − ir 2 )
0
= NI i f 2 = ir 1
x

I 2 = NI x I S 1 (i f 1 − i f 2 ) = ( N + 1) I x
Sat.
 S  1 
M2 i f 1 = 1 + 2  1 +   i f 2 = α i f 2
 S1  N 

M1 Applying UICM to both M1 & M2

Triode  1 + αi f 2 −1 
VX
= 1+ αif 2 − 1+ if 2 + ln  
φt  1+ i f 2 −1 
 
NI X NI X
if 2 = =
where IS2 S2 I SH

EMICROPB LP-LV Analog ICs 116

7. A self-biased current source - 2
SCM1,2
IX VX / φt

S2 = 0.01
IX

S1 = 0.01 2IX
SCM1,2 SCM3,4
α =3 α = 18.7
S 2 = 0.01 S 4 = 1.13
SCM3,4
IX

I X / I SH
S4 = 1.13
IX

S3 = 10 2IX  IX 
 1+α −1 
VX IX IX Seven I SH
= 1+ α − 1+ + ln  
φt Seven I SH S even I SH  IX 
S even  1   1 + − 1 
α = 1+ 1 + 
S odd  N   S even I SH 
EMICROPB LP-LV Analog ICs 117
 7. A self-biased current source - 3
VOLTAGE FOLLOWING (NMOS) CURRENT MIRROR (PMOS)1

Vref − VS 9  1 + JKi f 8 − 1 
= 1 + JKi f 8 − 1 + i f 8 + ln  
φt  1 + i f 8 −1 
 

When both M8 & M9 operate in WI:

Vref = VS 9 + φt ln( JK )

1 B. Gilbert, AICSP vol. 38, pp. 83-101, Feb. 2004

EMICROPB LP-LV Analog ICs 118

7. A self-biased current source - 4
1

VFCM
Vx Vx
VX / φt

SCM3,4
SCM1,2
VFCM is a positive feedback circuit →
return ratio must be < 1 for stability
I X / ISH

EMICROPB LP-LV Analog ICs 119

 Output current: Iref=10 nA
7. A SBCS: Design - 5 ISHn-channel≅100 nA, ISHp-channel≅40 nA

Let us choose if2 = 10, S2= S1

1
I S 2i f 2 = 10 nA → I S 2 = 1 nA → S 2 = S1 = 0.01
S2  1
α1−2 = 1 + 1 +  = 3
S1  N 
VX  1+ 30 −1
= 1+ 30 − 1+10 + ln   = 2.93 =10 nA
φt  1+10 −1 

Let us choose if3(4) <<1 (WI)

VX
≅ ln α 3− 4 ⇒ α 3− 4 = e 2.93 ≅ 18.7
φt VFCM
S4  1  S4
α 3− 4 = 1 + 1 +  ⇒ = 8.85
S3  1  S3

Let us choose if3=0.187 → i f 4 = i f 3 / α 3− 4 = 0.01

I S 4i f 4 = 10 nA → I S 4 = 1 µ A → S 4 = 10

S3 =
S4
= 1.13 VX  1 + α i f 2(4) − 1 
8.85 = 1 + α i f 2(4) − 1 + i f 2(4) + ln  
φt  1 + i f 2(4) − 1 
 
EMICROPB LP-LV Analog ICs 120
7. A SBCS: Design - 6
Summary

S if ir
M1 0.01 30 10
M2 0.01 10 0
M3 1.13 0.187 0.01
M4 10 0.01 0
M8, M8(a) 1 0. 1 0
M9, M9(a) 1 0. 1 0
MP (all) 2.5 0.1 0

Core area in 0.35µm CMOS ≈ 0.02 mm2

EMICROPB LP-LV Analog ICs 121
7. A SBCS – 7 IOUT vs. VDD at constant T

EMICROPB LP-LV Analog ICs 122

References for chapters 3, 4, 5

C. Galup-Montoro and M. C. Schneider, "MOSFET Modeling for Circuit Analysis and

Design", World Scientific, 2006, ISBN 981-256-810-7.
M. C. Schneider and C. Galup-Montoro, "CMOS Analog Design Using All-Region
MOSFET Modeling", Cambridge University Press, 2010, ISBN 978-0521110365.
Chapter 2 in E. Sánchez-Sinencio and A. G. Andreou (eds.), Low-Voltage/ Low Power
Integrated Circuits and Systems, IEEE Press, New York, 1999.
K. R. Laker and W. M. C. Sansen, Design of Analog Integrated Circuits and
Systems, 1994.
D. A. Johns and K. Martin, Analog Integrated Circuit Design, 1997.
P. R. Gray, P. J. Hurst, S. H. Lewis, and R. G. Meyer, Analysis and Design of Analog
Integrated Circuits, 4th edn., Wiley, 2001.
W. M. C. Sansen, Analog Design Essentials, Springer, 2006.
D. M. Binkley, Tradeoffs and Optimization in Analog CMOS Design, Wiley, 2008.
B. Razavi, Design of Analog CMOS Integrated Circuits, McGraw-Hill, 2001.
F. Maloberti, Analog Design for CMOS VLSI Systems, Kluwer, 2001.
P. E. Allen and D. R. Holberg, CMOS Analog Circuit Design, Oxford, 2002.

EMICROPB LP-LV Analog ICs 123

Some references for interesting work on LP-LV design

[Link] (Analog VLSI & Biological Systems Group)

S. Mandal, S. Zhak, and R. Sarpeshkar, "A Bio-Inspired Active Radio-Frequency
Silicon Cochlea," IEEE Journal of Solid-State Circuits, Vol. 44, No. 6, pp. 1814-
1828, June 2009.
R. Sarpeshkar et al, “Low-Power Circuits for Brain-Machine Interfaces,” IEEE
Trans. Biomedical Circuits and Systems, vol.2, no.3, pp.173-183, Sep. 2008.
X. Chen et al, “A Wireless Capsule Endoscope System with Low-Power Controlling
and Processing ASIC,” IEEE Trans. Biomedical Circuits and
Systems, vol.3, no.1, pp.11-22, Feb. 2009.
[Link]
[Link]
[Link]
[Link] (courses on Low-power & Low-voltage)

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EMICROPB LP-LV Analog ICs 125