a Complete 16-Bit Imaging

Signal Processor
AD9826
FEATURES PRODUCT DESCRIPTION
16-Bit 15 MSPS A/D Converter The AD9826 is a complete analog signal processor for imaging
3-Channel 16-Bit Operation up to 15 MSPS applications. It features a 3-channel architecture designed to
1-Channel 16-Bit Operation up to 12.5 MSPS sample and condition the outputs of trilinear color CCD arrays.
2-Channel Mode for Mono Sensors with Odd/Even Outputs Each channel consists of an input clamp, Correlated Double
Correlated Double Sampling Sampler (CDS), offset DAC, and Programmable Gain Amplifier
1~6ⴛ Programmable Gain (PGA), multiplexed to a high-performance 16-bit A/D converter.
ⴞ300 mV Programmable Offset The AD9826 can operate at speeds greater than 15 MSPS with
Input Clamp Circuitry reduced performance.
Internal Voltage Reference
Multiplexed Byte-Wide Output The CDS amplifiers may be disabled for use with sensors that
Optional Single Byte Output Mode do not require CDS, such as Contact Image Sensors (CIS),
3-Wire Serial Digital Interface CMOS active pixel sensors, and Focal Plane Arrays.
3 V/5 V Digital I/O Compatibility The 16-bit digital output is multiplexed into an 8-bit output word,
28-Lead SSOP Package which is accessed using two read cycles. There is an optional
Low Power CMOS: 400 mW (Typ) single byte output mode. The internal registers are programmed
Power-Down Mode Available through a 3-wire serial interface, and provide adjustment of
the gain, offset, and operating mode.
APPLICATIONS
Flatbed Document Scanners The AD9826 operates from a single 5 V power supply, typically
Digital Copier consumes 400 mW of power, and is packaged in a 28-lead SSOP.
Multifunction Peripherals
Infrared Imaging Applications
Machine Vision

FUNCTIONAL BLOCK DIAGRAM

AVDD AVSS CML CAPT CAPB AVDD AVSS DRVDD DRVSS

AD9826
VINR CDS PGA OEB
BANDGAP
9-BIT REFERENCE
DAC

3:1 16-BIT 16 16:8 8

VING CDS PGA DOUT
MUX ADC MUX

9-BIT
DAC CONFIGURATION
REGISTER

VINB PGA MUX

CDS
REGISTER SCLK
RED DIGITAL
9-BIT 6 CONTROL SLOAD
GREEN INTERFACE
DAC
BLUE GAIN SDATA
INPUT
REGISTERS
CLAMP RED
OFFSET BIAS 9
GREEN
BLUE OFFSET
REGISTERS

CDSCLK1 CDSCLK2 ADCCLK

REV. B
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
may result from its use. No license is granted by implication or otherwise Tel: 781/329-4700 [Link]
under any patent or patent rights of Analog Devices. Fax:  © Analog Devices, Inc., 
AD9826–SPECIFICATIONS
(TMIN to TMAX, AVDD = 5 V, DRVDD = 5 V, CDS Mode, fADCCLK = 15 MHz, fCDSCLK1 = fCDSCLK2 = 5 MHz, PGA
ANALOG SPECIFICATIONS Gain = 1, Input range = 4 V p-p, unless otherwise noted.)
Parameter Min Typ Max Unit
MAXIMUM CONVERSION RATE
3-Channel Mode with CDS 30 MSPS
2-Channel Mode with CDS 30 MSPS
1-Channel Mode with CDS 18 MSPS
ACCURACY (ENTIRE SIGNAL PATH)
ADC Resolution 16 Bits
Integral Nonlinearity (INL) ± 16 LSB
Differential Nonlinearity (DNL) ± 0.5 LSB
No Missing Codes Guaranteed
ANALOG INPUTS
Input Signal Range (Programmable)1 2.0/4.0 V p-p
Allowable Reset Transient1 1.0 V
Input Limits2 AVSS – 0.3 AVDD + 0.3 V
Input Capacitance 10 pF
Input Bias Current 10 nA
AMPLIFIERS
PGA Gain 1 6 V/V
PGA Gain Resolution2 64 Steps
PGA Gain Monotonicity Guaranteed
Programmable Offset –300 +300 mV
Programmable Offset Resolution 512 Steps
Programmable Offset Monotonicity Guaranteed
NOISE AND CROSSTALK
Total Output Noise @ PGA Minimum 3.0 LSB rms
Total Output Noise @ PGA Maximum 9.0 LSB rms
Channel-to-Channel Crosstalk
@ 15 MSPS 70 dB
@ 6 MSPS 90 dB
POWER SUPPLY REJECTION
AVDD = 5 V  0.25 V 0.1 % FSR
DIFFERENTIAL VREF (at 25°C)
CAPT–CAPB 2.0 V
TEMPERATURE RANGE
Operating –40 +85 °C
Storage –65 +150 °C
POWER SUPPLIES
AVDD 4.75 5.0 5.25 V
DRVDD 3.0 5.0 5.25 V
OPERATING CURRENT
AVDD 75 mA
DRVDD 5 mA
Power-Down Mode 200 μA
POWER DISSIPATION
3-Channel Mode 400 mW
1-Channel Mode 300 mW
NOTES
1
Linear Input Signal Range is from 0 V to 4 V when the CCD’s reference level is clamped to 4 V by the AD9826’s input clamp.

4V SET BY INPUT CLAMP

(3V OPTION ALSO AVAILABLE)
1V TYP
4V p-p MAX INPUT SIGNAL RANGE
RESET TRANSIENT
GND

6.0
2
The PGA Gain is approximately “linear in dB” and follows the equation: Gain = ⎡ 63 – G ⎤
where G is the register value.
1 + 5.0 ⎢ 63 ⎥
⎣ ⎦
Specifications subject to change without notice.

–2– REV. B
 AD9826
(TMIN to TMAX, AVDD = 5 V, DRVDD = 5 V, CDS Mode, fADCCLK = 15 MHz, fCDSCLK1 = fCDSCLK2 = 5 MHz,
DIGITAL SPECIFICATIONS CL = 10 pF, unless otherwise noted.)
Parameter Symbol Min Typ Max Unit
LOGIC INPUTS
High Level Input Voltage VIH 2.0 V
Low Level Input Voltage VIL 0.8 V
High Level Input Current IIH 10 μA
Low Level Input Current IIL 10 μA
Input Capacitance CIN 10 pF
LOGIC OUTPUTS
High Level Output Voltage VOH 4.5 V
Low Level Output Voltage VOL 0.1 V
High Level Output Current IOH 50 μA
Low Level Output Current IOL 50 μA
LOGIC OUTPUTS (with DRVDD = 3 V)
High Level Output Voltage, (IOH = 50 μA) VOH 2.95 V
Low Level Output Voltage (IOL = 50 μA) VOL 0.05 V
Specifications subject to change without notice.

TIMING SPECIFICATIONS (T MIN to TMAX, AVDD = 5 V, DRVDD = 5 V, specs are for 16-bit performance.)

Parameter Symbol Min Typ Max Unit

CLOCK PARAMETERS
3-Channel Pixel Rate tPRA 200 ns
1-Channel Pixel Rate tPRB 80 ns
ADCCLK Pulsewidth tADCLK 30 ns
CDSCLK1 Pulsewidth tC1 8 ns
CDSCLK2 Pulsewidth tC2 8 ns
CDSCLK1 Falling to CDSCLK2 Rising tC1C2 0 ns
ADCCLK Falling to CDSCLK2 Rising tADC2 0 ns
CDSCLK2 Rising to ADCCLK Rising tC2ADR 5 ns
CDSCLK2 Falling to ADCCLK Falling tC2ADF 30 ns
CDSCLK2 Falling to CDSCLK1 Rising tC2C1 5 ns
Aperture Delay for CDS Clocks tAD 2 ns
SERIAL INTERFACE
Maximum SCLK Frequency fSCLK 10 MHz
SLOAD to SCLK Set-Up Time tLS 10 ns
SCLK to SLOAD Hold Time tLH 10 ns
SDATA to SCLK Rising Set-Up Time tDS 10 ns
SCLK Rising to SDATA Hold Time tDH 10 ns
SCLK Falling to SDATA Valid tRDV 10 ns
DATA OUTPUTS
Output Delay tOD 6 ns
3-State to Data Valid tDV 10 ns
Output Enable High to 3-State tHZ 10 ns
Latency (Pipeline Delay) 3 (Fixed) Cycles
NOTES
It is recommended that CDSCLK falling edges do not occur within the first 10 ns following an ADCCLK edge.
Specifications subject to change without notice.

REV. B –3–
AD9826
ABSOLUTE MAXIMUM RATINGS*
With
Respect
Parameter To Min Max Unit
VIN, CAPT, CAPB AVSS –0.3 AVDD + 0.3 V
Digital Inputs AVSS –0.3 AVDD + 0.3 V
AVDD AVSS –0.5 +6.5 V THERMAL CHARACTERISTICS
DRVDD DRVSS –0.5 +6.5 V Thermal Resistance
AVSS DRVSS –0.3 +0.3 V 28-Lead 5.3 mm SSOP
Digital Outputs DRVSS –0.3 DRVDD + 0.3 V θJA = 109°C/W
Junction Temperature 150 °C θJC = 39°C/W
Storage Temperature –65 +150 °C
Lead Temperature 300 °C
(10 sec)

*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.

CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although WARNING!
the AD9826 features proprietary ESD protection circuitry, permanent damage may occur on devices
subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are recom-
ESD SENSITIVE DEVICE
mended to avoid performance degradation or loss of functionality.

–4– REV. B
 AD9826
PIN CONFIGURATION

CDSCLK1 1 28 AVDD

CDSCLK2 2 27 AVSS

ADCCLK 3 26 VINR

OEB 4 25 OFFSET

DRVDD 5 24 VING

DRVSS 6 23 CML
AD9826
(MSB) D7 7 22 VINB
TOP VIEW
D6 8 (Not to Scale) 21 CAPT

D5 9 20 CAPB

D4 10 19 AVSS

D3 11 18 AVDD

D2 12 17 SLOAD

D1 13 16 SCLK

(LSB) D0 14 15 SDATA

PIN FUNCTION DESCRIPTIONS

Pin No. Mnemonic Type Description

1 CDSCLK1 DI CDS Reference Level Sampling Clock
2 CDSCLK2 DI CDS Data Level Sampling Clock
3 ADCCLK DI A/D Converter Sampling Clock
4 OEB DI Output Enable, Active Low
5 DRVDD P Digital Output Driver Supply
6 DRVSS P Digital Output Driver Ground
7 D7 DO Data Output MSB. ADC DB15 High Byte, ADC DB7 Low Byte
8 D6 DO Data Output. ADC DB14 High Byte, ADC DB6 Low Byte
9 D5 DO Data Output. ADC DB13 High Byte, ADC DB5 Low Byte
10 D4 DO Data Output. ADC DB12 High Byte, ADC DB4 Low Byte
11 D3 DO Data Output. ADC DB11 High Byte, ADC DB3 Low Byte
12 D2 DO Data Output. ADC DB10 High Byte, ADC DB2 Low Byte
13 D1 DO Data Output. ADC DB9 High Byte, ADC DB1 Low Byte
14 D0 DO Data Output LSB. ADC DB8 High Byte, ADC DB0 Low Byte
15 SDATA DI/DO Serial Interface Data Input/Output
16 SCLK DI Serial Interface Clock Input
17 SLOAD DI Serial Interface Load Pulse
18, 28 AVDD P 5 V Analog Supply
19, 27 AVSS P Analog Ground
20 CAPB AO ADC Bottom Reference Voltage Decoupling
21 CAPT AO ADC Top Reference Voltage Decoupling
22 VINB AI Analog Input, Blue Channel
23 CML AO Internal Bias Level Decoupling
24 VING AI Analog Input, Green Channel
25 OFFSET AO Clamp Bias Level Decoupling
26 VINR AI Analog Input, Red Channel
TYPE: AI = Analog Input, AO = Analog Output, DI = Digital Input, DO = Digital Output, P = Power.

REV. B –5–
AD9826
DEFINITIONS OF SPECIFICATIONS INPUT REFERRED NOISE
INTEGRAL NONLINEARITY (INL) The rms output noise is measured using histogram techniques.
Integral nonlinearity error refers to the deviation of each individual The ADC output codes’ standard deviation is calculated in
code from a line drawn from “zero scale” through “positive full LSB, and can be converted to an equivalent voltage, using the
scale.” The point used as “zero scale” occurs 1/2 LSB before the relationship 1 LSB = 4 V/65536 = 61 μV. The noise may then
first code transition. “Positive full scale” is defined as a level be referred to the input of the AD9826 by dividing by the
1 1/2 LSB beyond the last code transition. The deviation is PGA gain.
measured from the middle of each particular code to the true
straight line. CHANNEL-TO-CHANNEL CROSSTALK
In an ideal 3-channel system, the signal in one channel will not
DIFFERENTIAL NONLINEARITY (DNL) influence the signal level of another channel. The channel-to-
An ideal ADC exhibits code transitions that are exactly 1 LSB channel crosstalk specification is a measure of the change that
apart. DNL is the deviation from this ideal value. Thus every occurs in one channel as the other two channels are varied. In
code must have a finite width. No missing codes guaranteed the AD9826, one channel is grounded and the other two chan-
to 16-bit resolution indicates that all 65536 codes, respec- nels are exercised with full scale input signals. The change in the
tively, must be present over all operating ranges. output codes from the first channel is measured and compared
with the result when all three channels are grounded. The differ-
OFFSET ERROR ence is the channel-to-channel crosstalk, stated in LSB.
The first ADC code transition should occur at a level 1/2 LSB
above the nominal zero scale voltage. The offset error is the APERTURE DELAY
deviation of the actual first code transition level from the The aperture delay is the time delay that occurs from when a
ideal level. sampling edge is applied to the AD9826 until the actual sample
of the input signal is held. Both CDSCLK1 and CDSCLK2
GAIN ERROR sample the input signal during the transition from high to low,
The last code transition should occur for an analog value so the aperture delay is measured from each clock’s falling edge
1 1/2 LSB below the nominal full scale voltage. Gain error is to the instant the actual internal sample is taken.
the deviation of the actual difference between first and last
code transitions and the ideal difference between the first and POWER SUPPLY REJECTION
last code transitions. Power supply rejection specifies the maximum full-scale change
that occurs from the initial value when the supplies are varied
over the specified limits.

–6– REV. B
 Typical Performance Characteristics–AD9826
20 1.0

10 0.5

0 0

–10 –0.5

–20 –1.0
0 12000 24000 36000 48000 64000 0 200 400 600 800 1000

TPC 1. Typical INL Performance at 15 MSPS TPC 4. Typical INL Performance at 30 MSPS

1.0 1.0

0.5 0.5

0 0

–0.5 –0.5

–1.0 –1.0
0 12000 24000 36000 48000 64000 0 200 400 600 800 1000

TPC 2. Typical DNL Performance at 15 MSPS TPC 5. Typical DNL Performance at 30 MSPS

10 10
NOISE – LSB RMS

NOISE – LSB RMS

5 5

0 0
0 15 30 45 63 0 15 30 45 63
GAIN SETTING GAIN SETTING

TPC 3. Output Noise vs. Gain TPC 6. Input Referred Noise vs. Gain

REV. B –7–
AD9826
TIMING DIAGRAMS

ANALOG
tAD PIXEL n (R,G,B) PIXEL PIXEL
INPUTS
(n+1) (n+2)

tAD

tC1 tPRA
tC2C1

CDSCLK1

tC1C2 tC2

tC2ADF
CDSCLK2

tADCLK tADC2 tC2ADR

ADCCLK

tADCLK tOD

OUTPUT
DATA R(n–2) G(n–2) G(n–2) B(n–2) B(n–2) R(n–1) R(n–1) G(n–1) G(n–1) B(n–1) B(n–1) R(n) R(n) G(n) G(n)
D<7:0>

HIGH LOW HB LB HB LB HB LB HB LB HB LB HB LB
BYTE BYTE

Figure 1. 3-Channel CDS Mode Timing

It is recommended that CDSCLK falling edges do not occur within the first 10 ns following an ADCCLK edge.

ANALOG PIXEL n PIXEL PIXEL

INPUTS tAD (n+1) (n+2)

tAD
tC1
tPRB
tC2C1

CDSCLK1
tC1C2
tC2

CDSCLK2

tC2ADR
tC2ADF

ADCCLK tADCLK

tADCLK tOD

OUTPUT
DATA PIXEL (n–4) PIXEL (n–4) PIXEL (n–3) PIXEL (n–3) PIXEL (n–2) PIXEL (n–2)
D<7:0>

HIGH BYTE LOW BYTE HIGH BYTE LOW BYTE HIGH BYTE LOW BYTE

NOTE
IN 1-CHANNEL CDS MODE, THE CDSCLK1 FALLING EDGE AND THE CDSCLK2 RISING EDGE MUST OCCUR WHILE ADCCLK IS “LOW.”

Figure 2. 1-Channel CDS Mode Timing

–8– REV. B
 AD9826

ANALOG tAD PIXEL n PIXEL (n+1) PIXEL (n+2)

INPUTS

tAD

tC1 tPRA
tC2C1

CDSCLK1

tC1C2 tC2

CDSCLK2
tC2ADR
tADC2 tC2ADF

ADCCLK

tADCLK tADCLK
OUTPUT
DATA CH1(n–2) CH2(n–2) CH1(n–1) CH2(n–1) CH1(n)
D<7:0>
HIGH LOW HIGH LOW HIGH LOW HIGH LOW HIGH LOW
BYTE BYTE BYTE BYTE BYTE BYTE BYTE BYTE BYTE BYTE

Figure 3. 2-Channel CDS Mode Timing

PIXEL
PIXEL n (n+1)

ANALOG tAD
INPUTS
tC2

CDSCLK2

tC2ADR
tADC2 tC2ADF

ADCCLK

tADCLK tADCLK

OUTPUT
DATA CH1(n–2) CH2(n–2) CH1(n–1) CH2(n–1) CH1(n)
D<7:0>
HIGH LOW HIGH LOW HIGH LOW HIGH LOW HIGH LOW
BYTE BYTE BYTE BYTE BYTE BYTE BYTE BYTE BYTE BYTE

Figure 4. 2-Channel SHA Mode Timing

REV. B –9–
AD9826

PIXEL n (R,G,B) PIXEL (n+1)

tAD
ANALOG
INPUTS

tPRA

tC2

tC2AD
CDSCLK2

tADCLK tADC2 tC2ADR

ADCCLK

tADCLK tOD

OUTPUT
DATA R (n–2) G (n–2) G (n–2) B (n–2) B (n–2) R (n–1) R (n–1) G (n–1) G (n–1) B (n–1) B (n–1) R (n) R (n) G (n) G (n)
D<7:0>
HIGH LOW HB LB HB LB HB LB HB LB HB LB HB LB
BYTE BYTE

Figure 5. 3-Channel SHA Mode Timing

PIXEL n

tAD
ANALOG
INPUTS

tPRB

tC2

CDSCLK2

tC2ADR
tC2ADF

ADCCLK
tADCLK

ttADCLK
ADCLK tOD

OUTPUT
DATA PIXEL (n–4) PIXEL (n–4) PIXEL (n–3) PIXEL (n–3) PIXEL (n–2) PIXEL (n–2)
D<7:0>

HIGH BYTE LOW BYTE HIGH BYTE LOW BYTE HIGH BYTE LOW BYTE

NOTE
IN 1-CHANNEL SHA MODE, THE CDSCLK2 RISING EDGE MUST OCCUR WHILE ADCCLK IS “LOW.”

Figure 6. 1-Channel SHA Mode Timing

–10– REV. B
 AD9826

ADCCLK

tOD tOD

OUTPUT HIGH BYTE LOW BYTE HB LB LB HB

DATA DB15–DB8 DB7–DB0 n+1 n+1 n+2 n+3
<D7:D0>

PIXEL n PIXEL n
tHZ tDV

OEB

Figure 7. Digital Output Data Timing

ADCCLK

tOD

OUTPUT HIGH BYTE HIGH BYTE HB HB

DATA DB15–DB8 DB15–DB8 n+2 n+3
<D7:D0>
PIXEL n PIXEL n+1
tHZ tDV

OEB

Figure 8. Single Byte Mode Digital Output Data Timing

R/Wb
SDATA A2 A1 A0 D8 D7 D6 D5 D4 D3 D2 D1 D0

tDH tDS

SCLK

tLS tLH

SLOAD

Figure 9. Serial Write Operation Timing

SDATA A2 A1 A0 D8 D7 D6 D5 D4 D3 D2 D1 D0
R/Wb

tRDV

SCLK

tLS tLH

SLOAD

Figure 10. Serial Read Operation Timing

REV. B –11–
AD9826

ANALOG
INPUTS PIXEL n (R,G,B) PIXEL (n+1)

CDSCLK1

CDSCLK2

ADCCLK

RED
PGA RED (n–1) RED (n) RED (n+1)
OUT

GREEN
PGA GREEN (n–1) GREEN (n) GREEN (n+1)
OUT

BLUE
PGA BLUE (n–1) BLUE (n) BLUE (n+1)
OUT

MUX
OUT GREEN (n–1) BLUE (n–1) RED (n) GREEN (n) BLUE (n) RED (n+1) GREEN (n+1)

OUTPUT
DATA R(n–2) G(n–2) G(n–2) B(n–2) B(n–2) R(n–1) R(n–1) G(n–1) G(n–1) B(n–1) B(n–1) R(n) R(n) G(n) G(n)
D<7:0>
HIGH LOW HB LB HB LB HB LB HB LB HB LB HB LB
BYTE BYTE

NOTES
1. THE MUX STATE MACHINE IS INTERNALLY RESET AT THE CDSCLK2 RISING EDGE.
2. EACH PIXEL IS SAMPLED AND AMPLIFIED BY THE PGAs AT CDSCLK2 FALLING EDGE.
3. AFTER CDSCLK2 RISING EDGE, THE NEXT ADCCLK RISING EDGE WILL ALWAYS SELECT RED PGA OUTPUT.
4. THE ADC SAMPLES THE MUX OUTPUT ON ADCCLK FALLING EDGES.
5. THE MUX SWITCHES TO THE NEXT PGA OUTPUT AT ADCCLK RISING EDGES.

Figure 11. Internal Timing Diagram for 3-Channel CDS Mode

–12– REV. B
 AD9826
FUNCTIONAL DESCRIPTION 2-Channel CDS Mode
The AD9826 can be operated in six different modes: 3-Channel The 2-Channel Mode is selected by writing a “1” into two of the
CDS Mode, 3-Channel SHA Mode, 2-Channel CDS Mode, channel select bits of the MUX register (D4–D6). Bit D5 of the
2-Channel SHA Mode, 1-Channel CDS Mode, and 1-Channel configuration register also needs to be set low to take the part out
SHA Mode. Each mode is selected by programming the Configura- of 3-Channel Mode. The channels that will be used is determined
tion Registers through the serial interface. For more detail on by the contents of Bits D4–D6 of the MUX Configuration Reg-
CDS or SHA mode operation, see the Circuit Operation section. ister (see Table III). The combination of inputs that can be
3-Channel CDS Mode selected are; RG, RB, or GB by writing a “1” into the appropri-
In 3-Channel CDS Mode, the AD9826 simultaneously samples ate bit. The sample order is selected by Bit D7. If D7 is high,
the Red, Green, and Blue input voltages from the CCD outputs. the MUX will sample in the following order: RG or RB or GB
The sampling points for each Correlated Double Sampler (CDS) depending on which channels are turned on. If Bit D7 is set low
are controlled by CDSCLK1 and CDSCLK2 (see Figures 11 the mux will sample in the following order: GR or BR or BG
and 13). CDSCLK1’s falling edge samples the reference level of depending on which channels are turned on.
the CCD waveform. CDSCLK2’s falling edge samples the data The AD9826 simultaneously samples the selected channels’
level of the CCD waveform. Each CDS amplifier outputs the input voltages from the CCD outputs. The sampling points
difference between the CCD’s reference and data levels. Next, for each Correlated Double Sampler (CDS) are controlled by
the output voltage of each CDS amplifier is level-shifted by an CDSCLK1 and CDSCLK2 (see Figure 11). CDSCLK1’s fall-
Offset DAC. The voltages are then scaled by the three Program- ing edge samples the reference level of the CCD waveform.
mable Gain Amplifiers before being multiplexed through the CDSCLK2’s falling edge samples the data level of the CCD
16-Bit ADC. The ADC sequentially samples the PGA outputs waveform. Each CDS amplifier outputs the difference between
on the falling edges of ADCCLK. the CCD’s reference and data levels. Next, the output voltage of
The offset and gain values for the Red, Green, and Blue chan- each CDS amplifier is level-shifted by an Offset DAC. The volt-
nels are programmed using the serial interface. The order in ages are then scaled by the two Programmable Gain Amplifiers
which the channels are switched through the multiplexer is before being multiplexed through the 16-bit ADC. The ADC
selected by programming the MUX Configuration register. sequentially samples the PGA outputs on the falling edges of
ADCCLK.
Timing for this mode is shown in Figure 1. It is recommended
that the falling edge of CDSCLK2 occur before the rising edge The offset and gain values for the Red, Green, and Blue chan-
of ADCCLK, although this is not required to satisfy the mini- nels are programmed using the serial interface. The order in
mum timing constraints. The rising edge of CDSCLK2 should which the channels are switched through the multiplexer is
not occur before the previous falling edge of ADCCLK, as selected by programming the MUX Configuration Register.
shown by tADC2. The output data latency is three clock cycles. Timing for this mode is shown in Figure 3. The rising edge of
3-Channel SHA Mode CDSCLK2 should not occur before the previous falling edge of
In 3-Channel SHA Mode, the AD9826 simultaneously samples ADCCLK, as shown by tADC2. The output data latency is three
the Red, Green, and Blue input voltages. The sampling point is clock cycles.
controlled by CDSCLK2. CDSCLK2’s falling edge samples the 2-Channel SHA Mode
input waveforms on each channel. The output voltages from the The 2-Channel Mode is selected by writing a “1” into two of the
three SHAs are modified by the offset DACs and then scaled by channel select bits of the MUX Register (D4–D6). Bit D5 of the
the three PGAs. The outputs of the PGAs are then multiplexed configuration register also needs to be set low to take the part
through the 16-bit ADC. The ADC sequentially samples the out of 3-Channel Mode. The channels that will be used is deter-
PGA outputs on the falling edges of ADCCLK. mined by the contents of Bits D4–D6 of the MUX Configuration
The input signal is sampled with respect to the voltage applied Register (see Table III ). The combination of inputs that can be
to the OFFSET pin (see Figure 14). With the OFFSET pin selected are; RG, RB, or GB by writing a “1” into the appropri-
grounded, a zero volt input corresponds to the ADC’s zero scale ate bit. The sample order is selected by Bit D7. If D7 is high,
output. The OFFSET pin may also be used as a coarse offset the mux will sample in the following order: RG or RB or GB,
adjust pin. A voltage applied to this pin will be subtracted from depending on which channels are turned on. If Bit D7 is set low,
the voltages applied to the Red, Green, and Blue inputs in the first the mux will sample in the following order: GR or BR or BG,
amplifier stage of the AD9826. The input clamp is disabled in this depending on which channels are turned on.
mode. For more information, see the Circuit Operation section. In 2-Channel SHA Mode, the AD9826 simultaneously samples
Timing for this mode is shown in Figure 5. CDSCLK1 should the selected channels’ input voltages. The sampling point is
be grounded in this mode. Although it is not required, it is recom- controlled by CDSCLK2. CDSCLK2’s falling edge samples the
mended that the falling edge of CDSCLK2 occur before the input waveforms on each channel. The output voltages from the
rising edge of ADCCLK. The rising edge of CDSCLK2 should two SHAs are modified by the offset DACs and then scaled by
not occur before the previous falling edge of ADCCLK, as shown the two PGAs. The outputs of the PGAs are then multiplexed
by tADC2. The output data latency is three ADCCLK cycles. through the 16-bit ADC. The ADC sequentially samples the PGA
outputs on the falling edges of ADCCLK.
The offset and gain values for the Red, Green, and Blue chan-
nels are programmed using the serial interface. The order in The input signal is sampled with respect to the voltage applied
which the channels are switched through the multiplexer is to the OFFSET pin (see Figure 14). With the OFFSET pin
selected by programming the MUX Configuration register. grounded, a zero volt input corresponds to the ADC’s zero scale
output. The OFFSET pin may also be used as a coarse offset

REV. B –13–
AD9826
adjust pin. A voltage applied to this pin will be subtracted from Bit D7 controls the input range of the AD9826. Setting D7 high
the voltages applied to the Red, Green, and Blue inputs in the first sets the input range to 4 V while setting Bit D7 low sets the
amplifier stage of the AD9826. The input clamp is disabled in this input range to 2 V. Bit D6 controls the internal voltage refer-
mode. For more information, see the Circuit Operation section. ence. If the AD9826’s internal voltage reference is used, then
Timing for this mode is shown in Figure 4. CDSCLK1 should this bit is set high. Setting Bit D6 low will disable the internal
be grounded in this mode. The rising edge of CDSCLK2 should voltage reference, allowing an external voltage reference to be
not occur before the previous falling edge of ADCCLK, as shown used. Setting Bit D5 high will configure the AD9826 for 3-
by tADC2. The output data latency is three ADCCLK cycles. The channel operation. If D5 is set low, the part will be in either
offset and gain values for the Red, Green, and Blue channels are 2CH or 1CH mode based on the settings in the MUX Configu-
programmed using the serial interface. The order in which the ration Register (See Table III and the MUX Configuration
channels are switched through the multiplexer is selected by Register description). Setting Bit D4 high will enable the CDS
programming the MUX Configuration Register. mode of operation, and setting this bit low will enable the SHA
mode of operation. Bit D3 sets the dc bias level of the AD9826’s
1-Channel CDS Mode input clamp.
This mode operates the same way as the 3-Channel CDS mode.
The difference is that the multiplexer remains fixed in this mode, This bit should always be set high for the 4 V clamp bias, unless
so only the channel specified in the MUX Configuration Regis- a CCD with a reset feedthrough transient exceeding 2 V is used.
ter is processed. If the 3 V clamp bias level is used, then the peak-to-peak input
signal range to the AD9826 is reduced to 3 V maximum. Bit D2
Timing for this mode is shown in Figure 2. controls the power-down mode. Setting Bit D2 high will place
1-Channel SHA Mode the AD9826 into a very low-power “sleep” mode. All register
This mode operates the same way as 3-Channel SHA mode, contents are retained while the AD9826 is in the powered-down
except that the multiplexer remains stationary. Only the channel state. Bit D0 controls the output mode of the AD9826. Setting
specified in the MUX Configuration Register is processed. Bit D0 high will enable a single byte output mode where only
the 8 MSBs of the 16 b ADC will be output on each rising edge
Timing for this mode is shown in Figure 6. CDSCLK1 should
of ADCCLK (see Figure 8). If Bit D0 is set low, then the 16 b
be grounded in this mode of operation.
ADC output is multiplexed into two bytes. The MSByte is
Configuration Register output on ADCCLK rising edge and the LSByte is output on
The Configuration Register controls the AD9826’s operating ADCCLK falling edge.
mode and bias levels. Bits D8 and D1 should always be set low.

Table I. Internal Register Map

Register Address Data Bits

Name A2 A1 A0 D8 D7 D6 D5 D4 D3 D2 D1 D0
Configuration 0 0 0 0 Input Rng VREF 3CH Mode CDS On Clamp Pwr Dn 0 1 Byte Out
MUX Config 0 0 1 0 RGB/BGR Red Green Blue 0 0 0 0
Red PGA 0 1 0 0 0 0 MSB LSB
Green PGA 0 1 1 0 0 0 MSB LSB
Blue PGA 1 0 0 0 0 0 MSB LSB
Red Offset 1 0 1 MSB LSB
Green Offset 1 1 0 MSB LSB
Blue Offset 1 1 1 MSB LSB

Table II. Configuration Register Settings

D8 D7 D6 D5 D4 D3 D2 D1 D0
Set Input Range Internal VREF 3CH Mode CDS Operation Input Clamp Bias Power-Down Set Output Mode
to to
1 = 4 V* 1 = Enabled* 1 = On* 1 = CDS Mode* 1 = 4 V* 1 = On 0 = 2 Byte*
0 0
0=2V 0 = Disabled 0 = Off 0 = SHA Mode 0=3V 0 = Off (Normal)* 1 = 1 Byte
*Power-on default value.

–14– REV. B
 AD9826
MUX Configuration Register PGA Gain Registers
The MUX Configuration Register controls the sampling chan- There are three PGA registers for individually programming the
nel order and the 2-Channel Mode configuration in the AD9826. gain in the Red, Green, and Blue channels. Bits D8, D7, and
Bits D8 and D3–D0 should always be set low. Bit D7 is used D6 in each register must be set low, and Bits D5 through D0
when operating in 3-Channel or 2-Channel Mode. Setting Bit control the gain range from 1× to 6× in 64 increments. See
D7 high will sequence the MUX to sample the Red channel Figure 17 for a graph of the PGA gain versus PGA register
first, then the Green channel, and then the Blue channel. When code. The coding for the PGA registers is straight binary, with
in 3-channel mode, the CDSCLK2 pulse always resets the MUX an all “zeros” word corresponding to the minimum gain setting
to sample the Red channel first (see Figure 11). When Bit D7 is (1×) and an all “ones” word corresponding to the maximum
set low, the channel order is reversed to Blue first, Green sec- gain setting (6×).
ond, and Red third. The CDSCLK2 pulse will always reset the Offset Registers
MUX to sample the Blue channel first. Bits D6, D5, and D4 are There are three Offset Registers for individually programming
used when operating in 1 or 2-Channel Mode. Bit D6 is set high the offset in the Red, Green, and Blue channels. Bits D8 through
to sample the Red channel. Bit D5 is set high to sample the D0 control the offset range from –300 mV to +300 mV in 512
Green channel. Bit D4 is set high to sample the Blue channel. increments. The coding for the Offset Registers is Sign Mag-
The MUX will remain stationary during 1-channel mode. Two- nitude, with D8 as the sign bit. Table V shows the offset range
Channel Mode is selected by setting two of the channel select as a function of the Bits D8 through D0.
Bits (D4–D6) high. The MUX samples the channels in the
order selected by Bit D7.

Table III. MUX Configuration Register Settings

D8 D7 D6 D5 D4 D3 D2 D1 D0
Set MUX Order Channel Select Channel Select Channel Select Set Set Set Set
to to to to to
1 = R-G-B* 1 = RED* 1 = GREEN 1 = BLUE
0 0 0 0 0
0 = B-G-R 0 = Off 0 = Off* 0 = Off*
*Power-on default value.

Table IV. PGA Gain Register Settings

D8 D7 D6 D5 D4 D3 D2 D1 D0 Gain (V/V) Gain (dB)

Set to 0 Set to 0 Set to 0 MSB LSB
0 0 0 0 0 0 0 0 0* 1.0 0.0
0 0 0 0 0 0 0 0 1 1.013 0.12
• • •
• • •
• • •
0 0 0 1 1 1 1 1 1 5.56 14.9
0 0 0 1 1 1 1 1 1 6.0 15.56
*Power-on default value.

Table V. Offset Register Settings

D8 D7 D6 D5 D4 D3 D2 D1 D0 Offset (mV)
MSB LSB
0 0 0 0 0 0 0 0 0* 0
0 0 0 0 0 0 0 0 1 +1.2
• •
• •
• •
0 1 1 1 1 1 1 1 1 +300
1 0 0 0 0 0 0 0 0 0
1 0 0 0 0 0 0 0 1 –1.2
• •
• •
• •
1 1 1 1 1 1 1 1 1 –300
*Power-on default value.

REV. B –15–
AD9826
CIRCUIT OPERATION External Input Coupling Capacitors
Analog Inputs—CDS Mode Operation The recommended value for the input coupling capacitors is
Figure 12 shows the analog input configuration for the CDS 0.1 μF. While it is possible to use a smaller capacitor, this larger
mode of operation. Figure 13 shows the internal timing for the value is chosen for several reasons:
sampling switches. The CCD reference level is sampled when Crosstalk
CDSCLK1 transitions from high to low, opening S1. The CCD The input coupling capacitor creates a capacitive divider with
data level is sampled when CDSCLK2 transitions from high to any parasitic capacitance between PCB traces and on chip traces.
low, opening S2. S3 is then closed, generating a differential CIN should be large relative to these parasitic capacitances in
output voltage representing the difference between the two order to minimize this effect. For example, with a 100 pF input
sampled levels. capacitance and just a few hundred f F of parasitic capacitance
The input clamp is controlled by CDSCLK1. When CDSCLK1 on the PCB and/or the IC the imaging system could expect
is high, S4 closes and the internal bias voltage is connected to to have hundreds of LSBs of crosstalk at the 16 b level. Using
the analog input. The bias voltage charges the external 0.1 μF a large capacitor value = 0.1 μF will minimize any errors due
input capacitor, level-shifting the CCD signal into the AD9826’s to crosstalk.
input common-mode range. The time constant of the input Signal Attenuation
clamp is determined by the internal 5 kΩ resistance and the The input coupling capacitor creates a capacitive divider with a
external 0.1 μF input capacitance. CMOS integrated circuit’s input capacitance, attenuating the
CCD signal level. CIN should be large relative to the IC’s 10 pF
input capacitance in order to minimize this effect.
AD9826
Linearity
VINR
S1 4pF Some of the input capacitance of a CMOS IC is junction capaci-
CCD
SIGNAL
CML tance, which varies nonlinearly with applied voltage. If the input
0.1␮F coupling capacitor is too small, then the attenuation of the CCD
S3 signal will vary nonlinearly with signal level. This will degrade
5K
the system linearity performance.
S2
CML Sampling Errors
4pF The internal 4 pF sample capacitors have a “memory” of the
S4 previously sampled pixel. There is a charge redistribution error
between CIN and the internal sample capacitors for larger pixel-
1.7k⍀
to-pixel voltage swings. As the value of CIN is reduced, the
OFFSET 4V
resulting error in the sampled voltage will increase. With a CIN
+
1␮F 0.1␮F 2.2k⍀
INPUT CLAMP LEVEL
IS SELECTED IN THE value of 0.1 μF, the charge redistribution error will be less than
3V CONFIGURATION
REGISTER
1 LSB for a full-scale pixel-to-pixel voltage swing.
6.9k⍀

Figure 12. CDS-Mode Input Configuration (All Three

Channels Are Identical)

S1, S4 CLOSED S1, S4 CLOSED

CDSCLK1
S1, S4 OPEN

S2 CLOSED S2 CLOSED

CDSCLK2 S2 OPEN

S3 CLOSED S3 CLOSED

Q3
(INTERNAL) S3 OPEN

Figure 13. CDS-Mode Internal Switch Timing

–16– REV. B
 AD9826
Analog Inputs—SHA Mode Operation Figure 16 shows how the OFFSET pin may be used in a CIS
Figure 14 shows the analog input configuration for the SHA application for coarse offset adjustment. Many CIS signals have
mode of operation. Figure 15 shows the internal timing for the dc offsets ranging from several hundred millivolts to more than
sampling switches. The input signal is sampled when CDSCLK2 1 V. By connecting the appropriate dc voltage to the OFFSET
transitions from high to low, opening S1. The voltage on the pin, the CIS signal will be restored to “zero.” After the large dc
OFFSET pin is also sampled on the falling edge of CDSCLK2, offset is removed, the signal can be scaled using the PGA to
when S2 opens. S3 is then closed, generating a differential out- maximize the ADC’s dynamic range.
put voltage representing the difference between the sampled
input voltage and the OFFSET voltage. The input clamp is
disabled during SHA mode operation. AD9826

AD9826 RED
VINR
RED-
SHA
4pF OFFSET
S1
INPUT VINR
CML
SIGNAL
VING
GREEN
GREEN-
SHA
S3 OFFSET
S2 4pF
OPTIONAL DC OFFSET
OFFSET (OR CML
VINB
CONNECT BLUE
TO GND) SHA BLUE-
OFFSET
VING
VRED FROM
CIS MODULE OFFSET

AVDD
0.1␮F
R1

DC OFFSET
VINB
R2

Figure 16. SHA-Mode Used with External DC Offset

Figure 14. SHA-Mode Input Configuration (All Three

Channels Are Identical)

S1, S2 CLOSED S1, S2 CLOSED

CDSCLK2 S1, S2 OPEN

S3 CLOSED S3 CLOSED

Q3
(INTERNAL) S3 OPEN

Figure 15. SHA-Mode Internal Switch Timing

REV. B –17–
AD9826
Programmable Gain Amplifiers APPLICATIONS INFORMATION
The AD9826 uses one Programmable Gain Amplifier (PGA) for Circuit and Layout Recommendations
each channel. Each PGA has a gain range from 1× (0 dB) to The recommended circuit configuration for 3-Channel CDS
6.0× (15.56 dB), adjustable in 64 steps. Figure 17 shows the Mode operation is shown in Figure 18. The recommended
PGA gain as a function of the PGA register code. Although the input coupling capacitor value is 0.1 μF (see Circuit Operation
gain curve is approximately “linear in dB,” the gain in V/V var- section for more details). A single ground plane is recommended
ies nonlinearly with register code, following the equation: for the AD9826. A separate power supply may be used for
6.0 DRVDD, the digital driver supply, but this supply pin should
Gain = still be decoupled to the same ground plane as the rest of the
⎡ 63 – G ⎤ AD9826. The loading of the digital outputs should be mini-
1 + 5.0 ⎢ ⎥
⎣ 63 ⎦ mized, either by using short traces to the digital ASIC, or by
where G is the decimal value of the gain register contents, and using external digital buffers. To minimize the effect of digital
varies from 0 to 63. transients during major output code transitions, the falling edge
of CDSCLK2 should occur coincident with or before the
16 6.00 rising edge of ADCCLK (see Figures 1 through 6 for timing).
All 0.1 μF decoupling capacitors should be located as close as
possible to the AD9826 pins. When operating in 1CH or 2CH
12 4.75 Mode, the unused analog inputs should be grounded.
For 3-Channel SHA Mode, all of the above considerations also
apply, except that the analog input signals are directly connected
GAIN – V/V
GAIN – dB

8 3.50 to the AD9826 without the use of coupling capacitors. The analog
GAIN – dB input signals must already be dc-biased between 0 V and 4 V.
Also, the OFFSET pin should be grounded if the inputs to the
4 2.25
AD9826 are to be referenced to ground, or a dc offset voltage
GAIN – V/V should be applied to the OFFSET pin in the case where a coarse
offset needs to be removed from the inputs. (See Figure 16 and
the Circuit Operation section for more details.)
0 1.00
0 12 24 36 48 60 63
PGA REGISTER VALUE – Decimal

Figure 17. PGA Gain Transfer Function

5V
0.1␮F
RED INPUT
CLOCK
INPUTS 0.1␮F
0.1␮F GREEN INPUT
CDSCLK1 AVDD
1 28
CDSCLK2 AVSS
2 27
ADCCLK VINR 0.1␮F
3 26
OEB OFFSET BLUE INPUT
5V/3V 4 25
DRVDD VING
5 24 0.1␮F 1.0␮F
DRVSS CML 0.1␮F
0.1␮F 6 23
(MSB) D7 AD9826 VINB 0.1␮F
7 22
D6 TOP VIEW
CAPT
8 (Not to Scale) 21 0.1␮F 10␮F
D5 CAPB
9 20
D4 AVSS 0.1␮F
10 19
D3 AVDD
11 18
D2 SLOAD 0.1␮F
12 17
D1 SCLK
13 16
(LSB)D0 SDATA 5V
14 15

DATA
SERIAL
INPUTS
INTERFACE

Figure 18. Recommended Circuit Configuration, 3-Channel CDS Mode

–18– REV. B
 AD9826
OUTLINE DIMENSIONS
10.50
10.20
9.90

28 15

5.60
5.30
5.00 8.20
7.80
1 7.40
14

1.85 0.25
2.00 MAX 1.75 0.09
1.65

8° 0.95
0.05 MIN 0.38
SEATING 4° 0.75
COPLANARITY 0.22 PLANE
0.65 BSC 0° 0.55
0.10

060106-A
COMPLIANT TO JEDEC STANDARDS MO-150-AH

Figure 19. 28-Lead Shrink Small Outline Package [SSOP]

(RS-28)
Dimensions shown in millimeters

Revision History
Location Page
Data Sheet changed from REV. 0 to REV. A.
Edits to ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Edits to Figure 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Edits to Figure 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

6/12—Rev. A to Rev. B
Changes to Ordering Guide ............................................................................................................................................................................................ 20

REV. B –19–
AD9826
ORDERING GUIDE
Model1 Temperature Range Package Description Package Option
AD9826KRSZ −40°C to +85°C 28-Lead Shrink Small Outline Package [SSOP] RS-28
AD9826KRSZRL −40°C to +85°C 28-Lead Shrink Small Outline Package [SSOP] RS-28
1
Z = RoHS Compliant Part.

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registered trademarks are the property of their respective owners.
D02367-0-/12(B)

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