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EC 5014 CMOS Analog IC Design
Analog ic Design (Anna University)
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ANNA UNIVERSITY (UNIVERSITY DEPARTMENTS)
B.E. / B. Tech / B. Arch (Full Time) - END SEMESTER EXAMINATIONS, NOV/DEC 2023
ELECTRONICS AND COMMUNICATION ENGINEERING
V Semester
EC5014 CMOS Analog IC Design
(Regulation 2019)
Time: 3hrs Max.Marks: 100
CO 1 To carry out design of the various building blocks used in CMOS analog ICs. These include current
mirror, cascades, common source amplifiers, differential amplifiers, two stage OTAs, source
followers.
CO 2 To carry out the paper design based on hand calculations for the above important building blocks.
This is normally the first mandatory step in the complete design and fabrication of CMOS Analog
ICs, and enables the student to carry out circuit simulations and layout design. In conjunction with
other similar courses in this area.
COB To pursue design and/or research carriers in the broad field of electronics and communication.
BL - Bloom's Taxonomy Levels
(LI - Remembering, L2 - Understanding, L3 - Applying, L4 - Analysing, L5 - Evaluating, L6 - Creating)
PART-A (10x2 = 20 Marks)
(Answer all Questions)
Q. No Questions Ma CO BL
rks
1 For the circuit in Fig. 1, assume (W/L)2 = 2(W/L)i and (W/L)4=2(W/L)3. Determine 2 COl L2
the raio of (14/lRef)
2 For Fig. 2, give the expression for the minimum voltage that can be obtained at 2 C02 L3
the drain of M4.
3 Consider the two possible open loop transfer functions given below and indicate 2 C02 L3
which one is more preferable from stability point of view when used in a
feedback amplifier configuration. Assume fpi<fz<fp2
AoLi= (l+jf/fz)/{(l+jf/fpi)(l+jf/fp2)} or Aoa= (l-jf/fz)/{(l+jf/fpi)(l+jf/fp2)};
4 Explain why Miller effect is not sufficient to fully explain the high frequency 2 COl L2
behavior of a common source amplifier.
5 With the help of a suitable diagram of your choice, explain the principle of folded 2 C02 L2
cascode amplifier.
6 An open loop amplifier has low input impedance and high output impedance. 2 C02 L3
Using this amplifier in negative feedback, it is required to reduce the closed loop
input impedance further and also increase the output impedance. Explain what
signal should be sensed at the output and what signal should be feedback as the
input.
7 In the equivalent circuit in Fig.3, identify the capacitors that are not due to 2 COl L2
reverse biased diodes.
8 Explain how many poles and zeros are present in the amplifier whose gain 2 C02 L3
magnitude is plotted as a function of frequency in Fig.4.
9 For the circuit in Fig.5, in terms of threshold voltages and overdrive voltages of 2 COl L2
appropriate transistors, express the minimum common mode input voltage for
Vnl or Vn2. Assume all transistors need to be in saturation.
10 Determine the small signal output impedance Vx/lx for the circuit shown in Fig.6. 2
PART- B (5 X 13 = 65 Marks)
Q. No Questions Marks CO BL
ll(a)(i) Sketch the cross sectionDownloaded
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substrate. Under pinchoff or saturation condition, indicate clearly the
depletion regions near the source, near the drain and in the channel
regions. Sketch the electric field under the gate near the source, near the
drain and channel regions.
(ii) For the circuit in Fig.7, sketch Vout as a function of Vin as Vin varies from 4
0 to 3Volts. Assume Vth =0.5Volts.
OR
11(b) (i) Derive the expressions for the output impedance and small signal gain of 4+5 COl L2
the source degenerated common source amplifier shown in Fig.8.
(ii) Sketch Vx as a function of time for the circuit shown in Fig.9. The initial 4
voltage across CI is IV as indicated.
12 (a) (i) For the circuit in Fig.10 draw the symmetric half equivalent circuits for the 2+2 COl L3
small signal differential inputs. Similarly draw the symmetric half +2+
equivalent circuit for common mode inputs. Hence derive the expressions 2
for the small signal differential gain (\/outl-Vout2)/(Vinl -Vin2) and the
small signal single ended common mode gains Vout/{(Vinl+Vin2)/2}. .
(ii) Give the expression for the small differential gain of the circuit shown in 5
Fig.ll.
OR
12(b) (i) Derive the expression for the small signal differential gain of the circuit 9 COl L3
shown in Fig.13
(ii) For the circuit shown in Fig.14, determine the relation between IT and IREF. 2+2
Also determine the ratio (W/L)M8/(W/L)M5.
13 (a) Draw the high frequency equivalent circuit shown in Fig.15 and derive an 3+4 COl L4
expression for the transfer function and also the expressions for its poles +3+
and zeros. 3
OR
13(b) Draw the high frequency equivalent circuit for the circuit shown in Fig.16a. 3+3 COl L4
Derive expressions for its input and output impedances. Show that the +3+
output impedance can be represented by the network shown in FiglBb 4
and determine the expressions of Rl, R2 and L
14 (a) (i) . Determine the expression for the total equivalent input mean square 7 C02 L2
noise voltage spectral density for the circuit shown below Fig.17.
(ii) What are the units of the quantity kT/C and explain how it arises. Briefly 6
state atleast one peculiar conclusion associated with it.
OR
14(b) For the block diagram shown in Fig.18, determine the expressions for 8+/ C02 L2
closed loop gain and output impedance.
15 (a)(i) Explain the terms gain and phase margins associated with feedback 2+2 C02 L2
systems. Explain also the two terms peaking and overshoot. What is the +1+
phase margin for an amplifier that has only one pole in its open loop 1+2
transfer function.
(ii) An amplifier has an open loop gain given by ADC/(1+S/ U) O). If this amplifier 5
is used in a negative feedback loop with a feedback factor 'p', determine
the expressions for the new 3dB cutoff frequency and also the Unity Gain
Bandwidth UGB
OR
15(b) In a two stage amplifier, explain how the dominant and non dominant 5+3 C02 L2
poles get altered due to Miller compensation. With justification, explain +5
whether any penalty is incurred due to Miller compensation. Explain any
one procedure by which the zero in the transfer function can be made
harmless.
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C (1 x 15 = 15 Marks)
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(Q.No.16 is compulsory)
Q. No Questions Marks CO BL
16. (i) What could be approximate expression for the aspect ratio (ratio of 5+5+5 C02 L5
Width to Length) of the equivalent transistor realized by the structure
shown in Fig.19
16 .(ii) Determine the expression for the small signal low frequency differential
gain (Voutl-Vout2)/Vin for the circuit in Fig.20
16. (iii) In the circuit of Fig.21, you have to first determine the short circuit
output current for the given small signal input current !;„. Then determine
the output impedance of the circuit, and finally determine the expression
for the small signal gain (Vo^^/liJ.
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