Materials Science in Semiconductor Processing 142 (2022) 106482

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Materials Science in Semiconductor Processing

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Analytical modeling and TCAD simulation for subthreshold characteristics

of asymmetric Tunnel FET
Jagritee Talukdar a, *, Gopal Rawat b, Kavicharan Mummaneni a
a
Department of Electronics and Communication Engineering, National Institute of Technology, Silchar, Assam, India
b
Department of Electronics and Communication Engineering, National Institute of Technology, Hamirpur, Himachal Pradesh, India

A R T I C L E I N F O A B S T R A C T

Keywords: In this paper, a 2-D analytical model has been developed for asymmetric Tunnel FET known as Non-Uniform
Analytical modeling Body with Dual Material Source TFET (NUTFET-DMS) Device. The proposed model formulation is based on
Poisson’s equation the solution of Poisson’s equation using suitable boundary conditions. The derived model for subthreshold
TFET
characteristics is proposed for numerous device parameters such as surface potential, lateral, vertical electric
Band to band tunneling
Parabolic approximation
fields, drain current and threshold voltage. In this work, for the first time the model accounts the prodigious non-
uniform nature of the Channel, Gate Dielectric Thickness, Dielectric Constants and Oxide Capacitance, at
different portions of the device. Next, to validate the accuracy of the model, device simulation using Sentaurus
TCAD with calibrated models is reported and a close agreement with 85–95% accuracy is observed. The detailed
and systematic device analysis is presented by studying different cases of applied biases, variation of device
dimensions, oxide materials etc. It is reported that the proposed TFET device is able to obtain a vertical and
lateral electric field of ± 5 MV/cm near the tunneling junction, implying a drain current in the order of 10− 5A/
μm. The present study highlights that the proposed TFET offers great potential for low standby power logic and
low power applications.

1. Introduction nanowires with a diamond cubicor zinc blende crystalline structure

[14]. Next, in the year 2012 W.Cho et al. investigated the homo-junction
Tunnel Field effect transistor (TFET) is considered to be the most In0.53Ga0.47 tunneling diode using a tight-binding model and the
promising futuristic device in the era of low power and high scalability Non-Equilibrium Green’s Function [15]. However, this technique is
[1,2]. For current conduction mechanism, TFET uses band to band computationally difficult and needs many approximations [18]. In the
tunneling (BTBT). As this BTBT mechanism is not inhibited by thermal second approach, various equations of device physics are considered and
limit of 60 mV/decade as in the case of MOSFET, thus it allows TFET to modified to obtain the particular device characteristics, thus this
attain lower SS which permits more supply voltage scaling [3,4]. approach is computationally adaptable, and provides a better perceptive
However, TFET provides a lower leakage current, yet its ON current is about the device functional aspect. Therefore, the analytical modeling of
very low, and ambipolar current is also very high [5]. The low ON physical device characteristics such as potential, electric field, threshold
current of conventional TFET is because of the BTBT process and higher voltage, drain current, etc. are in vogue. Some of the recent literature
bandgap of silicon (Si) material. Hence, different modifications and includes the study of the analytical model for stacked gate oxide double
improvements have been achieved on TFET to address these issues and gate TFET by S. Kumar et al. to evade the effect of interface trap charges
set forth in the literature [6–9]. The majority of state-of-the-art studies at high-k silicon interface [17]. Next, P. Pandey et al. extracted a model
of the device are performed using simulation [10–12] nevertheless, in for SOI TFET to determine the drain current by counting the depletion
recent years an increasing interest of researchers towards the modeling regions of source and drain sides [19]. Similarly, D. Keighobadi et al.
of TFET can be noticed. Fundamentally, there are two known ap­ reported a drain current model which includes the carrier concentration
proaches to perform the TFET modeling, namely atomistic modeling of channel and space charge distribution of depletion region [20]. In
[13–15] and analytical modeling [16,17]. Now based on atomistic 2019, S. Mohammadi et al. reported a universal analytical model for DG
modeling technique P. D’Amico et al. investigated BTBT mechanism in heterostructure TFET for both n-type and p-type structures considering

* Corresponding author.
E-mail addresses: [email protected] (J. Talukdar), [email protected] (G. Rawat), [email protected] (K. Mummaneni).

https://doi.org/10.1016/j.mssp.2022.106482
Received 29 July 2021; Received in revised form 23 December 2021; Accepted 10 January 2022
Available online 24 January 2022
1369-8001/© 2022 Elsevier Ltd. All rights reserved.
J. Talukdar et al. Materials Science in Semiconductor Processing 142 (2022) 106482

the impact of mobile charge carriers [21]. Similarly, other papers also Table 1
present a similar universal analytical model for various devices [22–24]. Device simulation parameters.
Therefore, a proper optimization with the help of the mathematical Parameters Values
model can lead to more improvement in the device’s electrical
Si bandgap (Eg1) 1.11 eV
characteristics. Ge Bandgap (Eg2) 0.67 eV
The literature review and present state of the art point out that Source Doping (Ns) 1 × 1020 cm− 3

nanoscale devices are highly capable to further improve the device Drain Doping (ND) 1 × 1017 cm− 3

subthreshold performances [25–27]. Some preliminary simulation study Channel doping (Nch) 1 × 1015 cm− 3

Dielectric constant of HfO2 22

on the Non-Uniform Body TFET with Dual Material Source (NUT­ Dielectric constant of SiO2 3.5
FET-DMS) has recognized that this structure can achieve a high value of Work function of Aluminum 4.2 eV
ON current and low value of leakage and ambipolar current [25]. The Channel thickness, (Tch) 15 nm
use of dual material in the device source makes it capable of maintaining Reduced channel thickness, (Tch-ΔTch) 7 nm
Dielectric thickness of HfO2 (Tox) 0.7 nm
a very low average SS of 22mV/decade [25]. In this regard, to the best of
Dielectric thickness of SiO2 (Tox-ΔTox) 1 nm
our knowledge, analytical model of NUTFET-DMS has not been pro­
posed and examined. Hence, there is a research gap and necessity to
derive electrical characteristics of the complex asymmetrical nanoscale constant, thickness, etc. [25].
device such as NUTFET-DMS.
3. Analytical model formulation
2. Architectural description of NUTFET-DMS
The schematic diagram of the NUTFET-DMS device considered for
The cross-section of the n-type NUTFET-DMS along with doping the present study is illustrated in Fig. 1. In Fig. 1, region-I (R1) and
concentration is shown in Fig. 1. The total length of the structure is 60 region-IV (R4) are the source and drain depletion regions having length
nm. The source is made up of two different materials with different L1 and L4, respectively. The channel region is divided into two regions, i.
bandgaps to improve the average SS of the structure. The presence of Ge e. region-II (R2) and region-III (R3) corresponding to the dissimilar
in the source keeps the SS lower even at higher gate to source voltages thickness of the channel. The origin and reference x and y axis are also
because of its lower bandgap. In addition, the non-uniform body benefits shown in Fig. 1 i.e. along channel length and thickness, respectively.
in maintaining different current components of the structure as Next, the junction potentials are denoted as ∅0, ∅1, ∅2, ∅3, and ∅4 at
explained in Ref. [25]. As shown in Fig. 1, Tch and Tch-ΔTch are channel different channel lengths as presented in Fig. 1. The proposed model
thickness corresponding to different regions of the channel. The formulation started by solving 2-D Poison’s equation in different re­
dielectric materials used near the source is HfO2 and near the drain is gions. Applying boundary conditions ((3)–(6) and (15)–(16)), the
SiO2 with thicknesses of Tox and Tox-ΔTox, respectively. Table 1 presents modeling and simulation of 2-D surface potential, electric fields, drain
the various device parameters such as doping concentration, dielectric current and threshold voltage has been performed.

Fig. 1. (a) Schematic of NUTFET-DMS device structure illustration various regions (b) Contour plot of doping concentration.

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J. Talukdar et al. Materials Science in Semiconductor Processing 142 (2022) 106482

3.1. Model derivation for surface potential ( )

Egj Ni
∅Gj = Vgs − ∅M + χ + + ∅t ln (7)
Let say ∅i (x, y) is 2-D potential distribution function, computed with 2q ni
reference to the fermi potential in the region R1 to R4 for Fig. 1. The Substituting the boundary conditions of (3)-(6) and (7), the co­
analogous 2-D Poisson’s equation [28] is expressed as efficients of (2) are calculated and expressed as following:
( )
∂2 ∅i ∂2 ∅i qNi Co T
+ 2 = (1) c0i (x) = ∅s (x) − ∅G (8)
∂x2 ∂y εi 4εsi

where, i = 1, 2, 3 and 4, Ni represents the doping concentration, and the c1i (x) = 0 (9)
sign is taken as negative for source and positive otherwise, εi is the
permittivity of each region Ri (i = 1, 2, 3, 4). Co (∅G − ∅s (x))
c2i (x) = (10)
The Parabolic approximation has been assumed for the solution of T εsi
the potential distribution function for the aforementioned Poisson’s
Placing the above expressions of (8)-(10) in (1) the 2-D potential
equation is given as following [28]:
distribution function can be obtained in 1-D form as given below:
∅i (x, y) = C0i (x) + C1i (x)y + C2i (x)y2 (2)
∂2 ∅si (x)
− β2i ∅si (x) = β2i ∅vi (11)
where, C0i, C1i, C2i are the coefficients, considered to be the arbitrary ∂2 x
functions of x. The value of these coefficients can be calculated using the ( )0.5 ( )
following boundary conditions (assume y = 0 at the centre of the Where, βi = 2Cox/T ε
/
and ∅vi = qNi β2 ε − ∅G . The parame­
si si
channel). i

⃒ ters βi and ∅vi sign up different values for different regions (R1-R4) of the
∂∅i (x, y)⃒⃒ device due to the variation of doping concentrations, thickness and
= 0 = ξx (x, 0 ) (3)
∂y ⃒y=0 oxide capacitances.
⃒ ( ) The general solution of (11) is applicable to all the regions of the
∂∅i (x, y)⃒⃒ Cox (∅G − ∅s (x)) T device structure (R1-R4) and it can be expressed as follows:
= ± = ξx x, ± (4)
∂y ⃒y=±T2 εsi 2
∅si (x) = Ai exp(βi xi ) + Bi exp(− βi xi ) − ∅vi (12)
( )
∅i x, ±
T
= ∅f (b)i (x) (5) The value of ∅s at the left and right edge of R1 and R4 can be
2 expressed as:
( )
∅f (x) = ∅b (x) = ∅s (x) (6) ∅s0 = − ∅t ln
Ns
(13)
ni
where, ∅f (x) and ∅b (x) signifies the surface potentials under the influ­ ( )
ence of front and back gate bias, respectively. For regions I and II, ∅s4 = VD + ∅t ln
ND
(14)
various parameters are denoted as channel thickness T = Tch , Dielectric ni
constant εo = εox , oxide capacitance C = Cox , and oxide thickness While, the expressions for the coefficients Ai and Bi can be calculated
To = Tox . Similarly, for region III and IV, channel thickness T = Tch − using the following boundary conditions in the x-direction, which
ΔTch , Dielectric constant εo = εox − Δεox , oxide capacitance C = Cox − reimburse the continuity of surface potential and electric field in all the
ΔCox , and oxide thickness To = Tox + ΔTox . For the depletion regions R1 regions.
and R4, fringing field effect has been appended, hence in these regions,
Cox and Cox − ΔCox have been replaced by (2/π)Cox and (2/π) Cox − ∅si (x)|x=xi = ∅s(i+1) (x)|x=xi (15)
ΔCox , respectively [29]. In addition, ∅G is the effective gate voltage ⃒ ⃒
which is found less than the applied gate bias (Vgs), where Egj = ∂∅si (x)⃒⃒
=
∂∅s(i+1) (x)⃒⃒
(16)
EgSilicon, EgGermenium and is given by: ∂x ⃒x=xi ∂x ⃒
x=xi

Fig. 2. Surface Potential across the channel for variation of (a) Drain to Source voltage (Vds) (b) Gate to Source voltage (Vgs).

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J. Talukdar et al. Materials Science in Semiconductor Processing 142 (2022) 106482

The calculation of lengths of depletion region at source and drain ⎧ √̅̅̅̅̅̅̅̅̅⎫

includes the influence of effective potential ∅v . As the source is made of ∫1 √̅̅̅̅ ⎨− π mE3g ⎬
E2.5 m
two materials, the calculation of L1 considers the average of bandgaps. Id = q √ ̅̅̅̅̅̅ exp dV (29)
18πħ2 Egj ⎩ 2ħ|E| ⎭
√̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅ Tunneling
2ε1 (∅v1 − ∅s0 )
L1 = (17) volume
qN1
√̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅ Where, m is the effective mass, Eg is the bandgap energy, ħ Plank’s
⃒√⃒̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅
⃒ ⃒
L4 =
2ε3 (∅s4 − ∅v3 )
(18) constant, the average electric field is |E| = ⃒ ξ2xi + ξ2yi ⃒, ξxi and ξyi are
qN4
lateral and vertical electric fields of different regions (R1-R4),
Now the simultaneous solutions of surface potential in different re­ respectively.
gions (R1-R4) can be obtained from the above equations (15)–(18) by
finding out Ai and Bi in different regions as given below:
3.4. Model derivation for threshold voltage
A1 = A4 X5 + B4 X6 − 2Z2 (19)
The threshold voltage (Vth) has been derived based on the constant
B1 = A4 Y5 + B4 Y6 − 2Z4 (20) current method [31]. As the drain current of TFET directly dependent on
BTBT, which is further dependent on the minimum tunneling length of
the source-channel junction. For the NUTFET-DMS, the minimum
tunneling length near Vgs ~ Vth occurs at region-II (R2). Therefore, the

A2 = A4 [X7 (β3 − β4 )exp(β4 L3 ) + X8 (β3 + β4 )exp(β4 L3 )] + B4 [X7 (β3 + β4 )exp(− β4 L3 ) + X8 (β3 − β4 )exp(− β4 L3 )] (21)

B2 = A4 [Y7 (β3 + β4 )exp(β4 L3 ) + Y8 (β3 − β4 )exp(β4 L3 )] + B4 [Y7 (β3 − β4 )exp(− β4 L3 ) + Y8 (β3 + β4 )exp(− β4 L3 )] (22)

1
A3 = [A4 (β3 + β4 )exp(β4 L3 ) + B4 (β3 − β4 )exp(− β4 L3 ) − β3 (∅v4 − ∅v3 )] (23)
2β3 exp(β3 L3 )

1
B3 = [A4 (β3 − β4 )exp(β4 L3 ) + B4 (β3 + β4 )exp(− β4 L3 ) − β3 (∅v4 − ∅v3 )] (24)
2β3 exp(− β3 L3 )

minimum tunneling length has been calculated from the potential pro­
Eg
P2 (X6 + Y6 ) − P1 exp(− β4 L4 ) file of R2, where the potential is greater than from the source potential.
A4 = (25) q
(X6 + Y6 )exp(β4 L4 ) − (X5 + Y5 )exp(− β4 L4 ) Hence, the minimum tunneling length satisfies the following set of
conditions.
P2 (X5 + Y5 ) − P1 exp(β4 L4 )
B4 = (26) ∅s2 (Lt− exp(β2 Lt− exp( − β2 Lt− (30)
(X5 + Y5 )exp(− β4 L4 ) − (X6 + Y6 )exp(β4 L4 ) min ) = A2 min ) + B2 min ) − ∅v2

Where, the variables X1 , Y1 , Z1 , P1 to X7 , Y7 , Z4, P2 are expressed in ∅s2 (Lt− min ) = ∅s0 +
Egj
(31)
terms of effective potentials ∅vi , lengths (Li ), and constant (βi ). q
Finally, threshold voltage can be determined by substituting the
3.2. Model derivation for lateral and vertical electric field values of A2 B2 , ∅v2 which are functions of Vgs and considering Lt− min
corresponding to the Id value of 10− 8 A/μm.
The electric field of the device in several regions (Ri) can be achieved
by taking the derivative of the analytical expression (12). Thus, the 4. Results and discussion
lateral electric field for various regions can be estimated as.
ξxi = − βi {Ai exp(βi xi ) − Bi exp(− βi xi )} (27) In order to appraise the precision of formulated models in section-III,
the present section brings a comparison between the results of TCAD
Similarly, the vertical electric field for various regions is calculated simulation and the proposed model. Various electrical characteristics
and expressed by the following equation: including surface potential, electric field, drain current and threshold
ξyi = − 2yC2i (x) (28) voltage are compared and analyzed. The models such as Non-Local Band
to Band Tunneling model, Shockley-Read-Hall (SRH) recombination
3.3. Model derivation for drain current model, Band Gap Narrowing model are used in the Sentaurus TCAD device
simulator and calibrated accurately [32].
The drain current obtained in the Non-uniform TFET with dual ma­
terial source is due to the presence of BTBT. Using the model of band to 4.1. Analysis of surface potential
band generation rate of the carriers over the tunneling volume from
valence band to conduction band of source and channel respectively, the Fig. 2 denotes the comparative results of TCAD simulation and
drain current can be calculated as follows [30]. mathematical model of surface potential as a function of lateral distance.
Fig. 2 (a) and Fig. 2 (b) study the surface potential profile for the vari­
ation of drain to source voltage (Vds) and gate to source voltage (Vgs),
respectively. It is noted from Fig. 2 (a) that, with the increase in Vds from
0.5 V to 0.9 V, the channel surface potential increases, but as Vds

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J. Talukdar et al. Materials Science in Semiconductor Processing 142 (2022) 106482

Fig. 3. Vertical (ξy ) and lateral (ξx ) electric field across the channel for variation of (a) Gate to Source voltage (Vgs) (b) Dielectric Materials.

approaches Vgs it loses control over the channel because of higher by Vgs, hence increase in Vds and Vgs will lead to an increase in both the
depletion region of channel-drain region. Similarly, it is perceived from electric fields, which further leads to the higher current in the device.
Fig. 2 (b) that, with increase in Vgs from 0.5 V to 1.5 V, the channel Similar analysis is observed in Fig. 3 (b) for the various dielectric ma­
surface potential increases with sharp change of surface potential at terials such as HfO2, SiO2, HfO2-SiO2 and SiO2-HfO2. Different dielectric
source-channel junction. It is attributed to the tunneling in the region materials are available with different dielectric constants, for example
and in between the channel also where the thickness of the channel SiO2 (εr = 3.9), Si3N4 (εr = 7.0), Al2O3 (εr = 9), HfSiO4 (εr = 11), Y2O3
changes [33]. Lastly, it can be inferred that surface potential profile of (εr = 16), HfO2 (εr = 25) and etc. [34–36]. Specifically, we have
simulation and proposed model closely matches and are in good considered SiO2 and HfO2 due to the large variation of the dielectric
agreement. constant. Notably, these results are in good agreement with the previ­
ously reported results [17,37]. It can be observed that in case of
HfO2-SiO2 when the gate dielectric near the source is topped with a
4.2. Analysis of lateral and vertical electric field high-k dielectric and near drain by a low-k dielectric, the values of Ey
and Ex are approximately ±5MV/cm which is much better as compared
The lateral and vertical electric fields of the presented device are to the existing results in Refs. [32,33], implying a higher ON current of
illustrated in Fig. 3. Fig. 3 (a) and Fig. 3 (b) show the comparison of the device. It can be observed that an asymmetric dielectric combination
lateral and vertical electric fields along the length of the channel for provides higher vertical as well as lateral electric fields, which has been
variation of Vgs and oxide materials, respectively. Fig. 3 (a) shows the validated by derived analytical model.
variation of both lateral and vertical electric fields with the variation of
Vgs from 0.5 V to 1.5 V. It is observed that a sharp change in electric field
occurs in the source-channel junction, which is due to the BTBT process. 4.3. Analysis of drain current
Towards the channel, different fluctuations occur in Ex and Ey because of
the non-uniformity of the structure. The lateral electric field in the de­ Fig. 4 represents the characteristics of drain current vs. gate to source
vice is mainly caused by the application of Vds and vertical electric field voltage (Vgs) for varying drain to source voltages (Vds) and dielectric

Fig. 4. Drain current characteristics (Id) vs. Gate to source voltage (Vgs) for variation of (a) drain to source voltage (Vds) (b) Dielectric materials.

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J. Talukdar et al. Materials Science in Semiconductor Processing 142 (2022) 106482

Fig. 5. TCAD simulation revealing the contour maps of the electron density (a) HfO2-SiO2 (b) HfO2 (c) SiO2 (d) SiO2-HfO2.

materials. From Fig. 4(a) it can be perceived that, with the increase in junction prompting higher ON current as compared to the case of low-k
Vds the ON current increases which is due the fact that as long as the Vds dielectric (SiO2) on the source side (Fig. 5(c) and (d)) [38]. The derived
< Vgs the channel and drain potential are pinned and there is an absence model calculates the drain current for different dielectric materials at
of depletion region at the channel-drain junction as a result channel different locations. However, the presence of different dielectric mate­
potential is regulated by Vds only. Hereby as Vds is enhanced, energy rials near the drain also affects the ambipolar current of the device as
bands of both channel and drain get dropped, allowing more tunneling explained in Ref. [25].
from source to channel conducting more drain current. From Fig. 4(a) it
can be noticed that, as the value of Vds approaches Vgs (Vds ~ Vgs = 0.9
4.4. Analysis of threshold voltage
V) the increase in drain current is significantly reduced because of
reduced control of the Vds over channel potential due to the origination
Fig. 6 presents the variation of threshold voltage (Vth) of the device
of depletion region at the channel-drain junction. But, mostly Vds affects
as a function of channel length. It can be observed that Vth of the device
the ambipolar current of the device because as Vds and the bandgap
decreases with decreasing channel length, however, for very small
value reaches each other, OFF state tunneling becomes prominent [36],
channel length, it increases slightly. It is observed that the threshold
However, this part of the study is not included in the model.
voltage decreases for high-k dielectric near source-channel junction
Fig. 4(b) denotes that, when the gate dielectric is made up of entirely
because of higher influence to lower the energy bands which reduces the
SiO2 and SiO2-HfO2, the ON current is very low, in other cases higher ON
tunneling length [39]. It can be perceived from Fig. 4 that the modeled
current can be observed. From Fig. 5(a) and Fig. 5(b) it can be inferred
valued of threshold voltage shows a close match with the simulated
that High-k dielectric (HfO2) on the source side causes higher electro­
threshold voltage at drain current of 10− 8 A/μm.
static coupling leading to higher e-density at the source-channel
Focusing on low power application, the preliminary study [25]
showed that the device provides an ON current, OFF current, point, and
avg. SS in the order of 10− 5 A/μm, 10− 16 A/μm, 9 mV/decade, and
22mV/decade, respectively, which is found to be better than other
compared structures [12,40–42]. In addition, Table 2 compares ON, OFF
current and threshold voltage of the device with reported literature and
it can be noted that NUTFET-DMS provides superior device perfor­
mance. It can be concluded that the NUTFET-DMS provides improved
subthreshold parameters, and the proposed model is capable to follow
the asymmetric changes of dimension and other material parameters.
Finally, it is inferred from the above result and discussion that a close
match prevails between the proposed model and simulation results.

Table 2
Comparison of ON (ION), OFF (IOFF) current and threshold voltage (Vth) with
other existing TFET structures.
Device Structures ION (A/ IOFF (A/ Vth
μm) μm) (V)

NUTFET-DMS (This work) ~10–5 ~10–16 ~0.3

Double-Gate p-n-p-n TFET [31] ~10–6 ~10–16 ~0.5
Vertical Tunnel FET [43] ~10–5 ~10–15 ~0.5
Nano-scale SOI-TFET [44] ~10–6 ~10–17 ~1.2
SOI-TFET [19] ~10–5 ~10–11 –
Cylindrical Channel GAA Heterojunction ~10–6 ~10–18 ~0.6
Fig. 6. Threshold Voltage (Vth) vs. Channel Length (L) for different combina­
TFET [20]
tions of dielectric materials.

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