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SECTION 13-2/FUNDAMENTALS OF PLD CIRCUITRY 875

many equivalent gates will be needed for a large design? The basic design of
the signal routing resources can affect how much of the PLD’s logic resources
can be utilized. The segmented interconnects often found in FPGAs can pro-
duce shorter delays between adjacent logic blocks, but they may also produce
longer delays between the blocks that are further apart than would be pro-
duced by the continuous type of interconnect found in most CPLDs. There is
no easy answer to your question, but every HCPLD manufacturer will give
you an answer anyway: their product is best!
As you can see, the field of PLDs is quite diverse and it is constantly chang-
ing. You should now have the basic knowledge of the various types and tech-
nologies necessary to interpret PLD data sheets and learn more about them.

REVIEW QUESTIONS 1. What are the three major categories of digital systems?
2. What is the major disadvantage of a microprocessor/DSP design?
3. What does ASIC stand for?
4. What are the four types of ASICs?
5. What are HCPLDs?
6. What are two major differences between CPLDs and FPGAs?
7. What does volatility refer to?

13-2 FUNDAMENTALS OF PLD CIRCUITRY

A simple PLD device is shown in Figure 13-3. Each of the four OR gates can
produce an output that is a function of the two input variables, A and B. Each
output function is programmed with the fuses located between the AND
gates and each of the OR gates.

FIGURE 13-3 Example of A B

a programmable logic
device.

A A B B AND array

AB AB

AB AB

Product
lines
AB AB

AB AB

Fuses 1 4

Input lines OR
1 2 3 4
array
O1 O2 O3 O4

Sum of product outputs

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876 CHAPTER 13/PROGRAMMABLE LOGIC DEVICE ARCHITECTURES

Each of the inputs A and B feed both a noninverting buffer and an in-
verting buffer to produce the true and inverted forms of each variable. These
are the input lines to the AND gate array. Each AND gate is connected to two
different input lines to generate a unique product of the input variables. The
AND outputs are called the product lines.
Each of the product lines is connected to one of the four inputs of each
OR gate through a fusible link. With all of the links initially intact, each OR
output will be a constant 1. Here’s the proof:

O1 = A B + A B + AB + AB
= A(B + B) + A(B + B)
= A + A = 1

Each of the four outputs O1, O2, O3, and O4 can be programmed to be any func-
tion of A and B by selectively blowing the appropriate fuses. PLDs are
designed so that a blown OR input acts as a logic 0. For example, if we blow
fuses 1 and 4 at OR gate 1, the O1 output becomes

O1 = 0 + A B + AB + 0 = A B + AB

We can program each of the OR outputs to any desired function in a sim-

ilar manner. Once all of the outputs have been programmed, the device will
permanently generate the selected output functions.

PLD Symbology
The example in Figure 13-3 has only two input variables and the circuit dia-
gram is already quite cluttered. You can imagine how messy the diagram
would be for PLDs with many more inputs. For this reason, PLD manufac-
turers have adopted a simplified symbolic representation of the internal cir-
cuitry of these devices.
Figure 13-4 shows the same PLD circuit as Figure 13-3 using the simpli-
fied symbols. First, notice that the input buffers are represented as a single
buffer with two outputs, one inverted and one noninverted. Next, note that a
single line is shown going into the AND gate to represent all four inputs. Each
time the row line crosses a column represents a separate input to the AND
gate. The connections from the input variable lines to the AND gate inputs
are indicated as dots. A dot means that this connection to the AND gate in-
put is hard-wired (i.e., one that cannot be changed). At first glance, it looks
like the input variables are connected to each other. It is important to real-
ize that this is not the case because the single row line represents multiple
inputs to the AND gate.
The inputs to each of the OR gates are also designated by a single line
representing all four inputs. An X represents an intact fuse connecting a
product line to one input of the OR gate. The absence of an X (or a dot) at
any intersection represents a blown fuse. For OR gate inputs, blown fuses
(unconnected inputs) are assumed to be LOW, and for AND gate inputs,
blown fuses are HIGH. In this example, the outputs are programmed as

O1 = A B + AB
O2 = AB
O3 = 0
O4 = 1
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SECTION 13-3/PLD ARCHITECTURES 877

FIGURE 13-4 Simplified A B

PLD symbology.

Intact Blown
A A B B fuse fuse
AB
AB

AB
AB

AB
AB

AB
AB

Hard-wired
connection
No
connection
O1 O2 O3 O4

REVIEW QUESTIONS 1. What is a PLD?

2. What would output O1 be in Figure 13-3 if fuses 1 and 2 were blown?
3. What does an X represent on a PLD diagram?
4. What does a dot represent on a PLD diagram?

13-3 PLD ARCHITECTURES

The concept of PLDs has led to many different architectural designs of the
inner circuitry of these devices. In this section, we will explore some of the
basic differences in architecture.

PROMs
The architecture of the programmable circuits in the previous section in-
volves programming the connections to the OR gate. The AND gates are
used to decode all the possible combinations of the input variables, as
shown in Figure 13-5(a). For any given input combination, the correspon-
ding row is activated (goes HIGH). If the OR input is connected to that
row, a HIGH appears at the OR output. If the input is not connected, a
LOW appears at the OR output. Does this sound familiar? Refer back to
Figure 12-9. If you think of the input variables as address inputs and the
intact/blown fuses as stored 1s and 0s, you should recognize the architec-
ture of a PROM.
Figure 13-5(b) shows how the PROM would be programmed to generate four
specified logic functions. Let’s follow the procedure for output O3 = AB + C D.
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878 CHAPTER 13/PROGRAMMABLE LOGIC DEVICE ARCHITECTURES

Inputs

D C B A OR array D C B A
(programmable)

0 0 DCBA

1 1 DCBA

2 2 DCBA

3 3 DCBA

4 4 DCBA

5 5 DCBA

6 6 DCBA

7 7 DCBA

8 8 DCBA

9 9 DCBA

10 10 DCBA

11 11 DCBA

12 12 DCBA

13 13 DCBA

14 14 DCBA

15 15 DCBA

3 2 1 0 3 2 1 0 Fuse
AND array O3 = AB + CD; O2 = ABC Blown left
(hard-wired) O1 = ABCD + ABCD; fuse intact
O3 O2 O1 O0 O0 = A + BD + CD O3 O2 O1 O0
All fuses
intact Outputs

(a) (b)
FIGURE 13-5 (a) PROM architecture makes it suitable for PLDs; (b) fuses are
blown to program outputs for given functions.

The first step is to construct a truth table showing the desired O3 output level
for all possible input combinations (Table 13-1).
Next, write down the AND products for those cases where the output is to
be a 1.The O3 output is to be the OR sum of these products.Thus, only the fuses
that connect these product terms to the inputs of OR gate 3 are to be left intact.
All others are to be blown, as indicated in Figure 13-5(b). This same procedure
is followed to determine the status of the fuses at the other OR gate inputs.
The PROM can generate any possible logic function of the input vari-
ables because it generates every possible AND product term. In general, any
application that requires every input combination to be available is a good
candidate for a PROM. However, PROMs become impractical when a large
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SECTION 13-3/PLD ARCHITECTURES 879

TABLE 13-1
D C B A O3

0 0 0 0 1 → DCBA
0 0 0 1 1 → DCBA
0 0 1 0 1 → D C BA
0 0 1 1 1 → D C BA
0 1 0 0 0
0 1 0 1 0
0 1 1 0 0
0 1 1 1 1 → D CBA
1 0 0 0 0
1 0 0 1 0
1 0 1 0 0
1 0 1 1 1 → DC BA
1 1 0 0 0
1 1 0 1 0
1 1 1 0 0
1 1 1 1 1 → DCBA

number of input variables must be accommodated because the number of

fuses doubles for each added input variable.
Calling a PROM a PLD is really just a semantics issue. You already knew
that a PROM is programmable and it is a logic device. This is just a way of us-
ing a PROM and thinking of its purpose as implementing SOP logic expres-
sions rather than storing data values in memory locations. The real problem is
translating the logic equations into the fuse map for a given PROM. A general-
purpose logic compiler designed to program SPLDs has a list of PROM de-
vices that it can support. If you choose to use any old scavenged EPROM as
a PLD, you may need to generate your own bit map (like they used to do it),
which is very tedious.

Programmable Array Logic (PAL)

The PROM architecture is well suited for those applications where every pos-
sible input combination is required to generate the output functions. Examples
are code converters and data storage (look-up) tables that we examined in
Chapter 12. When implementing SOP expressions, however, they do not make
very efficient use of circuitry. Each combination of address inputs must be
fully decoded, and each expanded product term has an associated fuse that is
used to OR them together. For example, notice how many fuses were required
in Figure 13-5 to program the simple SOP expressions and how many product
terms are often not used. This has led to the development of a class of PLDs
called programmable array logic (PAL). The architecture of a PAL differs
slightly from that of a PROM, as shown in Figure 13-6(a).
The PAL has an AND and OR structure similar to a PROM but in the
PAL, inputs to the AND gates are programmable, whereas the inputs to the
OR gates are hard-wired. This means that every AND gate can be pro-
grammed to generate any desired product of the four input variables and
their complements. Each OR gate is hard-wired to only four AND outputs.
This limits each output function to four product terms. If a function requires
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880 CHAPTER 13/PROGRAMMABLE LOGIC DEVICE ARCHITECTURES

D C B A OR array D C B A
(hard-wired)

1 1 AB

2 2 CD

3 3 0

4 4 0

5 5 ABC

6 6 0

7 7 0

8 8 0

9 9 ABCD

10 10 ABCD

11 11 0

12 12 0

13 13 A

14 14 BD

15 15 CD

16 16 0

3 2 1 0 3 2 1 0
AND array O3 = AB + CD; O2 = ABC
(programmable) O1 = ABCD + ABCD;
O3 O2 O1 O0 O0 = A + BD + CD O3 O2 O1 O0

(a) Outputs (b)

FIGURE 13-6 (a) Typical PAL architecture; (b) the same PAL programmed for the
given functions.

more than four product terms, it cannot be implemented with this PAL; one
having more OR inputs would have to be used. If fewer than four product
terms are required, the unneeded ones can be made 0.
Figure 13-6(b) shows how this PAL is programmed to generate four spec-
ified logic functions. Let’s follow the procedure for output O3 = AB + C D.
First, we must express this output as the OR sum of four terms because the
OR gates have four inputs. We do this by putting in 0s. Thus, we have

O3 = AB + C D + 0 + 0

Next, we must determine how to program the inputs to AND gates 1, 2, 3, and
4 so that they provide the correct product terms to OR gate 3. We do this term
by term. The first term, AB, is obtained by leaving intact the fuses that con-
nect inputs A and B to AND gate 1 and by blowing all other fuses on that line.
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SECTION 13-4/THE GAL 16V8 (GENERIC ARRAY LOGIC) 881

Likewise, the second term, C D, is obtained by leaving intact only the fuses
that connect inputs C and D to AND gate 2. The third term is a 0. A constant
0 is produced at the output of AND gate 3 by leaving all of its input fuses in-
tact. This would produce an output of AABBCCDD, which, as we know, is 0. The
fourth term is also 0, so the input fuses to AND gate 4 are also left intact.
The inputs to the other AND gates are programmed similarly to generate
the other output functions. Note especially that many of the AND gates have
all of their input fuses intact because they need to generate 0s.
An example of an actual PAL integrated circuit is the PAL16L8, which
has 10 logic inputs and eight output functions. Each output OR gate is hard-
wired to seven AND gate outputs, and so it can generate functions that in-
clude up to seven terms. An added feature of this particular PAL is that six
of the eight outputs are fed back into the AND array, where they can be con-
nected as inputs to any AND gate. This makes it very useful in generating all
sorts of combinational logic.
The PAL family also contains devices with variations of the basic SOP cir-
cuitry we have described. For example, most PAL devices have a tristate buffer
driving the output pin. Others channel the SOP logic circuit to a D FF input and
use one of the pins as a clock input to clock all of the output flip-flops synchro-
nously. These devices are referred to as registered PLDs because the outputs
pass through a register. An example is the PAL16R8, which has up to eight reg-
istered outputs (which can also serve as inputs) plus eight dedicated inputs.

Field Programmable Logic Array (FPLA)

The field programmable logic array (FPLA) was developed in the mid-1970s
as the first nonmemory programmable logic device. It used a programmable
AND array as well as a programmable OR array. Although the FPLA is more
flexible than the PAL architecture, it has not been as widely accepted by en-
gineers. FPLAs are used mostly in state-machine design where a large num-
ber of product terms are needed in each SOP expression.

REVIEW QUESTIONS 1. Verify that the correct fuses are blown for the O2, O1, and O0 functions in
Figure 13-5(b).
2. A PAL has a hard-wired _____ array and a programmable _____ array.
3. A PROM has a hard-wired _____ array and a programmable _____ array.
4. How would the equation for the output of O1 in Figure 13-5(b) change if
all the fuses from AND gate 14 were left intact?

13-4 THE GAL 16V8 (GENERIC ARRAY LOGIC)

The GAL 16V8, introduced by Lattice Semiconductor, has an architecture
that is very similar to the PAL devices described in the previous section.
Standard, low-density PALs are one-time programmable. The GAL chip, on
the other hand, uses an EEPROM array (located at row and column intersec-
tions in Figure 13-7) to control the programmable connections to the AND
matrix, allowing them to be erased and reprogrammed at least 100 times. In
addition to the AND and OR gates used to produce the sum of product func-
tions, the GAL 16V8 contains optional flip-flops for register and counter
applications, tristate buffers for the outputs, and control multiplexers used