1.
DEECODER
DESIGNER:-
-- Simple OR gate design
library IEEE;
use IEEE.std_logic_1164.all;
entity yo_gate is
port(
a: in std_logic;
b: in std_logic;
c: in std_logic;
d0: out std_logic;
d1: out std_logic;
d2: out std_logic;
d3: out std_logic;
d4: out std_logic;
d5: out std_logic;
d6: out std_logic;
d7: out std_logic);
end yo_gate;
architecture rtl of yo_gate is
begin
process(a, b) is
begin
d0 <= (not a ) and (not b) and (not c);
d1 <= (not a ) and (not b) and ( c);
d2 <= (not a ) and ( b) and (not c);
d3 <= (not a ) and ( b) and ( c);
d4 <= ( a ) and (not b) and (not c);
d5 <= ( a ) and (not b) and ( c);
d6 <= ( a ) and ( b) and (not c);
d7 <= ( a ) and ( b) and ( c);
end process;
end rtl;
TESTBENCH:-
-- Testbench for YO gate
library IEEE;
use IEEE.std_logic_1164.all;
entity testbench is
-- empty
end testbench;
architecture tb of testbench is
-- DUT component
component yo_gate is
port(
a: in std_logic;
b: in std_logic;
c: in std_logic;
d0: out std_logic;
d1: out std_logic;
d2: out std_logic;
d3: out std_logic;
d4: out std_logic;
d5: out std_logic;
d6: out std_logic;
d7: out std_logic);
end component;
signal a_in, b_in, c_in,d0_out,d1_out,d2_out,d3_out,d4_out,d5_out,d6_out,d7_out:
std_logic;
begin
-- Connect DUT
DUT: yo_gate port map(a_in, b_in,
c_in,d0_out,d1_out,d2_out,d3_out,d4_out,d5_out,d6_out,d7_out);
process
begin
a_in <= '0';
b_in <= '0';
c_in <= '0';
wait for 1 ns;
assert(d0_out='0') report "Fail 0/0/0" severity error;
a_in <= '0';
b_in <= '0';
c_in <= '1';
wait for 1 ns;
assert(d1_out='1') report "Fail 0/0/1" severity error;
a_in <= '0';
b_in <= '1';
c_in <= '0';
wait for 1 ns;
assert(d2_out='1') report "Fail 0/1/0" severity error;
a_in <= '0';
b_in <= '1';
c_in <= '1';
wait for 1 ns;
assert(d3_out='1') report "Fail 0/1/1" severity error;
a_in <= '1';
b_in <= '0';
c_in <= '0';
wait for 1 ns;
assert(d4_out='1') report "Fail 1/0/0" severity error;
a_in <= '1';
b_in <= '0';
c_in <= '1';
wait for 1 ns;
assert(d5_out='1') report "Fail 1/0/1" severity error;
a_in <= '1';
b_in <= '1';
c_in <= '0';
wait for 1 ns;
assert(d6_out='1') report "Fail 1/1/0" severity error;
a_in <= '1';
b_in <= '1';
c_in <= '1';
wait for 1 ns;
assert(d7_out='1') report "Fail 1/1/1" severity error;
-- Clear inputs
a_in <= '0';
b_in <= '0';
c_in <= '0';
assert false report "Test done." severity note;
wait;
end process;
end tb;
OUTPUT:-
2.ENCODER
DESIGNER:-
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity encoder is
port(
a : in STD_LOGIC_VECTOR(7 downto 0);
b : out STD_LOGIC_VECTOR(2 downto 0)
);
end encoder;
architecture bhv of encoder is
begin
process(a)
begin
case a is
when "00000001" => b <= "000";
when "00000010" => b <= "001";
when "00000100" => b <= "010";
when "00001000" => b <= "011";
when "00010000" => b <= "100";
when "00100000" => b <= "101";
when "01000000" => b <= "110";
when "10000000" => b <= "111";
when others => b <= "ZZZ";
end case;
end process;
end bhv;
TESTBENCH:-
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY tb_encoder IS
END tb_encoder;
ARCHITECTURE behavior OF tb_encoder IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT encoder
PORT(
a : IN std_logic_vector(7 downto 0);
b : OUT std_logic_vector(2 downto 0)
);
END COMPONENT;
--Inputs
signal a : std_logic_vector(7 downto 0) := (others => '0');
--Outputs
signal b : std_logic_vector(2 downto 0);
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: encoder PORT MAP (
a => a,
b => b
);
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 100 ns;
a <= "00000001";
wait for 100 ns;
a <= "00000010";
wait for 100 ns;
a <= "00000100";
wait for 100 ns;
a <= "00001000";
wait for 100 ns;
a <= "00010000";
wait for 100 ns;
a <= "00100000";
wait for 100 ns;
a <= "01000000";
wait for 100 ns;
a <= "10000000";
wait;
end process;
END;
OUTPUT:-
