Grand Viva

(2024)

Bishwajit Prasad Gond

222CS3113
Master of Technology
222cs3113@[Link]

May 2, 2025
Contents
1 Grand Viva 2024 1
1.1 What is tree data structure? . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.2 How to store elements of a tree in an array? . . . . . . . . . . . . . . . . . . . 1
1.3 Types of tree data structures? . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.4 Why is a tree a non-linear data structure? . . . . . . . . . . . . . . . . . . . . . 1
1.5 What is the syntax of a copy constructor? . . . . . . . . . . . . . . . . . . . . 1
1.6 What is a destructor? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.7 Given the postorder of a Binary Search Tree (BST), how would you design the
BST? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.8 Explain Different Types of Process Models . . . . . . . . . . . . . . . . . . . . 1
1.9 MTech Project . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.10 Smoke Testing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.11 Stubs and Drivers and Their Real-time Examples . . . . . . . . . . . . . . . . 1
1.12 If You Developed an OS, How Would You Test It? . . . . . . . . . . . . . . . . 1
1.13 Computer Networking Basic Questions . . . . . . . . . . . . . . . . . . . . . . 1
1.13.1 Based on Port Numbers, Protocols, and Flow Control Mechanisms . . . 1
1.14 Difference Between V-Model and Iterative Waterfall Model . . . . . . . . . . . 2
1.15 What is Agile Model and its Types? . . . . . . . . . . . . . . . . . . . . . . . 2

2 Operating Systems (OS) 2

2.1 What is PCB? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
2.2 Difference between Process and Thread . . . . . . . . . . . . . . . . . . . . . 2

3 Data Structures 2
3.1 Tell me some Data Structures you used? . . . . . . . . . . . . . . . . . . . . . 2
3.2 Implement a Stack . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
3.3 What is Linear and Non-linear Data Structure? . . . . . . . . . . . . . . . . . . 2
3.4 Why is a tree a Non-linear Data Structure? . . . . . . . . . . . . . . . . . . . . 2
3.5 Declare a Linked List from Scratch . . . . . . . . . . . . . . . . . . . . . . . . 2
3.6 Write a Program to Reverse Your Name . . . . . . . . . . . . . . . . . . . . . 2

4 Machine Learning 2
4.1 Confusion Matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
4.2 Formulas for Evaluation Metrics . . . . . . . . . . . . . . . . . . . . . . . . . 3
4.2.1 Matthews Correlation Coefficient (MCC): . . . . . . . . . . . . . . . . 3
4.2.2 Area Under the Curve (AUC): . . . . . . . . . . . . . . . . . . . . . . 4
4.2.3 Cohen’s Kappa Coefficient (CKC): . . . . . . . . . . . . . . . . . . . . 4
4.2.4 Accuracy: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
4.2.5 F1 Score: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
4.2.6 Recall (Sensitivity or True Positive Rate): . . . . . . . . . . . . . . . . 4
4.2.7 Precision (Positive Predictive Value): . . . . . . . . . . . . . . . . . . 4
4.2.8 Specificity (True Negative Rate): . . . . . . . . . . . . . . . . . . . . . 5
4.2.9 Balanced Accuracy: . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
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5 Matrix Multiplication 5
5.1 Solvay-Strassen Algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

6 SDLC Models 7
6.1 Waterfall Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
6.2 Agile Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
6.3 Scrum Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
6.4 DevOps Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

7 MVC (Model-View-Controller) Model 8

8 Microservices Architecture 9

9 Driver Model 9

10 Architectural Pattern vs Architectural Design 10

11 Difference between Stub and Driver 10

12 Relationship with Testing Strategies 10

13 OSI model and TCP/IP 11

14 Testing 11
14.1 Smoke Testing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
14.2 Regression Testing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
14.3 Equivalence Class Partitioning . . . . . . . . . . . . . . . . . . . . . . . . . . 11
14.4 Boundary Value Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

15 BTech Viva Questions 12

16 DBMS 12

17 Machine Learning 12
17.1 Hard and Soft Margin SVM . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
17.2 Lasso regression . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

18 Testing 13
18.1 How can you connect two computers physically, if I give you a wire, how will
you connect these two PCs? . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
18.2 Do you know optical fibre, have you seen it, what happens there, why do we use
it? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
18.3 RAM, ROM, EPROM, why do we use secondary memory, when something is
stored in a computer how do you decide where it gets stored? . . . . . . . . . . 14
18.4 Transport layer protocols, TCP, UDP, real-world examples? . . . . . . . . . . . 14
18.5 If given an instruction, how is it executed inside the computer, tell me all steps? 14
18.6 Write 10, in how many number systems can this be written? . . . . . . . . . . . 14
18.7 10.001, convert this to octal? . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

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18.8 698 can this be octal, and why, convert to octal if no? . . . . . . . . . . . . . . 15
18.9 The different parts of a computer run on AC or DC? . . . . . . . . . . . . . . . 15
18.10What converts AC to DC? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
18.11Regression testing? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
18.12Name a testing method which is done by the user/customer? . . . . . . . . . . . 15
18.13Father of the computer? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
18.14Mother of the computer? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
18.15Difference between flow diagram and dataflow diagram? . . . . . . . . . . . . 15
18.16Made an egg diagram and asked what is it? . . . . . . . . . . . . . . . . . . . . 16
18.17How many types of diagrams are there? . . . . . . . . . . . . . . . . . . . . . 16
18.18Cohesion, coupling, and some big term? . . . . . . . . . . . . . . . . . . . . . 16
18.19What is SMPS (Switched-Mode Power Supply)? . . . . . . . . . . . . . . . . . 16
18.20Logical address space, physical address? . . . . . . . . . . . . . . . . . . . . . 16
18.21What is the degree of multiprogramming? . . . . . . . . . . . . . . . . . . . . 16
18.22Mid-term scheduler? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
18.23Print numbers 1-5 using recursion. . . . . . . . . . . . . . . . . . . . . . . . . 17
18.24Would this be faster using a loop? . . . . . . . . . . . . . . . . . . . . . . . . 17
18.25Which will take more space, loop or recursion? . . . . . . . . . . . . . . . . . 17
18.26Block diagram of a computer. . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
18.27Dangling pointers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
18.28Foreign key and a real-life example of how it helps. . . . . . . . . . . . . . . . 17
18.29Preemptive vs. non-preemptive difference. . . . . . . . . . . . . . . . . . . . . 17
18.30Deadlock avoiding techniques. . . . . . . . . . . . . . . . . . . . . . . . . . . 18
18.31Block diagram of a computer. . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
18.32What are the buses in a computer and what is bidirectional? . . . . . . . . . . . 18
18.33How does printf work in C? . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
18.34Draw DFA and NFA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
18.35FDMA (Frequency Division Multiple Access) vs. TDMA (Time Division Multiple
Access). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
18.36What is done during FDMA? . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
18.37How is the message carried by a carrier signal? . . . . . . . . . . . . . . . . . 18
18.38How is a queue implemented in memory? . . . . . . . . . . . . . . . . . . . . 19
18.39What do printf and scanf return? . . . . . . . . . . . . . . . . . . . . . . . . . 19
18.40Draw an AND gate. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
18.41What is a half and full adder and does it accept? . . . . . . . . . . . . . . . . . 19
18.42Write the 2’s complement of 4. . . . . . . . . . . . . . . . . . . . . . . . . . . 19
18.43What is a bootloader and where is it stored? . . . . . . . . . . . . . . . . . . . 19
18.44Types of secondary memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
18.45How to access memory in secondary memory? . . . . . . . . . . . . . . . . . . 19
18.46What is paged segmentation and segmented page? . . . . . . . . . . . . . . . . 20
18.47What is a translation look-ahead buffer and why is it used? . . . . . . . . . . . 20
18.48Why not increase the size of the page table? . . . . . . . . . . . . . . . . . . . 20
18.49JK flip-flop. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
18.50What’s a clock and how timing works in a computer. . . . . . . . . . . . . . . . 20
18.51Master-slave architecture. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

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18.52Bibhu went to his system and started taking a printout of a question to solve in
ML, some derivation for soft margin classifier and precision, recall, F1 score
for classification. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
18.53Cohesion-coupling and types. . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
18.54Design patterns, test design patterns. . . . . . . . . . . . . . . . . . . . . . . . 21
18.55SOLID principles. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
18.56Inheritance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
18.57Accuracy metrics for unsupervised learning. . . . . . . . . . . . . . . . . . . . 21
18.58Make a graph for bias-variance tradeoff and bias calculation. . . . . . . . . . . 21
18.59Paged segmentation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
18.60How to represent a graph. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
18.61Draw a complete graph with 4 nodes. . . . . . . . . . . . . . . . . . . . . . . . 22
18.62IP (Internet Protocol) which layer full form and what it is. . . . . . . . . . . . . 22
18.63TCP (Transmission Control Protocol) which layer. . . . . . . . . . . . . . . . . 22
18.64IPv4 vs. IPv6, which is what. . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
18.65How many bits in IPv4 and IPv6. . . . . . . . . . . . . . . . . . . . . . . . . . 23
18.66What is an IP address and how many bits. . . . . . . . . . . . . . . . . . . . . 23
18.67 Show me in my computer the IP address. . . . . . . . . . . . . . . . . . . . . 23
18.68Have you ever seen a computer? Used it? Name the components of a computer. 23
18.69Belady’s Anomaly. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
18.70Process synchronization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
18.71CPU scheduling. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
18.72BDS picked up queue from CPU scheduling and went into DSA and never came
back. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
18.73What kind of queues. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
18.74What is the kernel. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
18.75Is it hardware or software. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
18.76What is an OS, have you ever bought a book on OS. . . . . . . . . . . . . . . . 24
18.77Have you ever bought a book in your [Link]. . . . . . . . . . . . . . . . . . . . 24
18.78Array. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
18.79Time complexity. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
18.80Give us 2000 for what we’ve taught you in these 20 minutes and get out. . . . . 25
18.81Draw a queue, show insertion, deletion. . . . . . . . . . . . . . . . . . . . . . 25
18.82Condition for an empty queue. . . . . . . . . . . . . . . . . . . . . . . . . . . 25
18.83Is TCP/IP connectionless or oriented? . . . . . . . . . . . . . . . . . . . . . . 25
18.84Can UDP + IP be used as a connection-oriented protocol? . . . . . . . . . . . . 25
18.85Protocols in the application layer. . . . . . . . . . . . . . . . . . . . . . . . . . 25
18.86Which protocols are used when you send an email. . . . . . . . . . . . . . . . 25
18.87Universal gates. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
18.88Express OR gate using NAND gate. . . . . . . . . . . . . . . . . . . . . . . . 26
18.89Which protocol is used to stream IPL matches. . . . . . . . . . . . . . . . . . . 26
18.90Aloha vs. Slotted Aloha. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
18.91Non-linear data structures. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
18.92How a tree is stored in memory. . . . . . . . . . . . . . . . . . . . . . . . . . . 26
18.93Name some topologies. What are the problems in star topology? . . . . . . . . 26

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19 Networking 27
19.1 Length of IP header. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
19.2 TCP vs. UDP, which is reliable and why. . . . . . . . . . . . . . . . . . . . . . 27
19.3 What is a port number and in which layer is it resolved. . . . . . . . . . . . . . 27
19.4 Contention and congestion, in which case collision can happen. . . . . . . . . . 27
19.5 CDMA/CD full form, CDMA CA vs. CD, in which layer it happens. . . . . . . 27
19.6 Deadlock, condition, how it is dealt with. . . . . . . . . . . . . . . . . . . . . . 27
19.7 Real-life example of deadlock. . . . . . . . . . . . . . . . . . . . . . . . . . . 27
19.8 You are in a computer center, your boss asked you to buy a SAN switch what
will you do. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
19.9 What is a router, bridge? Difference between router and bridge. . . . . . . . . . 28
19.10Can a router act as a bridge? . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

20 Operating System 28
20.1 What is I/O queuing and what is device queuing? . . . . . . . . . . . . . . . . 28
20.2 Belady’s Anomaly. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
20.3 LTS (Long-Term Scheduler) vs. STS (Short-Term Scheduler). . . . . . . . . . . 28
20.4 Paging, page replacement algorithms. . . . . . . . . . . . . . . . . . . . . . . 29
20.5 External fragmentation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
20.6 Why is there a layered structure in OSI models. . . . . . . . . . . . . . . . . . 29
20.7 Why do we need logical addressing at all? Thread vs. process. . . . . . . . . . 29
20.8 Design Turing machine, PDA, NFA. . . . . . . . . . . . . . . . . . . . . . . . 29
20.9 Hamiltonian path. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
20.10ACID properties, normal forms, B+ trees. . . . . . . . . . . . . . . . . . . . . 30
20.11Mux, demux, decoder, complements, minterms, maxterms. . . . . . . . . . . . 30
20.12Cohesion, coupling, modularity, different testing. . . . . . . . . . . . . . . . . 30
20.13Block diagram of a computer, different registers, and other components. . . . . 30
20.148086 architecture (different segments in 8086). . . . . . . . . . . . . . . . . . . 30

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1 Grand Viva 2024

1.1 What is tree data structure?

1.2 How to store elements of a tree in an array?

1.3 Types of tree data structures?

1.4 Why is a tree a non-linear data structure?

1.5 What is the syntax of a copy constructor?

1.6 What is a destructor?

1.7 Given the postorder of a Binary Search Tree (BST), how would you
design the BST?

1.8 Explain Different Types of Process Models

1.9 MTech Project

1.10 Smoke Testing

1.11 Stubs and Drivers and Their Real-time Examples

1.12 If You Developed an OS, How Would You Test It?

1.13 Computer Networking Basic Questions

1.13.1 Based on Port Numbers, Protocols, and Flow Control Mechanisms

• What is ARQ?
• What is the difference between Go-Back-N and Selective Repeat?
• What is a socket, and why are they used?
• Different port numbers of the FTP protocol?

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1.14 Difference Between V-Model and Iterative Waterfall Model

1.15 What is Agile Model and its Types?

2 Operating Systems (OS)

2.1 What is PCB?

2.2 Difference between Process and Thread

3 Data Structures

3.1 Tell me some Data Structures you used?

3.2 Implement a Stack

3.3 What is Linear and Non-linear Data Structure?

3.4 Why is a tree a Non-linear Data Structure?

3.5 Declare a Linked List from Scratch

3.6 Write a Program to Reverse Your Name

4 Machine Learning

4.1 Confusion Matrix

Consider a scenario where a malware detection system analyzes a software binary and provides
an assessment of its malicious or benign nature. The potential outcomes are depicted in Figure
4 , yielding four possibilities:
1. True Positive: The system correctly identifies the binary as malware.
2. False Negative: The system incorrectly categorizes the binary as non-malicious when it
is, in fact, malware.
3. False Positive: The system erroneously labels a non-malicious binary as malware.
4. True Negative: The system accurately identifies a non-malicious binary as such.
The crucial metrics for evaluating the performance of the malware detection system are the
true positive rate and the false positive rate. In practical terms, achieving true positive and true
negative results is the ultimate goal, although it is often challenging.

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Figure 1: Confusion Matrix for Malware Classification

The true positive rate is a significant summary statistic that gauges the system’s ability to
detect malware within a given test set. This rate is calculated by dividing the number of true
positives by the total number of malware samples in the test set, providing insight into the
system’s proficiency in recognizing malware.
However, solely relying on the true positive rate for evaluation is insufficient. For instance, if
the evaluation criterion only considers this rate, a simplistic function that consistently identifies
all files as malware would yield a perfect score. A comprehensive assessment of a detection
system involves not only its capability to identify malware correctly but also its ability to distinguish
non-malicious content accurately.
To assess the system’s proficiency in identifying non-malicious content, it is imperative to
measure the false positive rate.

4.2 Formulas for Evaluation Metrics

4.2.1 Matthews Correlation Coefficient (MCC):

The Matthews Correlation Coefficient is given by:

TP × TN − FP × FN
MCC = p (1)
(T P + F P )(T P + F N )(T N + F P )(T N + F N )

where:

T P is the number of true positives,

T N is the number of true negatives,
F P is the number of false positives,
F N is the number of false negatives.

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4.2.2 Area Under the Curve (AUC):

The Area Under the Curve is often used in the context of ROC curves, and it is calculated
numerically by approximating the integral under the curve.

4.2.3 Cohen’s Kappa Coefficient (CKC):

Cohen’s Kappa Coefficient is given by:

Po − Pe
CKC = (2)
1 − Pe
where:

Po is the observed agreement,

Pe is the expected agreement.

Po is the ratio of the number of agreements to the total number of observations, and Pe is the
expected agreement assuming random chance.

4.2.4 Accuracy:

Accuracy is given by:

TP + TN
Accuracy = (3)
TP + TN + FP + FN

4.2.5 F1 Score:

The F1 Score is the harmonic mean of precision and recall, and it is given by:
2 × Precision × Recall
F1 Score = (4)
Precision + Recall

4.2.6 Recall (Sensitivity or True Positive Rate):

Recall is given by:

TP
Recall = (5)
TP + FN

4.2.7 Precision (Positive Predictive Value):

Precision is given by:

TP
Precision = (6)
TP + FP

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4.2.8 Specificity (True Negative Rate):

Specificity is given by:

TN
Specificity = (7)
TN + FP

4.2.9 Balanced Accuracy:

Balanced Accuracy is the average of Sensitivity and Specificity and is given by:
Sensitivity + Specificity
Balanced Accuracy = (8)
2

5 Matrix Multiplication
1 import numpy as np
2
3 def matrix_multiply (A , B ) :
4 return np . dot (A , B )
5
6 # Example usage
7 A = np . array ([[1 , 2] , [3 , 4]])
8 B = np . array ([[5 , 6] , [7 , 8]])
9 result = matrix_multiply (A , B )
10 print ( result )

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5.1 Solvay-Strassen Algorithm

The Solvay-Strassen algorithm is an efficient method for multiplying two matrices using the
divide-and-conquer approach. Here’s the algorithm:
1. Input:
• Two matrices A and B of size n × n.
2. Output:
• The product matrix C = A × B.
3. Algorithm:
3.1 If n is small enough, perform matrix multiplication using a standard algorithm.
3.2 Divide the input matrices A and B into four equal-sized submatrices:
   
A11 A12  B11 B12 
A= , B =  
A21 A22 B21 B22

3.3 Compute the following intermediate matrices:

M1 = (A11 + A22 )(B11 + B22 )

M2 = (A21 + A22 )B11

M3 = A11 (B12 − B22 )
M4 = A22 (B21 − B11 )
M5 = (A11 + A12 )B22
M6 = (A21 − A11 )(B11 + B12 )
M7 = (A12 − A22 )(B21 + B22 )
3.4 Compute the output submatrices:

C11 = M1 + M4 − M5 + M7

C12 = M3 + M5
C21 = M2 + M4
C22 = M1 − M2 + M3 + M6
3.5 Concatenate the output submatrices to form the final product matrix C.
The time complexity of this matrix multiplication algorithm is O(n3 ) where n is the size of the
matrices.

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6 SDLC Models

6.1 Waterfall Model

– Description: The waterfall model is a sequential approach to software development, where
progress flows steadily downwards through distinct phases. Each phase must be completed
before moving on to the next.
– Phases:
1. Requirements: Gathering and documenting customer requirements.
2. Design: Planning the software architecture and system design.
3. Implementation: Writing and coding the software.
4. Testing: Verifying that the software meets requirements.
5. Deployment: Releasing the software to users.
– Advantages:
• Clear project milestones.
• Well-defined requirements upfront.
– Disadvantages:
• Limited flexibility for changes.
• Late testing may lead to costly errors.

6.2 Agile Model

– Description: The agile model is an iterative and incremental approach to software development.
It emphasizes flexibility, customer collaboration, and delivering working software in short
iterations.
– Key Concepts:
• Sprints: Short development cycles (typically 2-4 weeks).
• User Stories: Small, manageable units of work representing customer requirements.
• Continuous Integration: Frequently integrating code changes into a shared repository.
– Advantages:
• Adaptability to changing requirements.
• Customer involvement throughout the development process.
– Disadvantages:
• Requires strong teamwork and communication.
• May be challenging to scale for large projects.

6.3 Scrum Model

– Description: Scrum is an agile framework that provides a structure for organizing and managing
work in complex software development projects. It emphasizes teamwork, accountability, and
iterative progress.
– Roles:
• Product Owner: Represents the stakeholders and defines product features.
• Scrum Master: Facilitates the team and ensures adherence to Scrum principles.
• Development Team: Self-organizing team responsible for delivering the product increment.

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– Artifacts:
• Product Backlog: List of all desired features and enhancements.
• Sprint Backlog: Subset of the product backlog for the current sprint.
• Increment: The sum of all completed product backlog items.
– Events:
• Sprint Planning: Meeting to plan the work for the upcoming sprint.
• Daily Stand-up: Brief daily meeting to synchronize the team’s activities.
• Sprint Review: Demo of the increment and feedback from stakeholders.
• Sprint Retrospective: Reflection on the previous sprint and identification of improvements.
– Advantages:
• Transparency and visibility of progress.
• Encourages self-organization and continuous improvement.
– Disadvantages:
• Requires a dedicated Scrum Master and adherence to Scrum principles.
• May not be suitable for all types of projects.

6.4 DevOps Model

– Description: DevOps is a set of practices that integrates software development (Dev) and
IT operations (Ops) to shorten the systems development life cycle and provide continuous
delivery with high software quality.
– Key Practices:
• Continuous Integration (CI): Automatically integrating code changes into a shared
repository.
• Continuous Deployment (CD): Automatically deploying code changes into production
or staging environments.
• Infrastructure as Code (IaC): Managing and provisioning infrastructure through code.
• Monitoring and Logging: Monitoring application performance and collecting logs for
analysis.
– Advantages:
• Accelerated delivery of features and updates.
• Improved collaboration between development and operations teams.
– Disadvantages:
• Requires cultural and organizational changes.
• Complexity in managing infrastructure and automation tools.

7 MVC (Model-View-Controller) Model

Model: This component represents the application’s data and business logic. It encapsulates the
data and behavior of the application, ensuring that changes to the data are reflected appropriately.
View: The view component is responsible for presenting the data to the user. It consists
of the user interface elements that users interact with, such as web pages, forms, or graphical
interfaces.

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Controller: Acting as an intermediary between the model and the view, the controller
processes user input and updates the model accordingly. It handles user requests, triggers
appropriate actions in the model, and selects the appropriate view to present the updated data.
Key Features:
- Separation of concerns: MVC separates the presentation, business logic, and data layers,
making the application easier to maintain and modify.
- Reusability: Each component can be reused independently, promoting modular development.
- Testability: Because of its modular structure, each component can be tested separately,
facilitating unit testing and ensuring code quality.

8 Microservices Architecture

Microservices architecture breaks down an application into a set of small, loosely coupled
services, each running in its own process and communicating with lightweight mechanisms
such as HTTP/REST or messaging queues. Each service is responsible for a specific business
capability and can be developed, deployed, and scaled independently.
Key Features:
- Decentralized data management: Each microservice manages its own data, enabling teams
to choose the most suitable data storage technology for their service.
- Scalability: Microservices allow individual services to be scaled independently based on
demand, enhancing the application’s overall scalability.
- Fault isolation: If a microservice fails, it doesn’t necessarily affect the entire system, as
other services can continue to function independently.

9 Driver Model

The driver model is a design pattern used in software development, particularly in testing scenarios,
where a component called the ”driver” controls or coordinates the execution of other components.
In testing, the driver simulates user inputs or system interactions to observe and verify the
behavior of the components under test.
Key Features:
- Simulation of interactions: The driver mimics external inputs or interactions that would
occur in a real-world scenario, allowing developers to observe how the system responds.
- Isolation of components: By controlling the execution of other components, the driver
can isolate the behavior of the component being tested, making it easier to identify and
debug issues.

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10 Architectural Pattern vs Architectural Design

Architectural Pattern: Describes a general, reusable solution to a recurring design problem

within a particular context. Examples include MVC, Microservices, and Layered Architecture.
Architectural patterns provide high-level guidelines and best practices for structuring systems.
Architectural Design: Refers to the process of defining the architecture of a specific system,
including decisions about the structure, behavior, and interaction of components to meet specific
requirements. Architectural design involves applying architectural patterns and principles to
create a solution tailored to a particular problem domain.

11 Difference between Stub and Driver

In software testing and development, stubs and drivers are both used in integration testing, which
involves combining individual modules or components to ensure they work together correctly.
Here’s the difference between them:
1. Stub:
• A stub is a simplified version of a module or component that simulates the behavior
of the missing or incomplete parts.
• It provides canned responses to calls made by the module being tested.
• Stubs are used when the module being tested depends on other modules or components
that are not yet developed or available for testing.
• Typically, stubs are created by developers during the early stages of development to
facilitate testing of individual modules in isolation.
2. Driver:
• A driver is a test module or component that calls the module being tested.
• It acts as a substitute for the actual calling module.
• Drivers are used when the module being tested is dependent on other modules or
components that are already developed.
• Drivers are created specifically for testing purposes to provide inputs to the module
under test and to simulate its environment.

12 Relationship with Testing Strategies

• Bottom-up testing: In bottom-up testing, testing starts from the lowest level modules and
moves upwards. Stubs are typically used in bottom-up testing because they simulate the
behavior of higher-level modules that are not yet developed.
• Top-down testing: In top-down testing, testing starts from the top-level modules and
moves downwards. Drivers are typically used in top-down testing because they simulate
the behavior of lower-level modules that are not yet developed.
Both stubs and drivers are crucial for integration testing to ensure that all modules interact
correctly within the system.

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13 OSI model and TCP/IP

Figure 2: TCP/IP vs OSI

TCP is an acknowledgment (ACK) based protocol and every data packet that is received has
to be acknowledged. The TCP-data packets are transmitted from the AP to the STAs, each of
which transmits a TCP-ACK packet for every TCP-data packet that it receives.

14 Testing

14.1 Smoke Testing

Smoke Testing, also known as ”Build Verification Testing”, is a type of software testing that
comprises a non-exhaustive set of tests that aim at ensuring that the most important functions
work. The result of this testing is used to decide if a build is stable enough to proceed with
further testing.

14.2 Regression Testing

Regression Testing is a type of software testing to confirm that a recent program or code change
has not adversely affected existing features. It is performed after modification of a system,
component, or a group of related units to ensure that the changes have not introduced new
faults.

14.3 Equivalence Class Partitioning

Equivalence Class Partitioning is a software testing technique that divides the input data of a
software unit into partitions of equivalent data from which test cases can be derived. In principle,
test cases are designed to cover each partition at least once.

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14.4 Boundary Value Analysis

Boundary Value Analysis is a software testing technique in which tests are designed to include
representatives of boundary values in a range. The behavior at the edge of an input domain often
differs from its behavior at the center and might expose the application’s defects.

15 BTech Viva Questions

16 DBMS

17 Machine Learning

Figure 3: Bias vs Variance Graphical Representation

17.1 Hard and Soft Margin SVM

When the data is linearly separable, and we don’t want to have any misclassifications, we use
SVM with a hard margin. However, when a linear boundary is not feasible, or we want to allow
some misclassifications in the hope of achieving better generality, we can opt for a soft margin
for our classifier.

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Figure 4: Hard and Soft Margin SVM

17.2 Lasso regression

Lasso regression, also known as least absolute shrinkage and selection operator (LASSO), is a
regression analysis method that performs both variable selection and regularization to enhance
the prediction accuracy and interpretability of the resulting statistical model. It’s a type of linear
regression model that adds a penalty term to the loss function, which is the sum of the absolute
value of the regression coefficients. This penalty term is known as the L1 regularization or
L1-norm regularization.

18 Testing

18.1 How can you connect two computers physically, if I give you a wire,
how will you connect these two PCs?

To physically connect two computers, you can use an Ethernet cable (also known as a network
cable). You would plug one end of the cable into the Ethernet port of each computer, creating
a direct wired connection between the two.

18.2 Do you know optical fibre, have you seen it, what happens there, why
do we use it?

Optical fiber is a type of technology that uses thin strands of glass or plastic to transmit data
as light pulses. It is used for long-distance communication and high-speed data transmission
because it offers higher bandwidth and less signal loss compared to traditional copper cables.

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18.3 RAM, ROM, EPROM, why do we use secondary memory, when something
is stored in a computer how do you decide where it gets stored?

RAM (Random Access Memory) is used for temporary storage of data and program instructions
that are currently being used by the computer. ROM (Read-Only Memory) stores firmware that
is used to boot up the computer and cannot be changed. EPROM (Erasable Programmable
Read-Only Memory) is a type of memory that can be erased and reprogrammed.
Secondary memory, such as hard drives or SSDs, is used for long-term storage of data and
programs. When something is stored in a computer, the operating system decides where it gets
stored based on the type of data and the storage hierarchy.

18.4 Transport layer protocols, TCP, UDP, real-world examples?

TCP (Transmission Control Protocol) and UDP (User Datagram Protocol) are both transport
layer protocols used in computer networks. TCP provides reliable, connection-oriented communication,
making sure that data is delivered error-free and in order. UDP, on the other hand, is connectionless
and does not guarantee delivery or order of data. Real-world examples of TCP include web
browsing and email, while UDP is used for streaming media and online gaming.

18.5 If given an instruction, how is it executed inside the computer, tell

me all steps?

The execution of an instruction inside a computer involves several steps:

• Fetch: The CPU fetches the instruction from memory.
• Decode: The CPU decodes the instruction to understand what operation needs to be
performed.
• Execute: The CPU executes the instruction, performing the specified operation.
• Store: If necessary, the CPU stores the result of the operation back to memory.

18.6 Write 10, in how many number systems can this be written?

The number 10 can be written in various number systems, including binary (1010), octal (12),
decimal (10), and hexadecimal (A).

18.7 10.001, convert this to octal?

The decimal number 10.001 is equivalent to 12.000 in octal.

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18.8 698 can this be octal, and why, convert to octal if no?

No, 698 cannot be a valid octal number because octal numbers only use digits from 0 to 7. If
we convert 698 to octal, it would be 1252 in octal.

18.9 The different parts of a computer run on AC or DC?

Different parts of a computer, such as the CPU and memory, run on DC (Direct Current).

18.10 What converts AC to DC?

A power supply unit (PSU), specifically a component called a rectifier, converts AC (Alternating
Current) to DC (Direct Current) for use in a computer.

18.11 Regression testing?

Regression testing is a type of software testing that is performed to ensure that changes or
updates to a program have not adversely affected existing features.

18.12 Name a testing method which is done by the user/customer?

Acceptance testing is a testing method done by the user/customer to determine if the system
meets their requirements.

18.13 Father of the computer?

Charles Babbage is often referred to as the ”father of the computer” for his work on the Analytical
Engine, a mechanical computer design.

18.14 Mother of the computer?

Ada Lovelace is often regarded as the ”mother of the computer” for her work on Charles Babbage’s
Analytical Engine and her notes on the engine’s operation, which included what is now recognized
as the first algorithm intended to be processed by a machine.

18.15 Difference between flow diagram and dataflow diagram?

A flow diagram (or flowchart) is a graphical representation of a process, showing the steps
involved and their sequence. A data flow diagram (DFD) is a graphical representation of how
data flows through a system, showing the processes that transform data, the data stores, and the
data flows between them.

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18.16 Made an egg diagram and asked what is it?

An egg diagram is a type of diagram used in software engineering to represent the relationships
between different modules or components of a system.

18.17 How many types of diagrams are there?

There are many types of diagrams used in various fields such as software engineering, network
design, and system architecture. Some common types include flowcharts, UML diagrams,
network diagrams, and entity-relationship diagrams.

18.18 Cohesion, coupling, and some big term?

Cohesion refers to the degree to which the elements of a module belong together. Coupling refers
to the degree of interdependence between modules. The ”big term” you might be referring to
could be ”modularity,” which is the degree to which a system is divided into modules that can
be independently developed and maintained.

18.19 What is SMPS (Switched-Mode Power Supply)?

SMPS is a type of power supply that uses switching devices to convert electrical power efficiently.
It is commonly used in computers and other electronic devices.

18.20 Logical address space, physical address?

The logical address space is the set of all possible addresses generated by a program. The
physical address is the actual address in memory where the data is stored.

18.21 What is the degree of multiprogramming?

The degree of multiprogramming refers to the number of programs that can be simultaneously
loaded into memory and executed by the CPU.

18.22 Mid-term scheduler?

The mid-term scheduler (also known as the medium-term scheduler) is a component of the
operating system that decides when to swap processes out of memory and onto disk, and vice
versa. It helps maintain a balance between keeping the CPU busy and ensuring that there is
enough memory for incoming processes.

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18.23 Print numbers 1-5 using recursion.

void printNumbers(int n) {
if (n > 0) {
printNumbers(n - 1);
printf("%d ", n);
}
}
// Call printNumbers(5) to print numbers 1 to 5

18.24 Would this be faster using a loop?

Yes, in general, using a loop for this task would be faster than using recursion due to the overhead
of function calls in recursion.

18.25 Which will take more space, loop or recursion?

Recursion typically takes more space than a loop because each recursive call requires additional
memory to store the function’s state.

18.26 Block diagram of a computer.

A block diagram of a computer typically includes components such as the CPU, memory, storage
devices, input/output devices, and the system bus.

18.27 Dangling pointers.

Dangling pointers are pointers that point to memory that has been deallocated or freed, leading
to undefined behavior when accessed.

18.28 Foreign key and a real-life example of how it helps.

A foreign key is a column or a set of columns in a database table that provides a link between
data in two tables. For example, in a database for a university, the student table may have a
foreign key that references the ID of a course in the course table, indicating which course the
student is enrolled in.

18.29 Preemptive vs. non-preemptive difference.

Preemptive scheduling allows a higher-priority task to interrupt a lower-priority task, while

non-preemptive scheduling does not allow such interruptions and lets the lower-priority task
run to completion.

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18.30 Deadlock avoiding techniques.

Deadlock avoiding techniques include resource allocation strategies such as Banker’s algorithm
and ensuring a strict ordering of resource requests.

18.31 Block diagram of a computer.

A block diagram of a computer typically includes components such as the CPU, memory, storage
devices, input/output devices, and the system bus.

18.32 What are the buses in a computer and what is bidirectional?

Buses in a computer are communication pathways that allow data to be transferred between
components. A bidirectional bus is one that can carry data in both directions.

18.33 How does printf work in C?

printf is a function in C used for formatted output. It takes a format string and a variable number
of arguments, formats them according to the format string, and prints the result to the standard
output stream.

18.34 Draw DFA and NFA .

DFA and NFA diagrams are typically drawn using circles for states and arrows for transitions
between states, labeled with input symbols.

18.35 FDMA (Frequency Division Multiple Access) vs. TDMA (Time Division
Multiple Access).

FDMA divides the frequency spectrum into multiple channels, each assigned to a different user,
while TDMA divides the time into slots, with each user getting a slot to transmit.

18.36 What is done during FDMA?

During FDMA, the frequency spectrum is divided into separate frequency bands, each allocated
to a different communication channel.

18.37 How is the message carried by a carrier signal?

The message is modulated onto the carrier signal, altering its amplitude, frequency, or phase to
encode the information.

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18.38 How is a queue implemented in memory?

A queue can be implemented in memory using arrays or linked lists to store the queue elements
and pointers to keep track of the front and rear of the queue.

18.39 What do printf and scanf return?

printf returns the number of characters printed, while scanf returns the number of items successfully
read and assigned.

18.40 Draw an AND gate.

A ---|AND|--- Output
B ---|

18.41 What is a half and full adder and does it accept?

A half adder adds two single-bit binary numbers and produces a sum bit (S) and a carry bit (C).
A full adder adds two binary numbers along with a carry from the previous stage and produces
a sum bit (S) and a carry bit (C). Both accept binary inputs and produce binary outputs.

18.42 Write the 2’s complement of 4.

The 2’s complement of 4 in 4-bit binary is 1100.

18.43 What is a bootloader and where is it stored?

A bootloader is a program that loads the operating system into memory during the system startup
process. It is typically stored in the boot sector of the computer’s hard drive or in a dedicated
boot ROM chip.

18.44 Types of secondary memory.

Types of secondary memory include hard disk drives (HDDs), solid-state drives (SSDs), optical
discs (CDs, DVDs), and magnetic tapes.

18.45 How to access memory in secondary memory?

Memory in secondary memory is accessed using input/output (I/O) operations. Data is transferred
between secondary memory and primary memory (RAM) using I/O channels.

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18.46 What is paged segmentation and segmented page?

Paged segmentation is a memory management technique that combines the benefits of paging
and segmentation. Segmented paging refers to using both segmentation and paging to manage
memory, where each segment is divided into pages.

18.47 What is a translation look-ahead buffer and why is it used?

A translation look-ahead buffer (TLB) is a cache that stores recently accessed virtual-to-physical
address translations. It is used to speed up address translation in virtual memory systems.

18.48 Why not increase the size of the page table?

Increasing the size of the page table can lead to increased memory overhead and slower access
times, as the entire page table needs to be searched for each memory access.

18.49 JK flip-flop.

A JK flip-flop is a sequential logic circuit that can be used to store one bit of information. It has
two inputs, J (set) and K (reset), and two outputs, Q and Q’.

18.50 What’s a clock and how timing works in a computer.

In a computer, a clock is a signal that oscillates between high and low states at a regular interval,
providing a timing reference for the system. Timing in a computer is crucial for coordinating
the operations of different components and ensuring synchronous operation.

18.51 Master-slave architecture.

Master-slave architecture refers to a design pattern where one component (the master) controls
the operation of one or more other components (the slaves). This architecture is commonly used
in communication systems and data replication.

18.52 Bibhu went to his system and started taking a printout of a question
to solve in ML, some derivation for soft margin classifier and precision,
recall, F1 score for classification.

It sounds like Bibhu is working on a machine learning problem involving the soft margin classifier
and evaluation metrics like precision, recall, and F1 score. These metrics are commonly used
to assess the performance of classification models.

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18.53 Cohesion-coupling and types.

Cohesion refers to the degree to which the elements within a module belong together, while
coupling refers to the degree of interdependence between modules. Types of cohesion include
functional, sequential, and communicational, while types of coupling include data, stamp, and
control coupling.

18.54 Design patterns, test design patterns.

Design patterns are reusable solutions to common problems in software design. Test design
patterns are patterns that help in designing effective and efficient test cases and test suites.

18.55 SOLID principles.

SOLID is an acronym for five design principles in object-oriented programming: Single Responsibility
Principle, Open/Closed Principle, Liskov Substitution Principle, Interface Segregation Principle,
and Dependency Inversion Principle.

18.56 Inheritance.

Inheritance is a mechanism in object-oriented programming that allows a new class to inherit

attributes and methods from an existing class, facilitating code reuse and creating a hierarchical
relationship between classes.

18.57 Accuracy metrics for unsupervised learning.

In unsupervised learning, where the data is not labeled, accuracy is not a common metric.
Instead, metrics like silhouette score, Davies–Bouldin index, and Dunn index are used to evaluate
clustering algorithms.

18.58 Make a graph for bias-variance tradeoff and bias calculation.

The bias-variance tradeoff is a key concept in machine learning that illustrates the relationship
between model complexity and its ability to generalize to unseen data. As the complexity of
a model increases, its variance typically increases, leading to overfitting. Conversely, as the
complexity decreases, the bias typically increases, leading to underfitting. The goal is to find
the right balance between bias and variance for optimal model performance.

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18.59 Paged segmentation.

Paged segmentation is a memory management technique that combines the benefits of paging
and segmentation. Segmented paging refers to using both segmentation and paging to manage
memory, where each segment is divided into pages.

18.60 How to represent a graph.

A graph can be represented using an adjacency matrix, where each cell represents the presence
or absence of an edge between two vertices, or using an adjacency list, where each vertex has a
list of adjacent vertices.

18.61 Draw a complete graph with 4 nodes.

A complete graph with 4 nodes (vertices) has every pair of distinct vertices connected by a
unique edge. It can be represented as follows:

A --- B
| / |
| / |
C --- D

18.62 IP (Internet Protocol) which layer full form and what it is.

IP (Internet Protocol) is a network layer protocol in the OSI model that is responsible for routing
packets between network devices. It provides the addressing and routing functions necessary
for data to be transmitted over a network.

18.63 TCP (Transmission Control Protocol) which layer.

TCP (Transmission Control Protocol) is a transport layer protocol in the OSI model that provides
reliable, connection-oriented communication between devices on a network. It ensures that data
is delivered in order and without errors.

18.64 IPv4 vs. IPv6, which is what.

IPv4 (Internet Protocol version 4) is the fourth revision of the Internet Protocol and uses 32-bit
addresses, allowing for approximately 4.3 billion unique addresses. IPv6 (Internet Protocol
version 6) is the most recent version of the Internet Protocol and uses 128-bit addresses, allowing
for significantly more unique addresses than IPv4.

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18.65 How many bits in IPv4 and IPv6.

IPv4 addresses are 32 bits long, while IPv6 addresses are 128 bits long.

18.66 What is an IP address and how many bits.

An IP address is a numerical label assigned to each device connected to a computer network

that uses the Internet Protocol for communication. It is used to identify and locate devices on a
network. IPv4 addresses are 32 bits long, and IPv6 addresses are 128 bits long.

18.67 Show me in my computer the IP address.

BDS likely wanted to see the IP address assigned to their computer, which can typically be
found in the network settings or by using a command such as ipconfig (Windows) or ifconfig
(Linux/macOS) in the command line.

18.68 Have you ever seen a computer? Used it? Name the components of
a computer.

Yes, I have knowledge about computers. The components of a computer include the CPU
(Central Processing Unit), memory (RAM), storage devices (HDD, SSD), input devices (keyboard,
mouse), output devices (monitor, printer), and the motherboard.

18.69 Belady’s Anomaly.

Belady’s Anomaly is a phenomenon in page replacement algorithms where increasing the number
of page frames can lead to an increase in the number of page faults.

18.70 Process synchronization.

Process synchronization is the coordination of processes in a multitasking operating system to

ensure that they do not interfere with each other’s execution.

18.71 CPU scheduling.

CPU scheduling is the process by which the operating system decides which process to execute
next on the CPU.

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18.72 BDS picked up queue from CPU scheduling and went into DSA and
never came back.

It seems like BDS shifted the topic from CPU scheduling to Data Structures and Algorithms
(DSA) and did not return to the previous discussion.

18.73 What kind of queues.

Queues in CPU scheduling can include ready queues, where processes are waiting to be executed,
and device queues, where processes are waiting for I/O operations to complete.

18.74 What is the kernel.

The kernel is the core component of an operating system that manages system resources, handles
communication between hardware and software, and provides essential services for other parts
of the operating system.

18.75 Is it hardware or software.

The kernel is software, specifically the part of the operating system that directly interacts with
the hardware.

18.76 What is an OS, have you ever bought a book on OS.

An operating system (OS) is a software that manages computer hardware and provides services
for computer programs. Yes, I have bought a book on operating systems.

18.77 Have you ever bought a book in your [Link].

Yes, I have bought books during my [Link] studies.

18.78 Array.

An array is a data structure that stores a collection of elements, each identified by at least one
array index or key.

18.79 Time complexity.

Time complexity is a measure of the amount of time taken by an algorithm to run as a function
of the length of the input.

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18.80 Give us 2000 for what we’ve taught you in these 20 minutes and get
out.

It seems like a hypothetical scenario where someone is asking for payment for teaching in a
short time.

18.81 Draw a queue, show insertion, deletion.

A queue can be represented as follows:

Front Rear
| |
1 2 3 4 5
Insertion (enqueue): Add an element to the rear of the queue.
Deletion (dequeue): Remove an element from the front of the queue.

18.82 Condition for an empty queue.

An empty queue has its front and rear pointers at the same position.

18.83 Is TCP/IP connectionless or oriented?

TCP/IP is a connection-oriented protocol suite, as it establishes a connection before data is

transferred and ensures reliable delivery of data.

18.84 Can UDP + IP be used as a connection-oriented protocol?

No, UDP (User Datagram Protocol) is a connectionless protocol and does not provide the
features required for connection-oriented communication.

18.85 Protocols in the application layer.

Protocols in the application layer include HTTP (Hypertext Transfer Protocol), FTP (File Transfer
Protocol), SMTP (Simple Mail Transfer Protocol), and DNS (Domain Name System), among
others.

18.86 Which protocols are used when you send an email.

When you send an email, protocols such as SMTP (Simple Mail Transfer Protocol) are used to
send the email from the client to the server, and protocols like IMAP (Internet Message Access
Protocol) or POP3 (Post Office Protocol version 3) are used to retrieve the email from the server.

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18.87 Universal gates.

Universal gates are logic gates that can be used to implement any other type of logic gate. NAND
and NOR gates are considered universal gates.

18.88 Express OR gate using NAND gate.

An OR gate can be expressed using NAND gates as follows:

A ---|NAND|----
|
B ---|NAND|--- Output

18.89 Which protocol is used to stream IPL matches.

The protocol used to stream IPL matches can vary, but commonly used protocols include HTTP
(Hypertext Transfer Protocol) and RTSP (Real-Time Streaming Protocol).

18.90 Aloha vs. Slotted Aloha.

Aloha is a random access protocol where stations can transmit data at any time, potentially
leading to collisions. Slotted Aloha divides time into slots and stations can only transmit at the
beginning of a slot, reducing the chances of collisions.

18.91 Non-linear data structures.

Non-linear data structures are data structures where each element can point to multiple other
elements, creating a non-linear sequence. Examples include trees and graphs.

18.92 How a tree is stored in memory.

A tree can be stored in memory using various data structures such as arrays or linked structures.
For example, in a binary tree, each node may contain references to its left and right child nodes.

18.93 Name some topologies. What are the problems in star topology?

Some network topologies include star, bus, ring, and mesh. In star topology, the main problem
is that if the central hub fails, the entire network becomes unusable.

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19 Networking

19.1 Length of IP header.

The length of the IP header in IPv4 is typically 20 bytes, but it can vary depending on the options
and flags set in the header.

19.2 TCP vs. UDP, which is reliable and why.

TCP (Transmission Control Protocol) is reliable because it provides mechanisms for error checking,
flow control, and retransmission of lost packets. UDP (User Datagram Protocol) is not reliable
because it does not provide these mechanisms.

19.3 What is a port number and in which layer is it resolved.

A port number is a 16-bit unsigned integer used to identify specific processes or services on a
host in a network. Port numbers are resolved at the transport layer (Layer 4) of the OSI model.

19.4 Contention and congestion, in which case collision can happen.

Contention occurs when multiple devices attempt to use a shared resource at the same time,
potentially leading to collisions. Congestion occurs when the network is carrying more data
than it can handle, leading to delays and packet loss.

19.5 CDMA/CD full form, CDMA CA vs. CD, in which layer it happens.

CDMA/CD stands for Carrier Sense Multiple Access with Collision Detection. CDMA CA
(Collision Avoidance) is a variation of CDMA that attempts to avoid collisions by sensing the
medium before transmitting. CDMA/CD operates at the Data Link Layer (Layer 2) of the OSI
model.

19.6 Deadlock, condition, how it is dealt with.

Deadlock is a situation in which two or more processes are unable to proceed because each is
waiting for the other to release a resource. Deadlock can be prevented by using techniques such
as resource allocation graphs, deadlock detection algorithms, and deadlock recovery mechanisms.

19.7 Real-life example of deadlock.

A real-life example of deadlock is a traffic deadlock, where two or more vehicles at an intersection
are unable to move because each is waiting for the other to yield.

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19.8 You are in a computer center, your boss asked you to buy a SAN
switch what will you do.

If my boss asked me to buy a SAN (Storage Area Network) switch, I would first research
different SAN switches available in the market, compare their features and prices, and then
make a recommendation to my boss based on our requirements and budget.

19.9 What is a router, bridge? Difference between router and bridge.

A router is a networking device that forwards data packets between computer networks. A bridge
is a networking device that connects two or more network segments, effectively extending a local
area network (LAN).
The main difference between a router and a bridge is that a router operates at the network
layer (Layer 3) of the OSI model and can connect different types of networks (e.g., Ethernet,
Wi-Fi), while a bridge operates at the data link layer (Layer 2) and connects similar types of
networks.

19.10 Can a router act as a bridge?

Yes, a router can act as a bridge by connecting two or more network segments and forwarding
packets between them.

20 Operating System

20.1 What is I/O queuing and what is device queuing?

I/O queuing refers to the process of managing the order in which I/O requests are processed by
a computer system. Device queuing specifically refers to the queuing of requests for a particular
I/O device.

20.2 Belady’s Anomaly.

Belady’s Anomaly is a phenomenon in page replacement algorithms where increasing the number
of page frames can lead to an increase in the number of page faults.

20.3 LTS (Long-Term Scheduler) vs. STS (Short-Term Scheduler).

The Long-Term Scheduler (LTS) selects which processes should be brought into the ready queue
from the job pool, while the Short-Term Scheduler (STS) selects which process should run next
from the ready queue.

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20.4 Paging, page replacement algorithms.

Paging is a memory management scheme that allows the physical memory to be divided into
fixed-size blocks called pages, which are then mapped to logical addresses. Page replacement
algorithms are used to decide which pages to evict from memory when there is a page fault.

20.5 External fragmentation.

External fragmentation occurs when free memory blocks are scattered throughout the memory
space, making it difficult to allocate contiguous blocks of memory to processes even when the
total free memory is sufficient.

20.6 Why is there a layered structure in OSI models.

The layered structure in the OSI (Open Systems Interconnection) model allows for the separation
of concerns, making it easier to design, implement, and maintain complex network protocols.
Each layer has specific functions and interacts with adjacent layers through well-defined interfaces,
promoting interoperability and modularity.

20.7 Why do we need logical addressing at all? Thread vs. process.

Logical addressing is essential because it allows for the abstraction of physical memory addresses,
enabling programs to be written without knowledge of the underlying hardware layout. This
abstraction makes programs more portable and easier to develop.
A thread is a lightweight process that can be managed independently within a process.
Threads share the same memory space and resources, while processes have their own memory
space and resources. Threads are more efficient for multitasking within a single process, as they
require less overhead than separate processes.

20.8 Design Turing machine, PDA, NFA.

Designing a Turing machine, Pushdown Automaton (PDA), or Non-deterministic Finite Automaton

(NFA) involves specifying the states, transitions, input alphabet, and rules for accepting or
rejecting inputs. Each of these models has different capabilities and is used to solve different
types of computational problems.

20.9 Hamiltonian path.

A Hamiltonian path is a path in a graph that visits each vertex exactly once. Finding a Hamiltonian
path in a graph is a classic problem in graph theory and is NP-complete, meaning it is computationally
challenging for large graphs.

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20.10 ACID properties, normal forms, B+ trees.

ACID properties (Atomicity, Consistency, Isolation, Durability) are properties that guarantee
that database transactions are processed reliably. Normal forms in database design are rules for
organizing data to minimize redundancy and dependency. B+ trees are a type of self-balancing
tree data structure commonly used in database systems and file systems for indexing.

20.11 Mux, demux, decoder, complements, minterms, maxterms.

Multiplexer (mux), demultiplexer (demux), and decoder are fundamental digital logic components
used in designing combinational circuits. A mux selects one of several input lines and directs
it to a single output line based on control signals. A demux performs the opposite operation,
directing the input from a single line to one of several output lines. A decoder converts coded
inputs into a set of output lines. Complements, including 1’s complement and 2’s complement,
are used in binary arithmetic for negation and subtraction. Minterms and maxterms are terms
used in Boolean algebra to express logical expressions.

20.12 Cohesion, coupling, modularity, different testing.

Cohesion refers to the degree to which the elements within a module belong together. High
cohesion indicates that the elements are closely related and focused on a single task, while low
cohesion implies that the elements are less related and may perform multiple tasks. Coupling
measures the interdependence between modules. Low coupling indicates that modules are
relatively independent, making the system easier to maintain and modify. Modularity is the
concept of dividing a system into smaller, manageable parts or modules. Different testing
techniques include unit testing, integration testing, system testing, and acceptance testing, each
focusing on different aspects of software quality assurance.

20.13 Block diagram of a computer, different registers, and other components.

The block diagram of a computer typically includes components such as the central processing
unit (CPU), memory, input/output (I/O) devices, and storage. Different registers in a CPU
include the program counter (PC), instruction register (IR), memory address register (MAR),
memory data register (MDR), and general-purpose registers (such as accumulator, index registers,
and stack pointer). Other components may include arithmetic logic units (ALU), control unit,
cache memory, buses, and various peripheral devices.

20.14 8086 architecture (different segments in 8086).

The 8086 microprocessor architecture includes several segments, each serving a specific purpose.
These segments include the code segment (CS), which holds the program instructions, the data
segment (DS) for data storage, the stack segment (SS) for storing procedure call information

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and local variables, and the extra segment (ES), which provides additional data storage space.
These segments are used to organize memory access in real mode operation.

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