CHAPTER 1: MOS TRANSISTOR MODELS 7
1-2-3 MOST and JFET
In the JFET structure of Fig. 1-k, both controlling capacitances Cqc and Cue are
depletion layer capacitances. By definition, a FET device with channel conductiv
ity controlled by the width of a junction depletion layer or by a junction depletion
layer capacitance is called a Junction Field Effect Transistor (JFET). The structure of
Fig. 1-la is a double JFET.
By definition, a FET device with channel conductivity controlled by an oxide ca
pacitance, is called a Metal Oxide Semiconductor Transistor (MOST). The structure of
Fig. 1 - 1Z> is a parallel connection of a MOST and a JFET. The drain-source current can
be controlled by the top (MOST) gate, by the bulk (JFET) gate or by both in parallel.
However, if several MOST transistor structures are realized on the same substrate,
they share the same bottom (JFET) gate. Therefore, this bottom gate is not useful as
an input gate to control the current of the device. On the other hand, the top (MOST)
gate is well isolated from device to device resulting in only the top MOST gate being
used. The device in Fig. 1-16 is a MOS Transistor. Its top MOST gate is the only
gate used; its bottom JFET gate is handled as a parasitic effect.
The effect of the parasitic JFET in a MOST is represented in the threshold value
VT of the MOST by means of factor y (gamma). This factor is the body factor or
bulk polarization factor. It is given by
= V2£si^NsuB (Mfl)
y Cm
whjch has as a dimension V1/2. By use of the expressions of Cbc and Cgc, this factor
is also given by
y = (l-4ft)
Cqc
Body factor y is directly proportional to the ratio of both controlling capacitances
Cgc and Cqc (see Fig. 1-1). The proportionality factor is the voltage dependence of
the bulk junction capacitance Cbc-
We will review the ratio of both controlling capacitances later in this book. For
now, however, the ratio is represented by a specific parameter n, which is defined by
n- 1 = — = (l-5a)
Cgc ^y/^j ~ vbs
Note that n depends on the applied voltage vbs, whereas y does not. Parameters
y and n are the first two parameters of the MOST model.
In circuit simulators, the best known of which is SPICE, MOS transistor parameters
must be used (Antognetti and Massobrio 1988). They are obtained from measurements
and are normally provided by the silicon foundry that produced the circuit simulators.
Representative values for a standard 3 pm p-well CMOS process are listed in Ta
ble 1-1. For each parameter the expression in which this parameter has occurred first
is added.