8 DESIGN OF ANALOG INTEGRATED CIRCUITS AND SYSTEMS
TABLE 1-1 NOMINAL SPICE PARAMETERS FOR A MOST (p-WELL CMOS)
Equation
or Table
Type nMOS pMOS Dimension Name number
Level 1
VTO 0.6 -0.77 V Zero bias threshold voltage Eq. 1-6a
KP 4.0E-5 1.5E-5 A/V2 Transconductance parameter Eq. 1-9d
GAMMA 0.92 0.54 V1/2 Bulk threshold parameter Eq. 1-4a
LAMBDA 0.022 0.047 v-i Channel length modulation
parameter Eq. 1-24a
CGSO 5.2E-10 4.0E-10 F/m GS overlap capacitance
per meter channel width Table 1-6
CGDO 5.2E-10 4.0E-10 F/m GD overlap capacitance
per meter channel width
CGBO F/m GB overlap capacitance
per meter channel width
CJ 4.5E-4 3.6E-4 F/m2 Zero bias junction capacitance
MJ 0.5 0.5 — Grading coefficient
CJSW 6E-10 6E-10 F/m Zero bias junction
sidewall capacitance
MJSW 0.33 0.33 — Grading coefficient
PB 0.6 0.6 V Bulk junction potential Eq. 1-3b
FC 0.5 0.5 — Coefficient forward bias depletion Table 2-4
capacitance
JS 1E-3 1E-3 A/m2 Bulk junction saturation current Eq. 1-35
TPG 1.0 -1.0 4-- Type of gate Eq. 1-6b
LD 3.2E-7 3.2E-7 m. Lateral diffusion Eq. 1-21 a
RSH 20 50 n/D Sheet resistance diffusion of
D and S Eq. 1-36
RS 15 20 Q Ohmic source resistance Eq. 1-36
RD 15 20 R Ohmic drain resistance Eq. 1-36
IProcess parameters
TOX 5.2E-8 5-2E-8 hi Oxide thickness Eq. 1-1 b
PHI 0.60 0.60 V Surface potential (2<f>p) Eq. 1-6d
NSUB 4.6E15 2.5E14 cirr3 Substrate doping Eq. 1-3b
NSS 5E10 5E10 cm-2 Effect of surface charge (Qox) Eq. 1-6a
Added for Level 2
NFS 5E10 9E10 cm-2 Effect of fast surface states Eq. 1-5Ö
UO 500 200 cm2/V Surface mobility Eq. 1-38a
UCRIT 1E6 5.2E4 V/cm Critical field for mobility Eq. 1-38a
degradation
UEXP 0.01 0.17 — Critical field exponent Eq. 1-38a
UTRA 0.5 0.5 — Transverse field coefficient Eq. 1-38a
VMAX 1.0E5 1.0È5 cm/s Maximum drift velocity Eq. 1-38a