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Vlsi Lab9

The document details a VLSI design lab focused on the layout design of static memory cells, including a 4x4 array of SRAM cells. It includes circuit configurations, simulation parameters, and calculations for the area of SRAM. The conclusion highlights the design principles of static memory cells and observations on gate delays and power dissipation in larger arrays.

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Munawer Malik
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26 views5 pages

Vlsi Lab9

The document details a VLSI design lab focused on the layout design of static memory cells, including a 4x4 array of SRAM cells. It includes circuit configurations, simulation parameters, and calculations for the area of SRAM. The conclusion highlights the design principles of static memory cells and observations on gate delays and power dissipation in larger arrays.

Uploaded by

Munawer Malik
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd

VLSI Design

Lab # 09

Name: Munawar ahmed


Wajiha Noor
Registration No: FA22-EEE-030
FA20-EEE-031
Class: EEE-6
Instructor Name: Dr. Shahrukh Agha

Pre-Lab
Task 1:

In Lab
In Lab Task # 1: Layout Design of Static Memory Cell
.lib "C:\Users\hp\Documents\TannerEDA\TannerTools_v2019.2\Process\Generic_250nm\Models\
Generic_250nm.lib" TT

.tran 10p 24n

Vdd Vdd Gnd 2.5

VBL BL Gnd PULSE (0 2.5 0 0 50p 450p 1000p) ROUND=0

VBLB BLB Gnd PULSE (0 2.5 0 0 50p 900p 2000p) ROUND=0

VQ Q Gnd PULSE (0 2.5 0 0 50p 1800p 3000p) ROUND=0

VQB QBB Gnd PULSE (0 2.5 0 0 50p 2700p 4000p) ROUND=0

VWL WL Gnd PULSE (0 2.5 0 0 50p 3700p 5000p) ROUND=0

.print tran v(BL,Gnd) v(BLB,Gnd) v(Q,Gnd) v(QB,Gnd) v(WL,Gnd)

* Total Nodes: 49

* Total Elements: 145

* Total Number of Shorted Elements not written to the SPICE file: 0

* Output Generation Elapsed Time: 0.011 sec

* Total Extract Elapsed Time: 5.413 sec

.END
Area of SRAM:

Area=L*W=26.275*13.200=346.83

In-lab Task 2: Layout of 4x4 Array of Static Memory Cell


.lib
"C:\Users\hp\Documents\TannerEDA\TannerTools_v2019.2\Process\Generic_250nm\Models\Generic_250nm.lib" TT

.tran 10p 24n

Vdd Vdd Gnd 2.5

VBL BL Gnd PULSE (0 2.5 0 0 50p 450p 1000p) ROUND=0

VBLB BLB Gnd PULSE (0 2.5 0 0 50p 900p 2000p) ROUND=0

VQ Q Gnd PULSE (0 2.5 0 0 50p 1800p 3000p) ROUND=0

VQB QBB Gnd PULSE (0 2.5 0 0 50p 2700p 4000p) ROUND=0

VWL WL Gnd PULSE (0 2.5 0 0 50p 3700p 5000p) ROUND=0

.print tran v(BL,Gnd) v(BLB,Gnd) v(Q,Gnd) v(QB,Gnd) v(WL,Gnd)


Area of 4X4 SRAM:
Area=L*W=110.250*58.525

Area=6452.38

Critical Analysis/ Conclusion


The basic cell for static memory designs us based on 6 transistors, with two pass gates instead of
one gate. The circuit consists of two cross-coupled inverters but uses two pass transistors
instead of one transistor. The cell has been designed to be duplicated in X and Y to create a large
array of cells. The usual sizes of Megabit SRAM memories are 256 columns x 256 rows or
higher. The selection lines WL concern all the cells of one row.
We have further created 4x4 arrays of SRAM Cells that can store more data than a single cell.
In the post-lab, we observed that if we increase the distance between the individual cells in a
4x4 array then the gate delays increase with less power dissipation than in the previous case

THE END

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