LDC Manual Student NEW
LDC Manual Student NEW
DEPARTMENT OF EEE
STUDENT MANUAL
Name :
Register Number :
Class :
Batch :
Vision:
To impart state-of- the art technical education, including sterling values and shining character,
producing engineers who contribute to nation building thereby achieving our ultimate objective of
Mission:
• Continuous upgradation of its teaching faculty to ensure a high standard of quality education
and to meet the ever-changing needs of the society
• Constant interaction with its stakeholders
• Linkage with other educational institutions and industries at the national and international
level for mutual benefit
• Provision of research facilities and infrastructure in line with global trends
• Adequate opportunities and exposure to the students through suitable programs, to mould
their character and to develop their personality with an emphasis on professional ethics and
moral values
VISION AND MISSION OF THE DEPARTMENT
Vision:
Mission:
M1: To provide quality education to students in the field of Electrical and Electronics
Engineering.
M2: To inculcate innovative skills and improve research capabilities to bridge the gap between
academia and industry.
M3: To develop social responsibility with moral and professional ethical values.
PEO1: Provide adequate knowledge to analyze power electronics drives, power systems and
work with inter-disciplinary groups.
PEO2: Develop skills needed to work on computational platform and software applications.
PEO3: Encourage the ability to design, analyze and build electrical and electronics systems for
the present and also the future.
PEO4: Promote managerial skills and inculcate professional ethics.
PSO1: Able to understand the principles and working of electrical components, Circuits,
Systems and Control that are forming a part of power generation, transmission, distribution,
utilization, conservation and energy saving.
PSO2:Able to apply mathematical methodologies to solve problems related with electrical
engineering using appropriate engineering tools and algorithms.
PSO3:Able to use knowledge in various domains to identify research gaps and hence to
provide solution which leads to new ideas and innovations.
PROGRAM OUTCOMES (POs)
List Of Experiments
1. Implementation of Boolean Functions, Adder and Subtractor circuits.
2. Code converters: Excess-3 to BCD and Binary to Gray code converter and vice-versa.
3. Parity generator and parity checking.
4. Encoders and Decoders.
5. Counters: Design and implementation of 3-bit modulo counters as synchronous and
Asynchronous types using FF IC’s and specific counter IC.
6. Shift Registers: Design and implementation of 4-bit shift registers in SISO, SIPO, PISO, PIPO
modes using suitability IC’s.
7. Study of multiplexer and de multiplexer
8. Timer IC application: Study of NE/SE 555 timer in Astability, Monostability operation.
9. Application of Op-Amp: inverting and non-inverting amplifier, Adder, comparator, Integrator
and Differentiator.
10. Voltage to frequency characteristics of NE/ SE 566 IC.
11. Variability Voltage Regulator using IC LM317.
OUTCOMES:
At the end of the course, the student should have the:
• Ability to understand and implement Boolean Functions.
• Ability to understand the importance of code conversion
• Ability to Design and implement circuits with digital ICs like decoders, multiplexers, register.
• Ability to acquire knowledge on Application of Op-Amp
• Ability to Design and implement counters using analog ICs like timers, VCOs and digital ICs
like Flip-flops and counters.
COURSE OUTCOMES:
CO/PO PO1 PO2 PO3 PO4 PO5 PO6 PO7 PO8 PO9 PO10 PO11 PO12 PSO1 PSO2 PSO3
- - - 3 - - - 1.5 - - 3 3
CO213.1 2 1 2
- - 3 3 - - - 1.5 - - 3 3
CO213.2 2 1 2
- 3 2 3 3 - - 1.5 - - 3 3
CO213.3 2 1 2
- 3 3 3 3 - - 1.5 - - 3 3
CO213.4 2 1 2
- - - - - - - 1.5 - - - 3
CO213.5 - - -
- 3 1.6 3 3 - - 1.5 - - 3 3
CO213 2 1 2
S.No. Name of Experiment
TURE
(i) 7400 (ii) 7402 (iii) 7404 (iv) 7408 (v) 7432 (vi) 7486
OBJECTIVE :
To understand experimentally the functionality of various logic ICs and their alternates given
and to implement the same using NAND gates only.
COMPONENTS REQUIRED:
THEORY:
Most real world signals are analog in nature which continuously changes with time. On the
contrary, digital signal is characterized by two logic levels – 0s and 1s. The continuous nature of
analog signal is confined within these two logic levels. As the confinement goes, there arises a
noise level between these two logic values. Digital signals have numerous advantages over their
analog counterpart.
To mention a few, the systems processing digital signals can be characterized with precision,
ease of design, programmability, functionality and flexibility, speed, economy, keeping pace with
technology. Most of the texts explaining digital often denote 0s and 1s as Low and High values.
This is due to the fact that they describe real values and not abstract quantities. Confined to two
logic values, digital systems can now be solved using switching algebra – the values being low
and high, 0s and 1s and ON and OFF. Switching algebra can be functionally described using a
table – referred to as truth table. To do a functional description, the system designer need not
require the knowledge of the actual components with which the system is made of. Also no special
mathematics knowledge is required.
Functions to be performed by a system can be visualized mentally which makes the design
totally logical. Logic circuit can be diagrammatically represented using a black box which certain
inputs and outputs, the operation performed by the black box can be represented with the help of
a table. The circuit performing the logic function is referred to as Gate. The name is due to the
fact that the circuit performs the logical operation on a set of inputs and gives out a single output
– gates out a single output – gating out – gate. Basically there are three basic logic functions –
AND, OR and NOT.
PIN Diagrams:
AND gate – Produces one output if and only if all the inputs are high. OR gate –
Produces one output if any one of the input is high. NOT gate – Produces an output
which is just the inversion of its input.
Truth Table:
The Truth tables for basic and derived logic gates
The truth tables for the basic functions are shown. With the basic logic functions clearly
defined, combinations of these basic functions can be made to realize other two logic functions –
NAND and NOR. NAND gate – NOT combined with AND – produces output which is just the
opposite of AND gate. NOR gate – NOT combined with OR – produces output which is just the
opposite of OR gate. The truth tables are shown. The list does not end here. We have two more
interesting Logic gates in our kit. They are Exclusive OR, often referred to as Ex-OR and Exclusive
NOR, often referred to as Ex-NOR gates. Ex-OR gate – produces high only when the inputs are
different. Ex-NOR gate – produces high only when the inputs are same.
PROCEDURE:
1. Connections are given as per the pin diagram of IC.
2. Each IC has 4 logic gates and for NOT gate it has 6 logic gates internally.
3. Verify the truth table
(a) Verification of truth table:
IC7404
When logic 1 is applied to one of NOT gate of 7404 IC, then output becomes
zero.
When input LED is ON (RED), the output LED become OFF and vice versa
IC7432
The output of an OR gate is a 1 if one or the other or both of the inputs are 1, but a
0 if both inputs are 0. When One or the other or Both of the input LEDS are ON
(RED Light), then output LED is ON(RED) otherwise Output LED is OFF.
IC7408
AND Gate: The output of an AND gate is only 1 if both its inputs are 1. For all
other possible inputs the output is 0.When both the LEDS are On, then output LED
is ON (RED Light) otherwise Output LED is OFF.
IC7402
The output of the NOR gate is a 1 if both inputs are 0 but a 0 if one or the other or
both the inputs are 1. NAND Gate: The output of the NAND gate is a 0 if both
inputs are 1 but a 1 if one or the other or both the inputs are 0.
IC7486
The output of the XOR gate is a 1 if either but not both inputs are 1 and a 0 if the
inputs are both 0 and both 1.
(b) Implementation of basic logic gates using NAND gate
1. The connections are given as per the circuit diagram
2. The truth table is verified
. NAND gate as Universal gate
NAND gate is universal gate. It can perform all the basic logic function.:
NAND gate is actually a combination of two logic gates i.e. AND gate followed by NOT
gate. So its output is complement of the output of an AND gate. This gate can have minimum
two inputs. Output is always one. By using only NAND gates, we can realize all logic functions:
AND, OR, NOT, NOR, XOR and XNOR
⮚ IMPLEMENTING OR USING NAND GATE : The OR gate is replaced by a NAND gate with all its
inputs complemented by NAND gate inverters.
Thus, the NAND gate is a universal gate since it can implement the AND,
OR, NOT and many other logic functions.NOR GATE CAN BE USED AS A UNIVERSAL GATE
REAL TIME APPLICATIONS:
1. Logic gates are used in industrial automation.
2. These gates are commonly used in traffic light systems
VIVA QUESTIONS:
RESULT:
CIRCUIT DIAGRAM:
AIM:
To design and verify the truth table of a circuit which implements the Boolean Function f(A,B,C,D)
= Εm (2,3,5,7,10,11,13,14,15) using minimum number of logic gates (using K-map or QMC
method).
OBJECTIVES:
To understand various techniques of minimizing a function.
COMPONENTS REQUIRED:
THEORY:
The basic mathematics behind the logic design of digital system is Boolean algebra. Devices
making up any digital system are two-state devices (transistors with high or low value at the
output) which take up two values at any instant. Boolean algebra in which the variables assuming
only two possible instants is a special case of Boolean algebra, referred to as switching algebra.
Switching functions can be simplified by the theorems and laws of Boolean Algebra. Although
the method adopted is effective, it lacks a systematic approach in the sense that it is difficult to
say when the designer has reached a minimum solution.
Karnaugh map (K-map) and Quine-McCluskey (QMC) methods overcome the problems
associated with the attainment of minimum solution. The need for minimum solution is
inevitable as the solution obtained decides the number of gates required for the subsequent
implementation. When it comes to number of gates required, it is also essential to
concentrate on the number of gate inputs required.
Hence it becomes essential to obtain the minimum SOP and POS expressions. It is also important
to mention that unlike the minterm and maxterm expressions, the minimum SOP and POS
expressions obtained need not be necessarily unique. That is, a designer may end up with more than
one minimum SOP or POS expressions. This ambiguity is solved by resorting to systematic
approaches like K-map and QMC methods of simplifications.
The K-map and QMC methods employed, simplify the given minterms to sum of product (SOP)
expression (group of AND gates feeding a single OR gate) which is essentially a
two level simplification. Similarly the product of sums (POS) expressions is a group of OR
gates feeding a single AND gate.
Confining our discussion with K-map (the reader is advised to extend this discussion to QMC
method) any single 1 or group of 1’s which can be combined together in map of a function, F
represents a product term in the SOP expression is referred to as implicant of F. A single 1
on a map is a prime implicant if it is not adjacent to any other 1’s. Similarly, two adjacent 1’s
on a map is a prime implicant if they are not contained in a group of four 1’s. Similarly, four
adjacent 1’s on a map is a prime implicant if they are not present in a group of eight 1’s. I stop
here for need of space. The minimum SOP of a function consists of some (but not necessarily
all) of the prime implicants of a function. That is, all prime implicants are not necessary for the
eventual minimum solution. It necessitates a systematic approach in finding the prime implicant
which actually make up the minimum solution. It can be explained that, if a minterm is covered
by a single prime implicant, it is referred to as essential prime implicant. The minimum solution
will have all the essential prime implicant.
PROCEDURE:
(2,3,5,7,10,11,13,14,15)
1. Using the given function with the help of k-map derive the expression for the
same.
2. Develop the logic diagram and verify the truth table for different input
combinations
REALTIME APPLICATIONS:
1.It is used in light switches. Boolean algebra can be applied to any system in which each variable
has two states. Boolean algebra is applied in computer electronic circuits
Boolean algebra as the calculus of two values is fundamental to computer circuits, computer programming, and
mathematical logic, and is also used in other areas of mathematics such as set theory and statistics.
2.Boolean operations help define algorithms for filtering, transforming, and analyzing digital signals,
contributing to applications like image processing, audio compression, and telecommunications
VIVA QUESTIONS:
1. Give any three applications of Boolean algebra in image processing?
2. What are the basic logic gates used in implementing Boolean functions?
3. What is the difference between a sum-of-products (SOP) and a product-of-sums (POS) expression?
4. What is the concept of minterms and maxterms in the context of Boolean functions?
5. What is Karnaugh Map (K-map), and how is it used for simplifying Boolean functions?
RESULT:
CIRCUIT DIAGRAM:
AIM:
TO design and verify the truth table of half adder, half subtractor, full adder and full
Subtractor circuits
OBJECTIVE:
COMPONENTS REQUIRED:
THEORY:
Half adders perform addition of two binary digits with sum and carry outputs. Full
adders perform addition of three binary digits with sum and carry outputs. Explaining in
the similar way, circuit performing subtraction of two binary digits is referred to as half
subtractors and circuit performing subtraction of three binary digits is referred to as full
subtractors. We refer the outputs as difference and borrow in the case of subtractor
circuits.
The truth table of adder and subtractor circuits do not differ by much except for an
inversion in one of the inputs in the case of subtractor circuit. So both operations can be
implemented in a single circuit with a control signal.
Full adders and full subtractors form the fundamental building blocks of any digital
system, these circuits can be used effectively in implementing fast adders circuits such
as ripple carry adders, carry save adders, carry select adders etc.,
Implementation of Half Subtractor and Full Subtractor
PROCEDURE:
1. Using truth table, develop the logic expression with the help of K-map.
2. Implement the circuit as per the truth table and verify the same.
REALTIME APPLICATIONS:
VIVA QUESTIONS:
4. What is the significance of the carry input and carry output in a full-adder?
RESULT:
BCD to Excess-3 Converter:
Truth Table and Karnaugh Map Simplification
CIRCUIT DIAGRAM:
EXP NO:
DATE: CODE CONVERTERS: EXCESS-3 TO BCD AND BINARY TO
GRAY CODE CONVERTERS AND VICE VERSA
AIM:
(iii) To design and implement Binary to Gray code converter circuit and to
verify its truth table.
(iv) To design and implement Gray to Binary code converter circuit and to
verify its truth table.
OBJECTIVE:
To understand various code conversion and implement the same.
COMPONENTS REQUIRED:
THEORY:
BCD – XS3 code: The simplest form of binary coding is the one in which the decimal
number is replaced by its binary equivalent based on its position (weight). We refer the
same as Binary Coded Decimal or simply BCD. Since we have only 0 – 9 binary digits, the
binary equivalent from 1010 to 1111 stands invalid. The excess-3 code is simply adding
three to each BCD code. The conversion from one to the other can be simply carried out as
shown. BCD code is also referred to as weighted code for the reason mentioned earlier. We
refer BCD code as 8-4-2-1 code. There are many forms of weighted code namely, 6-3-1-1
code, 2-4-2-1 code etc. Gray code: In contrast to the case mentioned above, Gray code is a
non-weighted code. Gray code has the unique property that the successive decimal digits
differ exactly by a single bit. This is primarily done to improve the reliability of the decimal
code when it is used to convert analog quantities such as shaft position. The conversion of
one to another code can be carried out using the procedure shown.
CIRCUIT DIAGRAM:
TRUTH TABLE: CIRCUIT DIAGRAM: BINARY TO GRAY
REALTIME APPLICATIONS:
VIVA QUESTIONS:
RESULT:
PARITY GENERATOR
PARITY CHECKER
(ii) To design and verify the truth table of a circuit which checks odd and even
parity bit for three bit binary input.
OBJECTIVE:
To understand various error detecting techniques and implement the same.
COMPONENTS REQUIRED:
Each 2
THEORY:
Parity: The concept of parity is employed for error-checking purposes. The transmission of
digital signals is accompanied often with errors. The concept of parity includes an extra bit called as
parity bit. The parity bit is assigned 1 or 0, to make the number of 1’s transmitted in the data bit (say,
n bits) even or odd. Accordingly, the parity is referred to as even parity or odd parity. The parity
generated is altered if any error occurs during transmission. The same is checked at the receiving end
to using a parity checker circuit discussed. If error occurs in more than one bit or say, in even number
of bits, the concept of parity becomes useless.
PROCEDURE:
1. Using the truth table, develop the logic expression and logic diagram
2. The truth table is verified for the same.
REALTIME APPLICATIONS:
• Memory Systems
• Serial Communication
• Data Storage
• Network Communication
• Telecommunication Systems
• Industrial Control Systems
• Embedded Systems
•
Simple Error Detection
VIVA QUESTIONS:
2. How does a parity generator decide whether to set the parity bit to 0 or 1 for even and odd parity,
respectively?
RESULT:
Decoder:
AIM:
To design and implement a decoder and an encoder circuit using ICs and to verify its truth table
OBJECTIVE:
To design and implement encoder and decoder circuits using IC and to verify it’s truth table
COMPONENTS REQUIRED:
THEORY:
Decoder:
A binary decoder is a logic circuit with n inputs and 2noutputs. The decoder also has an enable input
which makes output zero when it is asserted zero. Only one output is asserted high at a time. In 2-4
decoder, the data input is two bit in size. The two-bit data input can have 4 combinations and for
each input combination, one of the 4 data output is asserted high. The construction of such a type
of circuit is done using sum of product expression. Large decoders can be built either using sop
expressions or from smaller decoders.
Encoder:
A binary encoder encodes information from 2ninputs into an n bit code. Only one bit in the input is
asserted high at a time and the output tells which input bit is high. The encoders are used to reduce
the number of bits needed to represent given information. This allows economical implementation
of logic circuit with fewer wires. A special form of encoder circuit is the priority encoder circuit in
which more than one bit in the input is high. A circuit output follows a definitive priority and
accordingly the output is made high.
Encoder:
REALTIME APPLICATIONS:
VIVA QUESTIONS:
1. Give any three applications of encoder in digital electronics?
RESULT:
Flip Flop:
Delay(D) IC7474: RS flip flop IC7471
SYNCHRONOUS COUNTER
EXP NO: DESIGN AND IMPLEMENTATION OF ASYNCHRONOUS AND
DATE: SYNCHRONOUS COUNTERS USING FF IC’S AND SPECIFIC
COUNTER IC
AIM:
OBJECTIVE:
To understand and implement asynchronous and synchronous counters using suitable flip flop.
COMPONENTS REQUIRED:
1. 7476,7408 2
2. 74LS90 1
4. Connecting wires As
required
THEORY:
Flip Flop:
A flip flop is a storage element that changes its output state at the edge of a controlling clock
signal. Flip flop responds to active edge of the clock. For the reason mentioned, flip flops are
often referred to as edge triggered flip flop in contrast to the latch which are level sensitive. JK
flip flop is one whose output Q will be logic one if J = 1 and K = 0 and output Q will be logic
zero if J = 0 and K = 1.
Counter:
A counter is a circuit with a set of flip flops which counts the number of pulses at a given
clock input. At any instance, the number of pulses received is shown in the counter outputs.
In an asynchronous counter, the external clock, input triggers only the first flip flop. The
second and further stages are triggered by the outputs of the previous stages. In synchronous
counters, all the flip-flop are triggered by individual clock pulses.
ASYNCHRONOUS COUNTER
SPECIFIC COUNTER IC
PROCEDURE:
REALTIMEAPPLICATIONS:
ASYNCHRONOUS COUNTERS:
Digital Timers:
SYNCHRONOUS COUNTERS:
Traffic Light Controllers:
Binary Coded Decimal (BCD) Counters:
VIVA QUESTIONS:
1. Write any three applications of synchronous counter?
RESULT:
Flip Flop:
Delay(D) IC7474:
Shift Register:
Circuit Diagram:
EXP NO: DESIGN AND IMPLEMENTATION OF SHIFT REGISTER
DATE: CIRCUITS IN SISO, SIPO, PISO, PIPO MODES
AIM:
To design and implement a 4-bit shift register in SISO, SIPO, PISO, PIPO modes using suitable ICs
OBJECTIVE:
To implement a circuit which performs SISO, SIPO, PISO, PIPO shift using control signals.
COMPONENTS REQUIRED:
1 7474,7408,7432,7402 2
THEORY:
Flip Flop: A flip flop is a storage element that changes its output state at the edge of a
controlling clock signal. Flip flop responds to active edge of the clock. For the reason
mentioned, flip flops are often referred to as edge triggered flip flop in contrast to the
latch which are level sensitive. The output of the Delay flip flop, as the name suggests,
follows the inputs after a delay. RS flip flop is one whose output Q will be logic one if
S = 1 and R = 0 and output Q will be logic zero if S = 0 and R = 1. The state S = 0 and
R = 0 will make the flip flop to retain its past state and S = 1 and R = 1 is not allowed
in RS flip flop
Shift Register: A flip flop is used to store a single bit of information. When a set of flip
flops is used to store n bit of information, we refer the circuit as register. A register which
gives an option of shifting its contents is referred to as shift register. A shift register can
serially shift its data when it is given inputs serially or parallely. Similarly, a shift register
can parallely shift its data when it is given inputs serially or parallely. Respectively, such
circuits are referred to as Serial Input Serial Output (SISO) shift register, Parallel Input
Serial Output (PISO) shift register, Serial Input Parallel Output (SIPO) shift register,
Parallel Input Parallel Output (PIPO) shift register. The circuit specified is capable of
performing all four functions.
Characteristic Table:
D Flip Flop:
REALTIME APPLICATIONS:
SISO (Serial-In Serial-Out) Shift Register:
• Used in applications where data needs to be transmitted or processed one bit at a time, such as serial
communication systems.
Summary of Modes:
Mode Data Input Data Output Description
SISO Serial Serial Data shifts in and out one bit at a time.
SIPO Serial Parallel Data shifts in serially, but output is parallel.
PISO Parallel Serial Data is loaded in parallel, shifted out serially.
PIPO Parallel Parallel Data is loaded and read out in parallel.
VIVA QUESTIONS:
RESULT:
Multiplexer (4 -1):
Circuit Diagram: Truth Table:
De-Multiplexer:
Circuit Diagram: Truth Table:
EXP NO: MULTIPLEXER AND DE MULTIPLEXER CIRCUITS
DATE :
AIM:
(a) Multiplexer
To design and implement a 4 : 1 Multiplexer circuit using ICs and to verify its truth table.
(b) De-Multiplexer
To design and implement a 1 : 4 De-Multiplexer circuit using ICs and to verify its
truth table
OBJECTIVE:
To understand and implement the concept of tracking one input from multiple inputs and re
tracking the same.
COMPONENTS REQUIRED:
THEORY:
Multiplexer:
A Multiplexer circuit is basically a data selector circuit. The circuit routes 2 ninputs to
one output. This is accomplished using n select lines. In figure is shown, a 4 – 1
multiplexer circuit which routes 4 input to one output using two select lines. Two select
lines can be connected in four different options. Each combination routes one of the input
to the output. Still larger multiplexers can be implemented using the multiplexer circuit
shown in the figure, i.e. 8 – 1 multiplexer can be implemented using two 4 – 1
multiplexers. The most basic multiplexer circuit is a 2 – 1 multiplexer circuit. The most
striking feature of multiplexer circuit is any logic function can be implemented using
multiplexer circuit.
De-Multiplexer:
The circuit which performs exactly the opposite function of Multiplexer is referred to as de-
multiplexer circuit. A de-multiplexer has one input and 2noutput with n select lines. The input
is routed to one of the output according to the combination selected in the n
select line. A decoder circuit can be modified to perform as de-multiplexer if the input of
the decoder is made as the select lines for the de-multiplexer and the enable input of the
decoder is made as the input to the de-multiplexer.
Multiplexer:
1. Using suitable ICs, design a logic circuit using the multiplexer concept and construct the truth table.
2. The truth table is then verified
De-Multiplexer:
1. Using suitable ICs, design a logic circuit using the de-multiplexer concept and construct the truth table.
2. The truth table is then verified
REALTIME APPLICATIONS:
Multiplexer:
1. Data Routing in Communication Systems
2. Analog-to-Digital Conversion
Demultiplexer:
1. Data Demultiplexing in Communication
2. Analog Switching
VIVA QUESTIONS:
RESULT:
Illustrations:
Basic Theorems:
Theorems involving single variable
only: Operations with 0 and 1:
X + 0 = X … (1) X . 1 = X … (1a)
X + 1 = 1 … (2) X . 0 = 0 … (2a)
Idempotent Laws:
X + X = X … (3) X . X = X … (3a)
Involution Law:
(X’)’ = X … (4)
Laws of complementarity
X + X’ = 1 … (5) X . X’ = 0 … (5a)
Simplification theorems:
XY + XY’ = X … (6) (X + Y)(X + Y’) = X …
(6a) X + XY = X … (7) X(X + Y) = X … (7a) (X
+ Y’)Y = XY … (8) XY’ + Y = X + Y … (8a)
De Morgan’s laws:
(X + Y)’ = X’Y’
(XY)’ = X’ + Y’
Consensus theorem:
XY + X’Z + YZ = XY + X’Z
Associative Laws
(XY)Z = X(YZ) = XYZ … (10)
(X + Y) + Z = X + (Y + Z) = X + Y + Z …
(10a) Distributive Laws X(Y
+ Z) = XY + XZ … (11)
X + YZ = (X + Y)(X + Z) … (11a)
Theorem (for factoring and multiplying
out) (X + Y)(X’ + Z) = XZ + X’Y … (12)
EXP NO:
DATE : EXPERIMENTAL VERIFICATION OF BOOLEAN ALGEBRA
AIM:
(a) To verify the laws and theorems of Boolean Algebra experimentally
(b) To implement the given Boolean expression with minimum number of gates
OBJECTIVE:
To understand experimentally the minimization techniques of a Boolean function using the
laws of Boolean algebra and implementing the same.
COMPONENTS REQUIRED:
THEORY:
The basic mathematics behind the logic design of digital system is Boolean algebra.
Devices making up any digital system are two-state devices (transistors with high or low
value at the output) which take up two values at any instant. Boolean algebra in which the
variables assuming only two possible instants is a special case of Boolean algebra, referred
to as switching algebra. George Boole, an English mathematician and philosopher introduced
the concept of Boolean algebra in the year 1847. Claude Elwood Shannon, an American
mathematician, electronic engineer and cryptographer first applied Boolean algebra to the
design of switching circuits in 1939.
Suppose, a variable, say X or Y is used to represent a Boolean variable – now, it can take
two values either 0 or 1. Although the values look like binary values, they are not, rather they
represent two values – either Low or High. H or T can be used instead of 0 or 1. Most of the
basic theorems and laws of Boolean algebra are very similar to ordinary algebra with some minor
modifications. The basis of applying Boolean algebra is to reduce the number of literals present
in the resulting sum of product or product of sum expressions which would result in eventual
economical implementations.
Circuit Diagrams:
Theorems involving single variable only:
PROCEDURE:
1. Using the logic expression, construct the logic diagram using suitable ICs
2. The truth table is developed for the logic diagram and the same is verified
REALTIME APPLICATIONS:
VIVA QUESTIONS:
1. Write any three applications of Boolean algebra in day to day life?
AIM:
a) Inverting and Non-inverting Amplifier
To design an inverting amplifier using IC 741 with closed loop gain of -10, to amplify an input sine wave of
2 V peak to peak of 1 kHz frequency.
To design a Non-inverting amplifier using IC 741 with closed loop gain of 11, to amplify an input sine wave
of 2 V peak to peak of 1 kHz frequency.
b) Summer Circuits
To construct an inverting summing amplifier with the given input voltages V1, V2 and V3 using IC 741.
To construct a Non-inverting summing amplifier with the given input voltages V1, V2 and V3 using IC 741.
OBJECTIVE :
To understand basic applications of op-amp in closed loop.
COMPONENTS REQUIRED:
IC 741 1
THEORY:
Linear Integrated Circuit is a solid state device capable of operating over a wide range of input
signals as against digital IC whose input and output are constrained to discrete levels. The most popular
linear IC is the operational amplifier (Op-Amp). The scope of Linear ICs cover a large area. Linear ICs are
employed in audio amplifiers, Analog to Digital convertors, averaging amplifiers, differentiators, DC
amplifiers, integrators, multivibrators, oscillators, audio filters, and sweep generators. Op-Amp can be
operated either in the open loop mode or in the closed loop mode. The most common and simplest way of
operating an Op-Amp is in the open loop mode, where the Op-Amp has limited number of applications like
voltage comparator, zero crossing detector etc. In open loop mode, Op-Amp behaves as a switch as the
output assumes one of the two possible states (positive and negative saturation). Op-Amp is operated in
closed loop mode. The two important negative feedback circuits are inverting and non-inverting amplifying
circuits.
Inverting and Non-inverting amplifier:
In the inverting mode, the output voltage is fed back to the inverting input terminal through Rf –
R1 network where, Rf is the feedback resistor and input voltage is applied to the inverting input
terminal through resistor R1. The non-inverting input terminal is grounded. The output undergoes
180 degree phase shift, hence the name If the signal is applied to the non-inverting input terminal
and feed back is maintained as in the previous case, the resulting output would not be inverted.
Hence the circuit connected in this manner is referred to as non-inverting amplifier. The voltage
source at the inverting input terminal is shorted for the circuit to work as non
inverting amplifier.
Summer:
When an Op-Amp is used to add signals at its input, the resulting circuit is referred to as summing
amplifier. If the signals to be added are applied at the inverting input terminal the circuit is referred
to as inverting summing amplifier. We also have a circuit which adds the signals applied at its non-
inverting input.
PROCEDURE:
1. Implement Inverting Amplifier and non-inverting amplifier circuit from the given specification.
2. Note down the readings ( Amplitude in volts & time in sec ).
3. Construct the adder circuit for inverting and non-inverting configuration.
4. Note down the readings.
REALTIME APPLICATIONS:
1.Audio Amplifiers
2,Signal Conditioning
VIVA QUESTIONS:
5. How does a non-inverting amplifier achieve a positive gain without signal inversion?
RESULT:
Circuit Diagrams:
Implementation of Differentiator and Integrator:
Implementation of Inverting Comparator:
OBJECTIVE:
To understand basic applications of operational amplifier in open loop and close loop
COMPONENTS REQUIRED:
1. IC 741 1
THEORY:
Linear Integrated Circuit is a solid state device capable of operating over a wide range of input
signals as against digital IC whose input and output are constrained to discrete levels. The most
popular linear IC is the operational amplifier (Op-Amp). The scope of Linear ICs cover a large
area. Linear ICs are employed in audio amplifiers, Analog to Digital convertors, averaging
amplifiers, differentiators, DC amplifiers, integrators, multivibrators, oscillators, audio filters,
and sweep generators. Op-Amp can be operated either in the open loop mode or in the closed
loop mode. The most common and simplest way of operating an Op-Amp is in the open loop
mode, where the Op-Amp has limited number of applications like voltage comparator, zero
crossing detector etc.
Differentiator and Integrator:
As the name says, the circuit performs the mathematical differentiation of the input signal.
At high frequencies, differentiator may become unstable and gives rise to oscillations. As the
input impedance is formed by a capacitor, the input impedance is inversely proportional to
the frequency which makes the circuit sensitive to high frequency noise at high frequencies
as the input frequency decreases. The time period of the output waveform is governed by
RfC1 time constant.
If the capacitor and resistor are interchanged in the differentiator circuit, the resulting circuit
is referred to as an integrator. The circuit performs the mathematical integration of the input
signal applied. The low frequency gain can be limited by connecting a resistor parallel to the
feedback capacitor. This provides dc stabilization.
Comparator:
As the name specifies, the circuit comparing the input signal applied at one of its input
terminals with a known reference voltage is referred to as comparator. Since there are two
input terminals in an Op-Amp, accordingly the circuit is referred to as inverting and non
inverting comparator.
Non-inverting Comparator:
The input voltage is applied at the non-inverting input and the known reference voltage is
applied at the inverting input terminal. The output voltage will be at the negative saturation if
the input voltage is less than the reference voltage and the output voltage will be at the positive
saturation if the input voltage is more than the reference voltage.
Inverting Comparator:
The input voltage is applied at the inverting input and the known reference voltage is
applied at the non-inverting input. The circuit behaves exactly opposite to that of non
inverting comparator.
PROCEDURE:
1. Construct Differentiator and Integrator circuit using the design values
2. The connections are given as per the circuit diagram
3. Note down the readings
4. Similarly construct an Inverting Comparator & Non-inverting Comparator circuit using the design values
and note down the values.
REALTIME APPLICATIONS:
Differentiator:
1. Signal Processing in Communication Systems:
2. Edge Detection in Image Processing:
Integrator:
1. Audio Frequency Response Shaping:
2. DC Offset Removal:
Inverting Comparator:
1. Zero Crossing Detector:
2. Pulse Width Modulation (PWM):
Non-inverting Comparator:
1. Voltage Comparator with Hysteresis:
2. Overvoltage/Undervoltage Detection:
VIVA QUESTIONS:
1. List any three applications of a comparotor.
RESULT:
Circuit Diagram:
Mono-stable Multivibrator:
AIM:
(a) Astable Multivibrator
To design and implement a Monostasble Multivibrator using 555 timer IC to obtain
an output waveform with 1 kHz frequency.
OBJECTIVE:
To understand and implement timer circuits using 555 timer.
COMPONENTS REQUIRED:
1. 555 timer IC 1
4. Bread board 1
6. Oscilloscope 1
THEORY:
555 timer, as the name indicates, used to generate time delay ranging from
microseconds to hours. 555 timer has wide range of applications which include oscillator,
pulse generator, ramp and square wave generator, mono-shot multivibrator, burglar
alarm, traffic light control and voltage monitor etc.
Astable Multivibrator:
The connection diagram for making 555 timer work in the monostable mode is shown in the
diagram. Once triggered, the timer holds on in the high state until time T (T is roughly 1.1
RC) elapses. A negative going trigger pulse will make the output become low and the output
continue to remain in this state until a negative going trigger is applied to trigger input. This
is for this reason the circuit is referred to as mono-stable multi-vibrator (students are advised
to refer to standard text for further reference).
Astable Multivibrator:
External trigger is not required to change the state of the internally connected flip flop, hence the name. The
charging time and discharge time can be adjusted and the duty cycle of designer’s convenience can be had
with the help of modified circuit for astable multivibrator.
PROCEDURE:
(i) Construct the designed circuit and the connections are given as per the circuit diagram
(ii) The waveforms are noted down
REALTIME APPLICATIONS:
Astable Multivibrator:
1. Pulse Generator:
2. Oscillator:
Monostable Multivibrator:
1. Pulse Width Modulation (PWM):
2. Debouncing Switches:
VIVA QUESTIONS:
1. List any three applications of Astable Multivibrator using a 555 timer
2. How can you calculate the frequency and duty cycle of the output waveform in Astable mode?
RESULT:
PINDIAGRAM: 566IC
CIRCUIT DIAGRAM:
EXP NO: VOLTAGE TO FREQUENCY CHARACTERISTICS OF NE/SE 566 IC
DATE:
AIM:
To set up voltage controlled oscillator using IC566 and plot the waveforms.
OBJECTIVES:
To construct a VCO using IC566 using IC566.
COMPONENTS REQUIRED:
1. Multimeter 1
3. Capacitors 1nF,47nF 1
4. Bread board 1
6. Oscilloscope 1
THEORY :
VCO is an oscillator whose oscillating frequency varies in response to a control voltage Vc. NE/SE566
is a commonly available VCO. The frequency of oscillation is determined by an externally connected
resistor R1 and capacitor C1.The control voltage is applied at the control terminal (Pin5) .The triangular
voltage is obtained at Pin4 which is generated by alternately charging the capacitor C1 by one current
source and discharging it linearly through another current source. The amount of charge and discharge
voltage swing is determined by the Schmitt trigger. The Schmitt trigger also provides the square wave
output at pin3.
The output voltage swing of the Schmitt trigger is set in the levels Vcc and 0.5Vcc.Timing capacitor
C1 is charged linearly or discharged by a constant current source. The current value can be controlled
in two ways either by changing the control voltage Vc given at the modulating input(pin5) or by
changing the timing resistor R1 connected externally .The voltage available at pin6 is same that of
pin5 . During charging of C1,when the voltage across C1 exceeds 0.5Vcc ,the Schmitt trigger
switches to LOW (0,5Vcc) and the capacitor starts discharging when the voltage across C1 reduce
to 0.25Vcc ,the Schmitt trigger switches to HIGH (Vcc) .
PROCEDURE:
REALTIME APPLICATIONS:
Frequency Synthesis in PLLs (Phase-Locked Loops):
Frequency Modulation (FM) Transmitters and Receivers:
Radar Systems:
VIVA QUESTIONS:
1. Write the applications of Voltage-Controlled Oscillator (VCO)?
RESULT:
LM 317 PIN DIAGRAM:
CIRCUIT DIAGRAM:
AIM:
OBJECTIVES:
After completion of this experiment the student will be able to construct variable power supply
using IC LM317 and must have knowledge about LM317.
COMPONENTS REQUIRED:
1. Oscilloscope 1
2. Multimeter 1
Variable Power Supply (0-30V)
3. 1
LM 317
4. 1
8. Bread board 1
THEORY:
IC LM 317 is an adjustable linear voltage regulator. LM 317 has 3 pin. Input, Output and adjustment.
Its output voltage range is from 1.25 - 37 V and maximum output current is 1.5A. The device is conceptually
an op-amp with relatively high output current capacity. The non-inverting input of the op-amp is the
adjustment pin while the inverting input is set by an internal voltage reference of 1.25V. A resistive voltage
divider between the output and ground configures the op-amp as a non-inverting amplifier. So that the
voltage of the output pin is continuously adjusted to a fixed amount of reference voltage. In the circuit
transformer steps down to AC 230V to 12V and is applied to bridge rectifier diodes D1 to D4. C1 and C2
are filter capacitors. Capacitor C3 is for the better performance of filter IC. The output voltage from IC
depending on the voltage ADJ pin of the IC. The voltage across variable resistor R2 controls the DC output.
Vout = 1.25 (1 + R1 / R2 ) . By varying the resistor R2 DC output voltage can be varied.
PROCEDURE:
REALTIME APPLICATIONS:
• Adjustable Power Supply
• Battery Chargers
VIVA QUESTIONS:
RESULT:
Circuit Diagram:
Design:
Observations:
UTP = LTP=
Graph:
EXP NO: SCHMITT TRIGGER
DATE:
AIM: To design and setup a Schmitt trigger, plot the input output waveforms and measure
VUT and VLT.
OBJECTIVES: After completion of this experiment, student will be able to design and setup
a Schmitt trigger circuit using OP AMP.
COMPONENTS REQUIRED:
THEORY:
It is a regenerative comparator or it is a comparator with hysteresis. This circuit uses
positive feedback and the op-amp is operated in saturation. The output can take two values
+Vsat and –Vsat. When output = +Vsat, the voltage appearing at the non-inverting terminal
is VUT or UTP = +Vsat(R1/R1+R2) called the upper threshold point. Similarly, When
o u t p u t = - Vsat, the voltage appearing at the non-inverting terminal is VLT or LTP = -Vsat(
R1/R1+R2) called the lower threshold point. When Vin is greater than UTP, the output will
switch from +Vsat to –Vsat. Similarly, When Vin is less than LTP; the output will switch from
-Vsat to +Vsat which is shown in the graph. The difference between UTP-LTP is called
hysteresis. Hysteresis avoids false triggering of the circuit by noise. Hysteresis curve is the plot
of Vo versus Vin. Schmitt trigger circuit is used to convert any irregular wave into square wave.
PROCEDURE:
• Signal Conditioning
• Pulse Shaping
• Oscillator Circuits
VIVA QUESTIONS:
3. What happens when the input voltage is between the upper and lower threshold of a Schmitt
Trigger?
RESULT:
Meenakshi Sundararajan Engineering College
363, Arcot Road, Kodambakkam, Chennai - 600 024.
www.msec.edu.in
Email id: [email protected]