Counters and Registers

Counters and registers belong to the category of MSI sequential logic circuits. They have similar architec-
ture, as both counters and registers comprise a cascaded arrangement of more than one flipflop with or
without combinational logic devices. Both constitute very important building blocks of sequential logic,
and different types of counter and register available in integrated circuit (IC) form are used in a wide
range of digital systems. While counters are mainly used in counting applications, where they either
measure the time interval between two unknown time instants or measure the frequency of a given sig-
nal, registers are primarily used for the temporary storage of data present at the output of a digital cir-
cuit before they are fed to another digital circuit.

Counters
Counters are divided into two classes:

 Asynchronous and
 Synchronous counter.

Ripple (Asynchronous) Counter

A ripple counter is a cascaded arrangement of flip-flops where the output of one flip-flop drives the clock
input of the following flip-flop. The number of flip-flops in the cascaded arrangement depends upon the
number of different logic states that it goes through before it repeats the sequence, a parameter known
as the modulus of the counter.

In a ripple counter, also called an asynchronous counter or a serial counter, the clock input is applied
only to the first flip-flop, also called the input flip-flop, in the cascaded arrangement. The clock input to
any subsequent flip-flop comes from the output of its immediately preceding flip-flop.

As a natural consequence of this, not all flip-flops change state at the same time. The second flip-flop
can change state only after the output of the first flip-flop has changed its state. This time delay here
equals the sum of propagation delays of two flip-flops, the first and the second flip-flops. In general, the
nth flip-flop will changes state only after a delay equal to 𝑛 times the propagation delay of one flip-flop.
The term ‘ripple counter’ comes from the mode in which the clock information ripples through the
counter. It is also called an ‘asynchronous counter’ as different flip-flops comprising the counter do not
change state in synchronization with the input clock.

Modulus of a Counter
The modulus (MOD number) of a counter is the number of different logic states it goes through before it
comes back to the initial state to repeat the count sequence. An n-bit counter that counts through all its
natural states and does not skip any of the states has a modulus of 2𝑛 . Such counters have a modulus

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that is an integral power of 2, that is, 2, 4, 8, 16 and so on. These can be modified with the help of addi-
tional combinational logic to get a modulus of less than 2𝑛 .

To determine the number of flip-flops required to build a counter having a given modulus, identify the
smallest integer 𝑚 that is either equal to or greater than the desired modulus and is also equal to an in-
tegral power of 2. For instance, if the desired modulus is 10, which is the case in a decade counter, the
smallest integer greater than or equal to 10 and which is also an integral power of 2 is 16. The number
of flip-flops in this case would be 4, as 16 = 24 . On the same lines, the number of flip-flops required to
construct counters with MOD numbers of 3, 6, 14, 28 and 63 would be 2, 3, 4, 5 and 6 respectively. In
general, the arrangement of a minimum number of N flip-flops can be used to construct any counter
with a modulus given by the equation:

(2𝑁−1 + 1) ≤ 2𝑁 .

UP COUNTERS
Up counters give an output value that increases as the number of clock pulses increase. In this section,
ounters with the modulus of 4 and 8 are used to describe the operation of an up counter.

Mod Four counter

Circuit diagram

Figure 1.

Truth table
Table 1

2
Waveforms

Figure 2

Operation
The flip-flops are clocked at the negative edge of the clock pulse. All flip-flops are connected to operate
in the toggle mode. All the flips are reset using the clear signal. This is the first count of 002 = 010 as
seen in the truth table, table 1 and waveform of figure 2. On the first trailing edge of the clock-pulse,
flip-flop FF0 toggles. The second flip-flop is not connected to the clock hence the change does not affect
its output. The result is the second count of 012 = 110 . On the second trailing edge of the clock-pulse,
flip-flop FF0 toggles again. Its change from high to low causes the flip-flop FF1 to toggle. The result is the
third count of 102 = 210 . On the third trailing edge of the clock-pulse, flip-flop FF0 toggles again. This
change is low to high, hence FF1 remains in its previous state. The result is the fourth count of 112 =
310 . Therefore, the counter is a mod- 4 counter.

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Mod Eight counter
Circuit diagram

Figure 3: 3-bit binary ripple counter.

Truth Table
Table 2

4
Waveforms

Figure 4

Operation
All the flips are reset using the clear signal. This is the first count of 0002 = 010 as seen in the truth ta-
ble, table 2 and waveform of figure 4. On the first trailing edge of the clock-pulse, flip-flop FF0 toggles.
The second flip-flop is not connected to the clock hence the change does not affect its output so is flip-
flop FF2. The result is the second count of 0012 = 110 . On the second trailing edge of the clock-pulse,
flip-flop FF0 toggles again. Its change from high to low causes the flip-flop FF1 to toggle. This change in
FF1, being low to high, does not affect FF2. The result is the third count of 0102 = 210 . On the third
trailing edge of the clock-pulse, flip-flop FF0 toggles again. This change is low to high, hence FF1 remains
in its previous state so does FF2. The result is the fourth count of 0112 = 310 . On the fourth trailing
edge of the clock, FF0 toggles again. The transition is high to low which causes FF1 to also toggle. The
transition on FF1 is also high to low. The transition of FF1 causes FF2 to toggle to high state. The result is
the fifth count of 1002 = 410 . On the fifth trailing edge of the clock, FF0 toggles again. The transition is
from low to high, therefore FF1 and FF2 remain in their previous state. The result is the sixth count of
1012 = 510 . On the sixth trailing edge of the clock, FF0 toggles again. The transition is from high to low,
making FF1 also to toggle. The transition at the output of FF1 is from low to high, therefore FF2 remain
in its previous state. The result is the seventh count of 1102 = 610 . On the seventh trailing edge of the
clock, FF0 toggles again. The transition is from low to high, therefore FF1 and FF2 remain in their previ-
ous state. The result is the eighth count of 1112 = 710 . If the clock transition was to occur for the
eighth time, then all the flip-flops toggle to 0002 = 010 , ready to start another cycle (see figure 4.

5
Mod Sixteen Counter
Circuit diagram

Figure 5.

Waveforms

Figure 6.

Operation
The operation can be explained as we have done for the previous counters.

DOWN COUNTERS
On occasion, there is a need to count down in binary instead of counting up. To form a down-counter,
simply take the binary outputs from the 𝑄̅ outputs instead of the Q outputs. The principle of operation
of down counters can be demonstrated by the following mod- eight down counter.

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Mod-Eight Down- Counter
Circuit diagram

Figure 7: MOD-8 ripple down-counter

Figure 8: MOD-8 down-counter waveforms

Comparing the waveforms of the up-counter of Figure 4 to the down-counter of Figure 8, it can be seen
that they are exact complements of each other. That is easy to understand because the binary output is
taken from𝑄̅ instead of Q.

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Combined up- and down- counter

Figure 10: Three-bit UP/DOWN counter with a common clock input.

Figure 10 shows a three-bit binary UP/DOWN counter. This is only one possible logic arrangement. It has
a common control input. When this input is in logic ‘1’ state the counter counts downwards, and when it
is in logic ‘0’ state it counts upwards.

Propagation Delay in Ripple Counters

A major problem with ripple counters arises from the propagation delay of the flip-flops constituting the
counter. The situation becomes worse with increase in the number of flip-flops used to construct the
counter, which is the case in larger bit counters.

To understand the effect of propagation delay, let us consider the three-bit counter of figure 3 above.
When we analyze the circuit and waveforms, we see that Q0 toggles at each negative edge of 𝐶 ̅̅̅̅̅
𝑃0 . Q1
toggles at each negative edge of Q0, and Q2 toggles at each negative edge of Q1. The result is that the
outputs will “count” repeatedly from 000 up to 111 and then 000 to 111, as shown in Figure 4.

For example, look at clock pulse 3. The negative edge of causes Q0 to toggle LOW . . . which causes Q1 to
toggle LOW . . . which causes Q2 to toggle HIGH. There will definitely be a propagation delay between
the time that 𝐶̅̅̅̅̅
𝑃0 goes LOW until Q2 finally goes HIGH. From the tome the input clock signal changes
state to the time third flip-flop changes, the is a time period of THREE flip-flops time delays. The propa-
gation delay effect can be illustrated using the waveforms of figure 11.

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Figure 11: Effect of propagation delay on ripple counter outputs.

An increased propagation delay puts a limit on the maximum frequency used as clock input to the coun-
ter. The maximum clock frequency therefore corresponds to a time period that equals the total propa-
gation delay. If 𝑡𝑝𝑑 is the propagation delay in each flip-flop, then, in a counter with 𝑁 flip-flops having a
modulus of less than or equal to 2𝑁 , the maximum usable clock frequency is given by 𝑓𝑚𝑎𝑥 = 1/(𝑁 ×
𝑡𝑝𝑑 ) Often, two propagation delay times are specified in the case of flip-flops, one for LOW-to-HIGH
transition (𝑡𝑝𝐿𝐻 ) and the other for HIGH-to-LOW transition (𝑡𝑝𝐻𝐿 ) at the output. In such a case, the
larger of the two should be considered for computing the maximum clock frequency.

Shorted modulus Ripple Counter

If we are required to design MOD-5 counter, we can modify the MOD-8 counter so that when it reaches
the number 5 (101) all flip-flops will be Reset. The new count sequence will be 0–1–2–3–4–0–1–2–3–4–
0–, and so on. To get the counter to Reset at number 5 (binary 101), we will have to monitor the 20 and
22 lines and, when they are both HIGH, put out a LOW Reset pulse to all flip-flops. Figure 12 shows a cir-
cuit that can do this for us.

As you can see, the inputs to the NAND gate are connected to the 20 and22 lines, so when the number
5 (101) comes up, the NAND puts out a LOW level to Reset all flip-flops. The waveforms in Figure 13 il-
lustrate the operation of the MOD-5 counter of Figure 12.

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Figure 12: A block diagram of MOD-5 binary counter.

Figure 13: waveforms of MOD-5 binary counter

Ripple Counter ICs

Four-bit binary ripple counters are available in a single IC package. The most popular are the 7490, 7492,
and 7493 TTL ICs.

Figure 14 shows the internal logic diagram for the 7493 4-bit binary ripple counter. The 7493 has four J-K
flip-flops in a single package. It is divided into two sections: a divide-by-2, and a divide-by-8. The first
flip-flop provides the divide-by-2 with its 𝐶 ̅̅̅̅̅
𝑃0 input and 𝑄0 output. The second group has three flip-flops
cascaded to each other and provides the divide-by-8 via the input 𝐶𝑃1 and Q1Q2Q3 outputs. To get a
divide-by-16, you can externally connect 𝑄0 to 𝐶𝑃1 so that all four flip-flops are cascaded end to end, as
shown in Figure 15. Notice that two Master Reset inputs (MR1, MR2) are provided to asynchronously
Reset all four flip-flops. When MR1 and MR2 are both HIGH, all Q’s will be Reset to 0. (MR1 or MR2 must
be held LOW to enable the count mode.)

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Figure 14: Logic diagram and pin configuration for a 7493 4-bit ripple counter IC.

Figure 15: A 7493 connected as a MOD-16 ripple counter.

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Synchronous Counters
Synchronous counters eliminate the problem of propagation delay because all the clock inputs ’s (𝐶 ̅̅̅
𝑃)
are tied to a common clock input line, so each flip-flop will be triggered at the same time (thus, any Q
output transitions will occur at the same time.

If we want to design a 4-bit synchronous counter, we need four flip-flops, giving us a MOD-16 (24 ) bi-
nary counter. Keep in mind that because all the inputs receive a trigger at the same time, we must hold
certain flip-flops from making output transitions until it is their turn. To design the connection scheme
for the synchronous counter, let’s first study the output waveforms of a 4-bit binary counter to deter-
mine which flip-flops are to be held from toggling, and when.

From the waveforms in Figure 16, we can see that the 20 output is a continuous toggle off the clock in-
put line. The 21 output line toggles on every negative edge of the 20 line, but because ̅̅̅𝐶𝑃 of the second
0
flip-flop is also connected to the clock input, it must be held from toggling until the 2 line is HIGH. This
can be done simply by tying the J and K inputs to the 20 line, as shown in Figure 17). The same logic fol-
lows through for the 22 and 23 output lines. The 22 line must be held from toggling until the 20 and 21
lines are both HIGH. Also, the 23 line must be held from toggling until the 20 , 21 and 22 lines are all
HIGH.

To keep the appropriate flip-flops in the hold or toggle condition, their J and K inputs are tied together
and, through the use of additional AND gates, as shown in figure 17, the J-K inputs will be both 0 or 1,
depending on whether they are to be in the hold or toggle mode.

From Figure 17, we can see that the same clock input is driving all four flip-flops. The 21 flip-flop will be
in the hold mode 𝐽1 = 𝐾1 = 0until the 20 output goes HIGH, which will force 𝐽1 − 𝐾1 HIGH, allowing the
21 flip-flop to toggle when the next negative clock edge comes in.

Now, observe the output waveforms [Figure 16] while you look at the circuit design [Figure 17] to deter-
mine the operation of the last two flip-flops. From the waveforms, we see that the 22 output must not
be allowed to toggle until 20 and 21 are both HIGH. Well, the first AND gate in Figure 17 takes care of
that by holding 𝐽2 − 𝐾2 LOW. The same method is used to keep the 23 output from toggling until the 20 ,
21 and 22 outputs are all HIGH.

Figure 16: 4-bit MOD-16 synchronous counter output waveform.

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Figure 17: 4-bit MOD-16 synchronous counter circuit connections.

As you can see, the circuit is more complicated, but the cumulative effect of propagation delays through
the flip-flops is not a problem as it was in ripple counters. This is because all output transitions will occur
at the same time, because all flip-flops are triggered from the same input line. (There is a propagation
delay through the AND gates, but it will not affect the Q outputs of the flip-flops.)

As with ripple counters, synchronous counters can be used as down-counters by taking the output from
the inverted outputs and can form any modulus count by resetting the count to zero after some prede-
termined binary number has been reached.

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