Your Name
@ : xyz@[Link] | Tel. : +00-00000000000
Profile Summary______________________________________________________________
FPGA Developer and Front End VLSI trainer with 4+ years of experience in designing, debugging and testing FPGA
based digital systems and Embedded systems with SoC. Proficient at writing Verilog design sources, Verilog testbench
sources, VHDL sources, System Verilog sources, C based application projects for SoC. Designed and verified FPGA
system with Verilog and VHDL sources on Artix-7, Spartan 6, Zynq 7000 and Spartan 3AN families. Possess excellent
communication skills and ready to work in a challenging environment.
Experience___________________________________________________________________
Company name, City June 2017 – Present
[Verilog, VHDL, System Verilog, Embedded C] (3 Years)
● Developing FPGA based system for R&D
projects using Verilog.
● Developing SoC based Embedded System Design
for data communication from Console PC using UART interface and Microblaze.
● Designing of Communication interfaces for
Digilent PMOD ADC, PMOD DAC, PMOD accelerometer, PMOD LCD using SPI & IIC interfaces.
● Training students on Verilog, VHDL, SoC design.
Company name, City July 2016 – June 2017
[Verilog, VHDL, SoC with Microblaze, SDK] (1 Year)
● FPGA Developer for design of Gradient
Controller for MRI Machine.
● Development of Timing and Signal generation
unit for Synchronisation of Transmitter, Receiver and Gradient Controller.
● Designed a Communication bridge between
FPGA and Console PC using Ethernet.
Education____________________________________________________________________
Post-graduation University, City August 2014 - July 2016
Master of Technology in Electronics Engineering CGPA - 5.00
Graduation University, City July 2009 - July2013
Bachelor of Engineering in Electronics & Telecommunication Engineering Percentage - 50.00
Higher Secondary School February 2009
Mumbai Divisional Board Percentage - 50.00
Secondary School March 2007
Mumbai Divisional Board Percentage - 50.00
Technical Skills_______________________________________________________________
● Programming Technologies: Verilog, VHDL, SystemVerilog, Embedded C
● Verification Technologies: SystemVerilog, Universal Verification Methodology (UVM)
● IDEs: Vivado Design Suite, Xilinx ISE, Vivado EDK, Vivado SDK, Modelsim, Model based design
● FPGA Families experience: Artix 7, Spartan 6, Zynq 7000, Spartan 3AN
● Communication Interfaces: SPI, UART, IIC, Ethernet
● Debugging Tools: ILA, VIO, Chipscope, Software debugging with Vivado SDK
Projects & Awards____________________________________________________________
Design of Gradient Controller and Timing and Signal Generation Unit for MRI Machine
● FPGA based Gradient Controller to generate gradient waveforms necessary to select a particular slice of the
patient using an MRI machine
● The Waveform data is being communicated to the FPGA system from Console PC using Ethernet
● A TSG(Timing and Signal Generator) unit to achieve synchronization between Transmitter, Receiver and
Gradient Controller
Design of 32-bit RISC Processor using Verilog for Parallel Operation with Microblaze
● Design of 32-bit Custom RISC Processor for Artix 7 Series FPGA
● Design of different Neuromorphic spikes for the Neuromorphic Processor
● Design of SPI interface for generation of Neuromorphic Spikes on FPGA using 12-bit DAC.
Development of Toolchain for Full development of Lab-on-Chip (LoC) devices.
● Design of COMSOL based design flow for development of LoC devices capable of detecting Bacteria,
Protozoans and Virus responsible for the Water borne diseases.
● FPGA based system for detection of the phase change between Bio-signals.
.
IEEE Conference paper reviewer for IBSSC 2019 (IEEE Bombay Section)
● Paper reviewer for the IEEE Conference organized by IEEE Bombay Section.
Gold Medalist
● Awarded with Gold medal for excellent performance during Graduation and Post graduation.
Project Selection in Vishwakarma Chhatra Award Regional Convention organized by AICTE
● The Water Quality Monitoring System developed by team of researcher lead by me is chosen for the
Vishwakarma Chhatra Award Regional Convention.
Texas Instrument Innovation Challenge
● Served as Elite Mentor for the TI innovation Challenge for the Year 2018, 2019 and 2020.
Research Paper Publications____________________________________________________
● Publication 1 (Follow IEEE reference format for adding Publication details)
● Publication 2 (Follow IEEE reference format for adding Publication details)
City:
Date: (Your Name)
