TXU0104

SCES937A – MAY 2021 – REVISED SEPTEMBER 2021

TXU0104 4-Bit Fixed Direction Voltage-Level Translator with Schmitt-Trigger Inputs

and 3-State Outputs

1 Features 2 Applications
• Fully configurable dual-rail design allows each port • Eliminate slow or noisy input signals
to operate from 1.1 V to 5.5 V • Driving indicator LEDs or buzzers
• Up to 200 Mbps support for 3.3 V to 5.0 V • Debouncing a mechanical switch
• Schmitt-trigger inputs allows for slow and noisy • General purpose I/O level shifting
inputs • Push-pull level shifting (UART, SPI, JTAG, and so
• Inputs with integrated static pull-down resistors forth)
prevent channels from floating
• High drive strength (up to 12 mA at 5 V)
3 Description
• Low power consumption TXU0104 is a 4-bit, dual-supply noninverting fixed
– 2.5 µA maximum (25°C) direction voltage level translation device. Ax pins
– 6 µA maximum (–40°C to 125°C) are referenced to VCCA logic level, OE pin can be
• VCC isolation and VCC disconnect (Ioff-float) feature referenced to either VCCA or V CCB logic levels, and Bx
– If either VCC input is <100 mV or disconnected, pins are referenced to VCCB logic levels. The A port
all outputs are disabled and become high- is able to accept input voltages ranging from 1.1 V to
impedance 5.5 V, while the B port can also accept input voltages
• Ioff supports partial-power-down mode operation from 1.1 V to 5.5 V. Fixed direction data transmission
• Control logic (OE) with VCC(MIN) circuitry allows for can occur from A to B or B to A when OE is set to
control from either A or B port high in reference to either supply. When OE is set to
• Pinout compatible with TXB family level shifters low, all output pins are in the high-impedance state.
• Available in other variants that support common See Device Functional Modes for a summary of the
applications: TXU0204, TXU0304 operation of the control logic.
• Operating temperature from –40°C to +125°C Device Information(1)
• Latch-up performance exceeds 100 mA per JESD PART NUMBER PACKAGE BODY SIZE (NOM)
78, class II
TXU0104BQA VQFN (14) 3.00 mm × 2.50 mm
• ESD protection exceeds JESD 22
TXU0104PW TSSOP (14) 5.00 mm × 4.40 mm
– 2500-V human-body model
TXU0104RUT UQFN (12) 2.00 mm × 1.70 mm
– 1500-V charged-device model
TXU0104DTR X2SON (12) 1.70 mm × 1.00 mm

(1) For all available packages, see the orderable addendum at

the end of the data sheet.

VCC(MIN) VCCA VCCB

OE

A1 B1Y

A2 B2Y

A3 B3Y

A4 B4Y

GND

TXU0104 Functional Block Diagram

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TXU0104
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Table of Contents
1 Features............................................................................1 9 Detailed Description......................................................20
2 Applications..................................................................... 1 9.1 Overview................................................................... 20
3 Description.......................................................................1 9.2 Functional Block Diagram......................................... 20
4 Revision History.............................................................. 2 9.3 Feature Description...................................................21
5 Related Products............................................................. 3 9.4 Device Functional Modes..........................................23
6 Pin Configuration and Functions—TXU0104 ............... 4 10 Application and Implementation................................ 24
7 Specifications.................................................................. 5 10.1 Application Information........................................... 24
7.1 Absolute Maximum Ratings ....................................... 5 10.2 Typical Application.................................................. 24
7.2 ESD Ratings .............................................................. 5 11 Power Supply Recommendations..............................25
7.3 Recommended Operating Conditions ........................6 12 Layout...........................................................................25
7.4 Thermal Information ...................................................6 12.1 Layout Guidelines................................................... 25
7.5 Electrical Characteristics ............................................7 12.2 Layout Example...................................................... 26
7.6 Switching Characteristics: Tsk, TMAX ..........................9 13 Device and Documentation Support..........................27
7.7 Switching Characteristics, VCCA = 1.2 ± 0.1 V.......... 10 13.1 Device Support....................................................... 27
7.8 Switching Characteristics, VCCA = 1.5 ± 0.1 V.......... 11 13.2 Documentation Support.......................................... 27
7.9 Switching Characteristics, VCCA = 1.8 ± 0.15 V........ 12 13.3 Receiving Notification of Documentation Updates..27
7.10 Switching Characteristics, VCCA = 2.5 ± 0.2 V........ 13 13.4 Support Resources................................................. 27
7.11 Switching Characteristics, VCCA = 3.3 ± 0.3 V........ 14 13.5 Trademarks............................................................. 27
7.12 Switching Characteristics, VCCA = 5.0 ± 0.5 V........ 15 13.6 Electrostatic Discharge Caution..............................27
7.13 Operating Characteristics....................................... 16 13.7 Glossary..................................................................27
7.14 Typical Characteristics............................................ 17 14 Mechanical, Packaging, and Orderable
8 Parameter Measurement Information.......................... 18 Information.................................................................... 27
8.1 Load Circuit and Voltage Waveforms........................18

4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from Revision * (May 2021) to Revision A (September 2021) Page

• Changed the status of the TXU0104BQA, TXU0104RUT, and TXU0104DTR devices from: Product Preview
to: Production Data ............................................................................................................................................ 1

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5 Related Products
TXU0x04 4-Bit TXU0x04 are 4-bit, dual-supply noninverting fixed direction voltage level translators. These
Unidirectional devices are compatible to the TXB0104 with the same pinout allowing for a drop in
Voltage-Level replacement. The OE pin can be referenced to either VCCA or VCCB logic levels allowing
Translators for one of the TXU0x04 devices to be used for fixed direction, high drive applications which
the TXB0104 is not recommended to support.
TXU0204 TXU0204 is a 4-bit, dual-supply noninverting fixed direction voltage level translators with 2
channels in the opposing direction commonly used for GPIO, UART, and JTAG translation.

VCC(MIN) VCCA VCCB

OE

A1 B1Y

A2 B2Y

A3Y B3

A4Y B4

GND

Figure 5-1. TXU0204 Functional Block Diagram

TXU0304 TXU0304 is a 4-bit, dual-supply noninverting fixed direction voltage level translators with 1
channel in the opposing direction commonly used for GPIO, SPI, and I2S translation.

VCC(MIN) VCCA VCCB

OE

A1 B1Y

A2 B2Y

A3 B3Y

A4Y B4

GND

Figure 5-2. TXU0304 Functional Block Diagram

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6 Pin Configuration and Functions—TXU0104

VCCB
VCCA
VCCA 1 14 VCCB

14
1
A1 2 13
B1Y A1 2 13 B1Y
3 12 B2Y
A2 A2 3 12 B2Y
Thermal
A3 4 11 B3Y A3 4
Pad 11 B3Y
A4 5 10 B4Y A4 5 10 B4Y
6 9 NC NC 6 9 NC
NC

8
GND
OE
GND 7 8 OE

Figure 6-1. PW 14-Pin TSSOP Top View Figure 6-2. BQA Package 14-Pin VQFN Transparent
Top View
OE

OE
12
VCCA 1 11 VCCB
VCCA 1 12 11 VCCB
A1 2 10 B1Y A1 2 10 B1Y

A2 3 9 B2Y A2 3 9 B2Y
A3 4 8 B3Y
A3 4 8 B3Y
A4 5 6 7 B4Y
A4 5 7 B4Y
GND

6
GND

Figure 6-3. RUT Package 12-Pin UQFN Transparent Figure 6-4. DTR Package 12-Pin X2SON
Top View Transparent Top View

Table 6-1. TXU0104 Pin Functions

PIN
I/O DESCRIPTION
Name PW, BQA RUT, DTR
A1 2 2 I Input A1. Referenced to VCCA.
A2 3 3 I Input A2. Referenced to VCCA.
A3 4 4 I Input A3. Referenced to VCCA.
A4 5 5 I Input A4. Referenced to VCCA.
B1Y 13 10 O Output B1. Referenced to VCCB.
B2Y 12 9 O Output B2. Referenced to VCCB.
B3Y 11 8 O Output B3. Referenced to VCCB.
B4Y 10 7 O Output B4. Referenced to VCCB.
GND 7 6 — Ground
NC 6, 9 — No internal connection.
Output Enable. Pull to GND to place all outputs in high-impedance mode. Pull
OE 8 12 I
to VCCA or VCCB to enable all outputs.
VCCA 1 1 — A-port supply voltage. 1.1 V ≤ VCCA ≤ 5.5 V
VCCB 14 11 — B-port supply voltage. 1.1 V ≤ VCCB ≤ 5.5 V
PAD — — Thermal pad. May be grounded (recommended) or left floating.

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7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN MAX UNIT
VCCA Supply voltage A –0.5 6.5 V
VCCB Supply voltage B –0.5 6.5 V
I/O Ports (A Port) –0.5 6.5
VI Input Voltage(2) I/O Ports (B Port) –0.5 6.5 V
OE –0.5 6.5

Voltage applied to any output in the high-impedance or power-off A Port –0.5 6.5
VO V
state(2) B Port –0.5 6.5
A Port –0.5 VCCA + 0.5
VO Voltage applied to any output in the high or low state(2) (3) V
B Port –0.5 VCCB + 0.5
IIK Input clamp current VI < 0 –20 mA
IOK Output clamp current VO < 0 –20 mA
IO Continuous output current –25 25 mA
Continuous current through VCC or GND –100 100 mA
Tj Junction Temperature 150 °C
Tstg Storage temperature –65 150 °C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress
ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Conditions. Exposure beyond the limits listed in Recommended Operating Conditions. may affect device
reliability.
(2) The input voltage and output negative-voltage ratings may be exceeded if the input and output current ratings are observed.
(3) The output positive-voltage rating may be exceeded up to 6.5 V maximum if the output current rating is observed.

7.2 ESD Ratings

VALUE UNIT
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2500
V(ESD) Electrostatic discharge V
Charged device model (CDM), per JEDEC specification JESD22-C101(2) ±1500

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

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7.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted) (1) (2) (3)
MIN MAX UNIT
VCCA Supply voltage A 1.08 5.5 V
VCCB Supply voltage B 1.08 5.5 V
VCCO = 1.1 V –1.5
VCCO = 1.4 V –3
VCCO = 1.65 V –4.5
IOH High-level output current mA
VCCO = 2.3 V –8
VCCO = 3 V –10
VCCO = 4.5 V –12
VCCO = 1.1 V 1.5
VCCO = 1.4 V 3
VCCO = 1.65 V 4.5
IOL Low-level output current mA
VCCO = 2.3 V 8
VCCO = 3 V 10
VCCO = 4.5 V 12
VI Input voltage (3) 0 5.5 V
Active State 0 VCCO
VO Output voltage V
Tri-State 0 5.5
TA Operating free-air temperature –40 125 °C

(1) VCCI is the VCC associated with the input port.

(2) VCCO is the VCC associated with the output port.
(3) All control inputs and data I/Os of this device have weak pulldowns to ensure the line is not floating when undefined external to the
device. The input leakage from these weak pulldowns is defined by the II specification indicated under Electrical Characteristics.

7.4 Thermal Information

TXU0104
THERMAL METRIC(1) PW (TSSOP) BQA (WQFN) RUT (UQFN) DTR (X2SON) UNIT
14 PINS 14 PINS 12 PINS 12 PINS
Junction-to-ambient thermal
RθJA 135.8 87.2 171.9 176.6 °C/W
resistance
Junction-to-case (top) thermal
RθJC(top) 65.0 90.0 100.4 84.1 °C/W
resistance
Junction-to-board thermal
RθJB 78.8 56.0 97.1 99.1 °C/W
resistance
Junction-to-top characterization
YJT 15.6 9.8 10.9 2.6 °C/W
parameter
Junction-to-board characterization
YJB 78.2 56.0 95.5 98.9 °C/W
parameter
Junction-to-case (bottom) thermal
RθJC(bottom) N/A 33.0 N/A N/A °C/W
resistance

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.

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7.5 Electrical Characteristics

over operating free-air temperature range (unless otherwise noted)(1) (2)
Operating free-air temperature (TA)
PARAMETER TEST CONDITIONS VCCA VCCB 25°C –40°C to 85°C –40°C to 125°C UNIT
MIN TYP MAX MIN TYP MAX MIN TYP MAX
1.1 V 1.1 V 0.44 0.88 0.44 0.88
1.4 V 1.4 V 0.60 0.98 0.60 0.98
1.65 V 1.65 V 0.76 1.13 0.76 1.13
Data Inputs
(Ax, Bx) 2.3 V 2.3 V 1.08 1.56 1.08 1.56 V
(Referenced to VCCI)
3V 3V 1.48 1.92 1.48 1.92
4.5 V 4.5 V 2.19 2.74 2.19 2.74
Positive-
going input- 5.5 V 5.5 V 2.65 3.33 2.65 3.33
VT+
threshold 1.1 V 1.1 V 0.44 0.88 0.44 0.88
voltage
1.4 V 1.4 V 0.60 0.98 0.60 0.98
1.65 V 1.65 V 0.76 1.13 0.76 1.13
OE
(Referenced to VCCA 2.3 V 2.3 V 1.08 1.56 1.08 1.56 V
or VCCB)
3V 3V 1.48 1.92 1.48 1.92
4.5 V 4.5 V 2.19 2.74 2.19 2.74
5.5 V 5.5 V 2.65 3.33 2.65 3.33
1.1 V 1.1 V 0.17 0.48 0.17 0.48
1.4 V 1.4 V 0.28 0.59 0.28 0.59
1.65 V 1.65 V 0.35 0.69 0.35 0.69
Data Inputs
(Ax, Bx) 2.3 V 2.3 V 0.56 0.97 0.56 0.97 V
(Referenced to VCCI)
3V 3V 0.89 1.5 0.89 1.5
4.5 V 4.5 V 1.51 1.97 1.51 1.97
Negative-
going input- 5.5 V 5.5 V 1.88 2.4 1.88 2.4
VT-
threshold 1.1 V 1.1 V 0.17 0.48 0.17 0.48
voltage
1.4 V 1.4 V 0.28 0.59 0.28 0.59
1.65 V 1.65 V 0.35 0.69 0.35 0.69
OE
(Referenced to VCCA 2.3 V 2.3 V 0.56 0.97 0.56 0.97 V
or VCCB)
3V 3V 0.89 1.5 0.89 1.5
4.5 V 4.5 V 1.51 1.97 1.51 1.97
5.5 V 5.5 V 1.88 2.46 1.88 2.46
1.1 V 1.1 V 0.2 0.4 0.2 0.4
1.4 V 1.4 V 0.25 0.5 0.25 0.5
1.65 V 1.65 V 0.3 0.55 0.3 0.55
Data Inputs
(Ax, Bx) 2.3 V 2.3 V 0.38 0.65 0.38 0.65 V
(Referenced to VCCI)
3V 3V 0.46 0.72 0.46 0.72
4.5 V 4.5 V 0.58 0.93 0.58 0.93
Input-
threshold 5.5 V 5.5 V 0.69 1.06 0.69 1.06
ΔVT
hysteresis 1.1 V 1.1 V 0.15 0.41 0.15 0.41
(VT+ – VT-)
1.4 V 1.4 V 0.2 0.5 0.2 0.5
1.65 V 1.65 V 0.23 0.55 0.23 0.55
OE
(Referenced to VCCA 2.3 V 2.3 V 0.32 0.65 0.32 0.65 V
or VCCB)
3V 3V 0.39 0.72 0.39 0.72
4.5 V 4.5 V 0.57 0.97 0.57 0.97
5.5 V 5.5 V 0.69 1.18 0.69 1.18

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7.5 Electrical Characteristics (continued)

over operating free-air temperature range (unless otherwise noted)(1) (2)
Operating free-air temperature (TA)
PARAMETER TEST CONDITIONS VCCA VCCB 25°C –40°C to 85°C –40°C to 125°C UNIT
MIN TYP MAX MIN TYP MAX MIN TYP MAX
VCCO VCCO
IOH = –0.1 mA 1.1V – 5.5V 1.1V – 5.5V
– 0.1 – 0.1
IOH = –0.5 mA 1.1 V 1.1 V 0.82 0.82
High-level IOH = –3 mA 1.4 V 1.4 V 1 1
VOH output V
IOH = –4.5 mA 1.65 V 1.65 V 1.2 1.2
voltage (3)
IOH = –8 mA 2.3 V 2.3 V 1.7 1.7
IOH = –10 mA 3V 3V 2.2 2.2
IOH = –12 mA 4.5 V 4.5 V 3.7 3.7
IOL = 0.1 mA 1.1V – 5.5V 1.1V – 5.5V 0.1 0.1
IOL = 0.5 mA 1.1 V 1.1 V 0.27 0.27
IOL = 3 mA 1.4 V 1.4 V 0.35 0.35
Low-level IOL = 4.5 mA 1.65 V 1.65 V 0.45 0.45
VOL output V
voltage (4) IOL = 8 mA 2.3 V 2.3 V 0.7 0.7
IOL = 10 mA 3V 3V 0.8 0.8
IOL = 8 mA 4.5 V 4.5 V 0.55 0.55
IOL = 12 mA 4.5 V 4.5 V 0.8 0.8
OE
1.1V – 5.5V 1.1V – 5.5V -0.1 1.5 -0.1 1.5 -0.1 2 µA
VI = VCC or GND
Input leakage
II Data Inputs
current
(Ax, Bx) 1.1V – 5.5V 1.1V – 5.5V –0.1 1.5 –0.1 1.5 –2 2 µA
VI = VCCI or GND
A Port or B Port 0V 0 V - 5.5 V –1.5 1.5 –2 2 –2.5 2.5
Partial power
Ioff VI or VO = 0 V - 5.5 µA
down current 0 V - 5.5 V 0V –1.5 1.5 –2 2 –2.5 2.5
V
Floating Floating(5) 0 V - 5.5 V –1.5 1.5 –2 2 –2.5 2.5
supply Partial A Port or B Port
Ioff-float µA
power down VI or VO = GND 0 V - 5.5 V Floating(5) –1.5 1.5 –2 2 –2.5 2.5
current
A or B Port:
Tri-state VI = VCCI or GND
IOZ 1.1V – 5.5V 1.1V – 5.5V –0.3 0.3 –1 1 –2 2 µA
output current VO = VCCO or GND
OE = GND
1.1V – 5.5V 1.1V – 5.5V 1.5 2.5 6
VI = VCCI or GND
0V 5.5 V –0.3 –1 –1
VCCA supply IO = 0
ICCA 5.5 V 0V 1 1.5 3 µA
current
VI = GND
5.5 V Floating(5) 1.5 7 15
IO = 0
1.1V – 5.5V 1.1V – 5.5V 1.5 2.5 6
VI = VCCI or GND
0V 5.5 V 1 1.5 3
VCCB supply IO = 0
ICCB 5.5 V 0V –0.3 –1 –1 µA
current
VI = GND
Floating(5) 5.5 V 1.5 7 15
IO = 0
Combined
ICCA + VI = VCCI or GND
supply 1.1V – 5.5V 1.1V – 5.5V 2.5 3 6 µA
ICCB IO = 0
current
Control Input
Ci VI = 3.3 V or GND 3.3 V 3.3 V 2.75 3 3.5 pF
Capacitance

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7.5 Electrical Characteristics (continued)

over operating free-air temperature range (unless otherwise noted)(1) (2)
Operating free-air temperature (TA)
PARAMETER TEST CONDITIONS VCCA VCCB 25°C –40°C to 85°C –40°C to 125°C UNIT
MIN TYP MAX MIN TYP MAX MIN TYP MAX
OE = GND, VO =
Data I/O
Cio 1.65V DC +1 MHz 3.3 V 3.3 V 3 4 4 pF
Capacitance
-16 dBm sine wave

(1) VCCI is the VCC associated with the input port

(2) VCCO is the VCC associated with the output port
(3) Tested at VI = VT+(MAX)
(4) Tested at VI = VT-(MIN)
(5) Floating is defined as a node that is both not actively driven by an external device and has leakage not exeeding 10nA

7.6 Switching Characteristics: Tsk, TMAX

over operating free-air temperature range (unless otherwise noted)
Operating free-air
temperature (TA)
PARAMETER TEST CONDITIONS VCCI VCCO UNIT
-40°C to 125°C
MIN TYP MAX
3.0 V - 3.6 V 4.5 V - 5.5 V 200
1.65 V - 1.95 V 4.5 V - 5.5 V 150
1.1 V - 1.3 V 4.5 V - 5.5 V 30
Up Translation
50% Duty Cycle 1.65 V - 1.95 V 3.0 V - 3.6 V 100
Input 1.1 V - 1.3 V 3.0 V - 3.6 V 30
One channel
TMAX - Maximum switching 1.1 V - 1.3 V 1.65 V - 1.95 V 20
Mbps
Data Rate 20% of pulse > 4.5 V - 5.5 V 3.0 V - 3.6 V 125
0.7*VCCO
20% of pulse < 4.5 V - 5.5 V 1.65 V - 1.95 V 50
0.3*VCCO 4.5 V - 5.5 V 1.1 V - 1.3 V 10
Down Translation
3.0 V - 3.6 V 1.65 V - 1.95 V 50
3.0 V - 3.6 V 1.1 V - 1.3 V 10
1.65 V - 1.95 V 1.1 V - 1.3 V 10
3.0 V - 3.6 V 4.5 V - 5.5 V 3
1.65 V - 1.95 V 4.5 V - 5.5 V 10
1.1 V - 1.3 V 4.5 V - 5.5 V 42
Up Translation
1.65 V - 1.95 V 3.0 V - 3.6 V 8
Timing skew 1.1 V - 1.3 V 3.0 V - 3.6 V 42
between any 1.1 V - 1.3 V 1.65 V - 1.95 V 45
tsk - Output skew switching outputs on ns
the rising or falling 4.5 V - 5.5 V 3.0 V - 3.6 V 3
edge 4.5 V - 5.5 V 1.65 V - 1.95 V 10
4.5 V - 5.5 V 1.1 V - 1.3 V 42
Down Translation
3.0 V - 3.6 V 1.65 V - 1.95 V 8
3.0 V - 3.6 V 1.1 V - 1.3 V 42
1.65 V - 1.95 V 1.1 V - 1.3 V 45

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7.7 Switching Characteristics, VCCA = 1.2 ± 0.1 V

See Figure 8-1 and Table 8-1 for test circuit and loading. See Figure 8-2, Figure 8-3, and Figure 8-4 for measurement waveforms.
B-Port Supply Voltage (VCCB)
Test
PARAMETER FROM TO 1.2 ± 0.1 V 1.5 ± 0.1 V 1.8 ± 0.15 V 2.5 ± 0.2 V 3.3 ± 0.3 V 5.0 ± 0.5 V UNIT
Conditions
MIN TYP MAX MIN TYP MAX MIN TYP MAX MIN TYP MAX MIN TYP MAX MIN TYP MAX
-40°C to 85°C 3.3 96 0.5 43 0.5 37 0.5 32 0.5 30 0.5 31
A B
Propagation -40°C to 125°C 5.7 60 3.0 39 1.4 33 0.5 28 0.5 27 0.5 26
tpd ns
delay -40°C to 85°C 3.3 95 1.9 80 0.5 75 0.5 70 0.5 69 0.5 69
B A
-40°C to 125°C 5.7 60 4.1 51 2.9 48 1.8 45 1.5 44 1.3 44
-40°C to 85°C 28.8 133 28.5 130 28.4 133 28.8 137 28.4 143 18.7 211
OE A
-40°C to 125°C 43.3 133 43.3 130 43.7 130 44.7 131 45.4 134 31.8 140
tdis Disable time ns
-40°C to 85°C 32.5 150 27.6 117 25.8 110 22.5 104 22.1 112 20.1 181
OE B
-40°C to 125°C 48.3 149 43.2 120 40.8 113 36.8 104 36.5 107 33.8 111
-40°C to 85°C 24.1 237 22.1 229 21.4 230 21.3 232 21.7 235 22.7 244
OE A
-40°C to 125°C 34.9 156 33.3 167 32.0 169 31.7 173 32.0 177 34.2 187
ten Enable time ns
-40°C to 85°C 21.3 237 14.3 152 11.2 140 8.8 130 8.2 130 8.4 132
OE B
-40°C to 125°C 29.8 143 23.0 116 18.6 107 15.4 97 14.5 97 14.8 103

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7.8 Switching Characteristics, VCCA = 1.5 ± 0.1 V

See Figure 8-1 and Table 8-1 for test circuit and loading. See Figure 8-2, Figure 8-3, and Figure 8-4 for measurement waveforms.
B-Port Supply Voltage (VCCB)
Test
PARAMETER FROM TO 1.2 ± 0.1 V 1.5 ± 0.1 V 1.8 ± 0.15 V 2.5 ± 0.2 V 3.3 ± 0.3 V 5.0 ± 0.5 V UNIT
Conditions
MIN TYP MAX MIN TYP MAX MIN TYP MAX MIN TYP MAX MIN TYP MAX MIN TYP MAX
-40°C to 85°C 1.9 80 0.5 31 0.5 25 0.5 19 0.5 17 0.5 15
A B
Propagation -40°C to 125°C 4.1 51 1.6 31 0.5 25 0.5 20 0.5 18 0.5 16
tpd ns
delay -40°C to 85°C 0.5 43 0.5 31 0.5 28 0.5 26 0.5 25 0.5 24
B A
-40°C to 125°C 3.0 39 1.6 31 0.5 28 0.5 26 0.5 25 0.5 24
-40°C to 85°C 20.0 91 19.0 82 18.8 81 19.2 82 19.6 83 12.2 87
OE A
-40°C to 125°C 34.9 95 32.6 86 32.8 85 33.4 87 34.2 88 24.6 92
tdis Disable time ns
-40°C to 85°C 27.4 127 21.7 91 19.9 82 16.3 71 15.9 71 13.7 70
OE B
-40°C to 125°C 44.4 130 36.7 95 34.7 86 30.2 75 29.8 75 26.6 74
-40°C to 85°C 14.9 102 14.4 86 13.5 88 12.7 90 12.6 92 13.2 97
OE A
-40°C to 125°C 25.5 102 25.2 89 24.1 91 22.8 93 22.8 96 23.5 100
ten Enable time ns
-40°C to 85°C 17.9 175 12.7 80 9.1 69 6.1 57 4.9 53 4.5 54
OE B
-40°C to 125°C 26.6 135 21.0 81 16.8 71 12.5 60 10.8 56 10.4 57

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7.9 Switching Characteristics, VCCA = 1.8 ± 0.15 V

See Figure 8-1 and Table 8-1 for test circuit and loading. See Figure 8-2, Figure 8-3, and Figure 8-4 for measurement waveforms.
B-Port Supply Voltage (VCCB)
Test
PARAMETER FROM TO 1.2 ± 0.1 V 1.5 ± 0.1 V 1.8 ± 0.15 V 2.5 ± 0.2 V 3.3 ± 0.3 V 5.0 ± 0.5 V UNIT
Conditions
MIN TYP MAX MIN TYP MAX MIN TYP MAX MIN TYP MAX MIN TYP MAX MIN TYP MAX
-40°C to 85°C 0.5 75 0.5 28 0.5 22 0.5 17 0.5 14 0.5 12
A B
Propagation -40°C to 125°C 2.9 48 0.5 28 0.5 23 0.5 17 0.5 15 0.5 13
tpd ns
delay -40°C to 85°C 0.5 37 0.5 25 0.5 22 0.5 19 0.5 19 0.5 18
B A
-40°C to 125°C 1.4 33 0.5 25 0.5 23 0.5 20 0.5 19 0.5 19
-40°C to 85°C 17.2 79 14.7 67 14.5 65 14.3 65 14.4 66 8.5 68
OE A
-40°C to 125°C 30.9 83 28.0 71 26.6 69 27.5 70 27.2 71 20.0 73
tdis Disable time ns
-40°C to 85°C 25.4 121 18.7 81 16.5 71 12.8 60 12.5 58 9.8 55
OE B
-40°C to 125°C 41.7 123 34.0 86 30.3 76 26.2 64 25.3 62 21.8 59
-40°C to 85°C 10.9 88 9.5 66 9.4 63 8.6 65 8.2 66 8.1 69
OE A
-40°C to 125°C 20.3 87 19.0 69 18.9 67 17.6 68 17.1 70 17.1 73
ten Enable time ns
-40°C to 85°C 16.7 177 10.4 75 8.1 58 4.9 46 3.3 42 2.2 39
OE B
-40°C to 125°C 25.1 135 18.7 77 15.5 60 11.0 49 8.7 44 7.3 42

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7.10 Switching Characteristics, VCCA = 2.5 ± 0.2 V

See Figure 8-1 and Table 8-1 for test circuit and loading. See Figure 8-2, Figure 8-3, and Figure 8-4 for measurement waveforms.
B-Port Supply Voltage (VCCB)
Test
PARAMETER FROM TO 1.2 ± 0.1 V 1.5 ± 0.1 V 1.8 ± 0.15 V 2.5 ± 0.2 V 3.3 ± 0.3 V 5.0 ± 0.5 V UNIT
Conditions
MIN TYP MAX MIN TYP MAX MIN TYP MAX MIN TYP MAX MIN TYP MAX MIN TYP MAX
-40°C to 85°C 0.5 70 0.5 26 0.5 20 0.5 14 0.5 12 0.5 9
A B
Propagation -40°C to 125°C 1.8 45 0.5 26 0.5 20 0.5 14 0.5 12 0.5 10
tpd ns
delay -40°C to 85°C 0.5 32 0.5 19 0.5 17 0.5 14 0.5 13 0.5 13
B A
-40°C to 125°C 0.5 28 0.5 20 0.5 17 0.5 14 0.5 13 0.5 13
-40°C to 85°C 12.9 65 10.5 51 9.0 51 8.1 43 8.4 44 5.0 45
OE A
-40°C to 125°C 24.9 68 21.8 55 19.7 50 18.2 47 18.6 48 15.0 49
tdis Disable time ns
-40°C to 85°C 23.2 112 16.5 74 14.0 61 9.0 46 9.1 44 6.4 39
OE B
-40°C to 125°C 38.7 115 30.9 79 27.1 66 21.6 51 20.5 48 16.8 43
-40°C to 85°C 7.9 80 5.9 50 5.1 44 4.7 39 4.4 40 3.7 41
OE A
-40°C to 125°C 15.6 74 13.5 53 12.4 47 12.0 42 11.5 43 10.8 44
ten Enable time ns
-40°C to 85°C 16.3 183 9.2 74 6.0 54 4.0 36 2.1 31 0.5 27
OE B
-40°C to 125°C 24.4 139 17.2 76 13.0 57 9.8 38 7.1 33 4.7 29

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7.11 Switching Characteristics, VCCA = 3.3 ± 0.3 V

See Figure 8-1 and Table 8-1 for test circuit and loading. See Figure 8-2, Figure 8-3, and Figure 8-4 for measurement waveforms.
B-Port Supply Voltage (VCCB)
Test
PARAMETER FROM TO 1.2 ± 0.1 V 1.5 ± 0.1 V 1.8 ± 0.15 V 2.5 ± 0.2 V 3.3 ± 0.3 V 5.0 ± 0.5 V UNIT
Conditions
MIN TYP MAX MIN TYP MAX MIN TYP MAX MIN TYP MAX MIN TYP MAX MIN TYP MAX
-40°C to 85°C 0.5 69 0.5 25 0.5 19 0.5 13 0.5 11 0.5 8
A B
Propagation -40°C to 125°C 1.5 44 0.5 25 0.5 19 0.5 13 0.5 11 0.5 9
tpd ns
delay -40°C to 85°C 0.5 30 0.5 17 0.5 14 0.5 12 0.5 11 0.5 10
B A
-40°C to 125°C 0.5 27 0.5 18 0.5 15 0.5 12 0.5 11 0.5 10
-40°C to 85°C 12.9 62 10.1 47 8.7 42 6.9 39 6.6 39 6.9 40
OE A
-40°C to 125°C 24.0 65 20.6 51 18.4 46 15.7 40 15.3 39 15.9 40
tdis Disable time ns
-40°C to 85°C 22.7 109 15.7 71 13.2 59 8.5 42 7.6 38 4.7 34
OE B
-40°C to 125°C 37.6 111 29.5 75 25.4 63 19.2 46 18.5 42 14.2 36
-40°C to 85°C 6.6 85 4.2 45 3.0 37 2.4 31 2.2 30 1.7 30
OE A
-40°C to 125°C 13.6 72 10.9 47 9.3 40 8.2 33 8.1 32 7.5 33
ten Enable time ns
-40°C to 85°C 16.3 192 8.9 76 5.4 55 2.6 34 1.8 27 0.5 22
OE B
-40°C to 125°C 24.3 144 16.7 78 12.2 57 8.0 36 6.6 29 3.7 24

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7.12 Switching Characteristics, VCCA = 5.0 ± 0.5 V

See Figure 8-1 and Table 8-1 for test circuit and loading. See Figure 8-2, Figure 8-3, and Figure 8-4 for measurement waveforms.
B-Port Supply Voltage (VCCB)
Test
PARAMETER FROM TO 1.2 ± 0.1 V 1.5 ± 0.1 V 1.8 ± 0.15 V 2.5 ± 0.2 V 3.3 ± 0.3 V 5.0 ± 0.5 V UNIT
Conditions
MIN TYP MAX MIN TYP MAX MIN TYP MAX MIN TYP MAX MIN TYP MAX MIN TYP MAX
-40°C to 85°C 0.5 69 0.5 24 0.5 18 0.5 13 0.5 10 0.5 8
A B
Propagation -40°C to 125°C 1.3 44 0.5 24 0.5 19 0.5 13 0.5 11 0.5 8
tpd ns
delay -40°C to 85°C 0.5 31 0.5 15 0.5 12 0.5 9 0.5 8 0.5 8
B A
-40°C to 125°C 0.5 26 0.5 16 0.5 13 0.5 10 0.5 9 0.5 8
-40°C to 85°C 10.8 58 7.7 42 5.9 36 4.2 31 3.4 30 2.8 26
OE A
-40°C to 125°C 20.8 61 17.0 46 14.5 40 11.8 33 10.4 31 9.6 29
tdis Disable time ns
-40°C to 85°C 9.7 109 5.9 69 13.2 56 8.4 40 6.9 36 3.7 29
OE B
-40°C to 125°C 37.4 111 29.2 73 24.6 60 18.1 43 16.4 39 12.2 31
-40°C to 85°C 6.0 102 2.8 44 1.2 33 0.5 25 0.5 22 0.5 21
OE A
-40°C to 125°C 12.4 81 8.8 46 6.5 36 4.7 27 4.2 24 4.4 23
ten Enable time ns
-40°C to 85°C 16.7 212 8.8 82 4.8 58 1.6 35 0.5 26 0.5 19
OE B
-40°C to 125°C 24.8 158 16.7 83 11.7 60 6.9 37 4.7 28 3.5 21

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7.13 Operating Characteristics

TA = 25℃ (1)
Supply Voltage (VCCB = VCCA)
PARAMETER Test Conditions 1.2 ± 0.1V 1.5 ± 0.1V 1.8 ± 0.15V 2.5 ± 0.2V 3.3 ± 0.3V 5.0 ± 0.5V UNIT
TYP TYP TYP TYP TYP TYP
A to B: outputs enabled 2 2 2 2 2 3
A Port
A to B: outputs disabled CL = 0, RL = Open 2 2 2 2 2 3
CpdA (2) pF
B to A: outputs enabled f = 10 MHz 12 12 12 13 13 16
trise = tfall = 1 ns
B to A: outputs disabled 2 2 2 2 2 3
A to B: outputs enabled 12 12 12 13 13 16
B Port
A to B: outputs disabled CL = 0, RL = Open 2 2 2 2 2 3
CpdB (3) pF
B to A: outputs enabled f = 10 MHz 2 2 2 2 2 3
trise = tfall = 1 ns
B to A: outputs disabled 2 2 2 2 2 3

(1) See the CMOS Power Consumption and Cpd Calculation application report for additional information about how power dissipation
capacitance affects power consumption.
(2) A-Port power dissipation capacitance per transceiver.
(3) B-Port power dissipation capacitance per transceiver.

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7.14 Typical Characteristics

5 1.95
4.75
4.5 1.8
VOH - Output High Voltage (V)

VOH - Output High Voltage (V)

4.25
1.65
4
3.75 1.5
VCC = 5.0V
3.5 VCC = 3.3V
3.25 VCC = 2.5V 1.35
3
2.75 1.2

2.5
1.05
2.25
VCC = 1.8V
2 VCC = 1.5V
0.9 VCC = 1.2V
1.75
1.5 0.75
0 3 6 9 12 15 18 21 24 0 0.8 1.6 2.4 3.2 4 4.8 5.6 6.4 7.2 8
IOH - Output High Current (mA) IOH - Output High Current (mA)

Figure 7-1. Typical (TA=25°C) Output High Voltage (VOH) vs Figure 7-2. Typical (TA=25°C) Output High Voltage (VOH) vs
Source Current (IOH) Source Current (IOH)

0.35 0.35
VCC = 2.5V VCC = 1.2V
0.325 VCC = 3.3V 0.325 VCC = 1.5V
0.3 VCC = 5.0V 0.3 VCC = 1.8V

0.275 0.275
VOL - Output Low Voltage (V)

VOL - Output Low Voltage (V)

0.25 0.25
0.225 0.225
0.2 0.2
0.175 0.175
0.15 0.15
0.125 0.125
0.1 0.1
0.075 0.075
0.05 0.05
0.025 0.025
0 0
0 3 6 9 12 15 18 21 24 0 0.8 1.6 2.4 3.2 4 4.8 5.6 6.4 7.2 8
IOL - Output Low Current (mA) IOL - Output Low Current (mA)

Figure 7-3. Typical (TA=25°C) Output Low Voltage (VOL) vs Sink Figure 7-4. Typical (TA=25°C) Output Low Voltage (VOL) vs Sink
Current (IOL) Current (IOL)

2 0.22
VCC = 2.5 V VCC = 1.2 V
1.8 0.2
VCC = 3.3 V VCC = 1.5 V
VCC = 5 V 0.18 VCC = 1.8 V
1.6
ICC - Supply Current (mA)
ICC - Supply Current (mA)

0.16
1.4
0.14
1.2
0.12
1
0.1
0.8 0.08
0.6 0.06
0.4 0.04

0.2 0.02
0
0 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 VIN - Input Voltage (V)
VIN - Input Voltage (V)
Figure 7-6. Typical (TA=25°C) Supply Current (ICC) vs Input
Figure 7-5. Typical (TA=25°C) Supply Current (ICC) vs Input
Voltage (VIN)
Voltage (VIN)

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8 Parameter Measurement Information

8.1 Load Circuit and Voltage Waveforms
Unless otherwise noted, generators supply all input pulses that have the following characteristics:
• f = 1 MHz
• ZO = 50 Ω
• Δt/ΔV ≤ 1 ns/V
Measurement Point
2 x VCCO
RL
S1
Output Pin
Open
Under Test

CL(1) RL GND

A. CL includes probe and jig capacitance.

Figure 8-1. Load Circuit

Table 8-1. Load Circuit Conditions

Parameter VCCO RL CL S1 VTP
tpd Propagation (delay) time 1.1 V – 5.5 V 10 kΩ 5 pF Open N/A
1.1 V – 1.6 V 10 kΩ 5 pF 2 × VCCO 0.1 V
ten, tdis Enable time, disable time 1.65 V – 2.7 V 10 kΩ 5 pF 2 × VCCO 0.15 V
3.0 V – 5.5 V 10 kΩ 5 pF 2 × VCCO 0.3 V
1.1 V – 1.6 V 10 kΩ 5 pF GND 0.1 V
ten, tdis Enable time, disable time 1.65 V – 2.7 V 10 kΩ 5 pF GND 0.15 V
3.0 V – 5.5 V 10 kΩ 5 pF GND 0.3 V

VCCI(1)
VCCI(1)
100 kHz
VCCI / 2
Input A, B
Input A, B VCCI / 2
500 ps/V ± 1 s/V
0V
0V
tpd tpd VOH(2)
VOH(2) Output B, A Ensure Monotonic
Rising and Falling Edge
Output B, A VCCI / 2 VCCI / 2 VOL(2)
VOL(2) 1. VCCI is the supply pin associated with the input port.
2. VOH and VOL are typical output voltage levels that occur
1. VCCI is the supply pin associated with the input port.
with specified RL, CL, and S1
2. VOH and VOL are typical output voltage levels that occur
Figure 8-3. Input Transition Rise and Fall Rate
with specified RL, CL, and S1
Figure 8-2. Propagation Delay

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VCCA

OE VCC A / 2 VCC A / 2

GND

tdi s ten

VCCO(3)

Output(1) VCC O / 2
VOL + VTP
VOL (4)

VOH (4)
VOH - VTP
Output(2) VCC O / 2

GND

A. 1. Output waveform on the condition that input is driven to a valid Logic Low.
2. Output waveform on the condition that input is driven to a valid Logic High.
3. VCCO is the supply pin associated with the output port.
4. VOH and VOL are typical output voltage levels with specified RL, CL, and S1.

Figure 8-4. Enable Time And Disable Time

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9 Detailed Description
9.1 Overview
The TXU0104 is a 4-bit translating transceiver that uses two individually configurable power-supply rails. The
device is operational with VCCA and V CCB supplies as low as 1.1 V and as high as 5.5 V. Additionally, the device
can be operated with VCCA = VCCB. The A port is designed to track VCCA, and the B port is designed to track
VCCB.
The TXU0104 device is designed for asynchronous communication between data buses, and transmits data with
fixed direction from the A bus to the B bus on some channels and from the B bus to the A bus on the remaining
channels. The output-enable input (OE) is used to disable the outputs so the buses are effectively isolated. The
output-enable pin of the TXU0104 (OE) can be referenced to either VCCA or VCCB. The OE pin can be left floating
or externally pulled down to ground to ensure the high-impedance state of the level shifter outputs during power
up or power down.
This device is fully specified for partial-power-down applications using the Ioff current. The Ioff protection circuitry
ensures that no excessive current is drawn from or sourced into an input or output while the device is powered
down.
The VCC isolation or VCC disconnect feature ensures that if either VCC is less than 100 mV or disconnected
with the complementary supply within recommended operating conditions, outputs are disabled and set to the
high-impedance state while the supply current is maintained. The Ioff-float circuitry ensures that no excessive
current is drawn from or sourced into an input or output while the supply is floating.
Glitch-free power supply sequencing allows either supply rail to be powered on or off in any order while providing
robust power sequencing performance.
9.2 Functional Block Diagram

VCC(MIN) VCCA VCCB

OE

A1 B1Y

A2 B2Y

A3 B3Y

A4 B4Y

GND

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9.3 Feature Description

9.3.1 CMOS Schmitt-Trigger Inputs with Integrated Pulldowns
Standard CMOS inputs are high impedance and are typically modeled as a resistor in parallel with the input
capacitance given in the Electrical Characteristics. The worst case resistance is calculated with the maximum
input voltage, given in the Absolute Maximum Ratings, and the maximum input leakage current, given in the
Electrical Characteristics, using ohm's law (R = V ÷ I).
The Schmitt-trigger input architecture provides hysteresis as defined by ΔVT in the Electrical Characteristics,
which makes this device extremely tolerant to slow or noisy inputs. Driving the inputs slowly will increase
dynamic current consumption of the device. See Understanding Schmitt Triggers for additional information
regarding Schmitt-trigger inputs.
[Link] Inputs with Integrated Static Pull-Down Resistors
This device has 5 MΩ typical integrated weak pull-downs for each input. This feature allows all inputs to be left
floating without the concern for unstable outputs or increased current consumption. This also helps to reduce
external component count for applications where not all channels are used or need to be fixed low. If an external
pull-up is required, it should be no larger than 1 MΩ to avoid contention with the 5 MΩ internal pull-down.
9.3.2 Control Logic (OE) with VCC(MIN) Circuitry
The output-enable input (OE) is used to disable the outputs so the buses are effectively isolated. The
output-enable pin of the TXU0x04 has VCC(MIN) circuitry, which allows the OE pin to operate with the lower
supply voltage. The Over-Voltage Tolerant Inputs feature allows the OE pin to operate with the higher supply
voltage. This combination means that the enable pin can be referenced to either VCCA or VCCB supply. Multiple
permutations of each device are possible since the controller can be placed on either the A or B port and can still
control the enable pin.
9.3.3 Balanced High-Drive CMOS Push-Pull Outputs
A balanced output allows the device to sink and source similar currents. The high drive capability of this device
creates fast edges into light loads, so routing and load conditions should be considered to prevent ringing.
Additionally, the outputs of this device are capable of driving larger currents than the device can sustain without
being damaged. Absolute Maximum Ratings defines the electrical and thermal limits that must be followed at all
times.
9.3.4 Partial Power Down (Ioff)
The inputs and outputs for this device enter a high-impedance state when the device is powered down, inhibiting
current backflow into the device. The Ioff in the Electrical Characteristics specifies the maximum leakage into or
out of any input or output pin on the device.
9.3.5 VCC Isolation and VCC Disconnect
The outputs for this device are disabled and enter a high-impedance state when either supply is <100 mV
or left floating (disconnected), with the complementary supply within recommended operating conditions. It is
recommended that the inputs are kept low before floating (disconnecting) either supply.
The ICCx(floating) in the Electrical Characteristics specifies the maximum supply current. The Ioff(float) in the
Electrical Characteristics specifies the maximum leakage into or out of any input or output pin on the device.

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VCCA VCCB
Supply disconnected ICCB maintained
VCC(MIN) VCCA VCCB
OE

Hi-Z Disabled Hi-Z

A1 B1Y
Ioff(float) Ioff(float)

GND

Figure 9-1. VCC Disconnect Feature

9.3.6 Over-Voltage Tolerant Inputs

Input signals to this device can be driven above the supply voltage so long as they remain below the maximum
input voltage value specified in the Recommended Operating Conditions.
9.3.7 Glitch-Free Power Supply Sequencing
Either supply rail may be powered on or off in any order without producing a glitch on the inputs or outputs (that
is, where the output erroneously transitions to VCC when it should be held low or vice versa). Glitches of this
nature can be misinterpreted by a peripheral as a valid data bit, which could trigger a false device reset of the
peripheral, a false device configuration of the peripheral, or even a false data initialization by the peripheral.

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9.3.8 Negative Clamping Diodes

Figure 9-2 depicts the inputs and outputs to this device that have negative clamping diodes.

CAUTION
Voltages beyond the values specified in the Absoulte Maximum Ratings table can cause damage to
the device. The input negative-voltage and output voltage ratings may be exceeded if the input and
output clamp-current ratings are observed.

VCCA VCCB
Device

Input or I/O
Level I/O configured
configured
Shifter as output
as input
-IIK -IOK

GND

Figure 9-2. Electrical Placement of Clamping Diodes for Each Input and Output

9.3.9 Fully Configurable Dual-Rail Design

The VCCA and VCCB pins can be supplied at any voltage from 1.1 V to 5.5 V, making the device suitable for
translating between any of the voltage nodes (1.2 V, 1.5 V, 1.8 V, 3.3 V, and 5.0 V).
9.3.10 Supports High-Speed Translation
The TXU0104 device can support high data-rate applications. The translated signal data rate can be up to 200
Mbps when the signal is translated from 3.3 V to 5.0 V.
9.4 Device Functional Modes
Table 9-1. Function Table
CONTROL INPUTS Port Status
OPERATION
OE Input Output
H L L Unidirectional non-inverting
voltage translation
H H H Unidirectional non-inverting
voltage translation
L X Hi-Z Isolation

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10 Application and Implementation

Note
Information in the following applications sections is not part of the TI component specification,
and TI does not warrant its accuracy or completeness. TI’s customers are responsible for
determining suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.

10.1 Application Information

The TXU0104 device can be used in level-translation applications for interfacing devices or systems operating
at different interface voltages with one another. The TXU0104 device is ideal for use in applications where
a push-pull driver is connected to the data Inputs. The max data rate can be up to 200 Mbps when device
translates a signal from 3.3 V to 5.0 V.
10.2 Typical Application

1.2 V 5.0 V

0.1 µF 0.1 µF

System
Controller VCCA VCCB
GPIO1 OE
GPIO2 A1 B1Y
TXU0104
GPIO3 A2 B2Y
GPIO4 A3 B3Y
GPIO5 A4 GND B4Y

Figure 10-1. TXU0104 LED Driver Application

10.2.1 Design Requirements

Use the parameters listed in Table 10-1 for this design example.
Table 10-1. Design Parameters
DESIGN PARAMETERS EXAMPLE VALUES
Input voltage range 1.1 V to 5.5 V
Output voltage range 1.1 V to 5.5 V

10.2.2 Detailed Design Procedure

To begin the design process, determine the following:
• Input voltage range
– Use the supply voltage of the device that is driving the TXU0104 device to determine the input voltage
range. For a valid logic-high, the value must exceed the positive-going input-threshold voltage (VT+) of the
input port. For a valid logic low the value must be less than the negative-going input-threshold voltage
(VT-) of the input port.
• Output voltage range
– Use the supply voltage of the device that the TXU0104 device is driving to determine the output voltage
range.

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[Link] SCES937A – MAY 2021 – REVISED SEPTEMBER 2021

10.2.3 Application Curve

Figure 10-2. Up Translation at 1 MHz (1.2 V to 5 V)

11 Power Supply Recommendations

Always apply a ground reference to the GND pins first. This device is designed for glitch free power sequencing
without any supply sequencing requirements such as ramp order or ramp rate.
Glitch-Free Power Supply Sequencing describes how this device was designed with various power supply
sequencing methods in mind to help prevent unintended triggering of downstream devices.
12 Layout
12.1 Layout Guidelines
To ensure reliability of the device, following common printed-circuit board layout guidelines are recommended:
• Use bypass capacitors on the power supply pins and place them as close to the device as possible. A 0.1 µF
capacitor is recommended, but transient performance can be improved by having 1 µF and 0.1 µF capacitors
in parallel as bypass capacitors.
• The high drive capability of this device creates fast edges into light loads so routing and load conditions
should be considered to prevent ringing.

Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 25

Product Folder Links: TXU0104
TXU0104
SCES937A – MAY 2021 – REVISED SEPTEMBER 2021 [Link]

12.2 Layout Example

Legend
Via to VCCA A Via to GND G
Via to VCCB B Copper Traces

TXU0104DTR

G G
01005 01005
0.1µF 0.1µF

OE
B
12
VCCA A 1 11 VCCB

A1 2 10 B1Y

A2 3 9 B2Y

A3 4 8 B3Y
8 mil

A4 5 7 B4Y
6
GND
G
Figure 12-1. Layout Example – TXU0104

26 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated

Product Folder Links: TXU0104

 TXU0104
[Link] SCES937A – MAY 2021 – REVISED SEPTEMBER 2021

13 Device and Documentation Support

13.1 Device Support

13.1.1 Regulatory Requirements

No statutory or regulatory requirements apply to this device.
There are no special characteristics for this product.
13.2 Documentation Support
13.2.1 Related Documentation
• Texas Instruments, Understanding Schmitt Triggers application report
• Texas Instruments, CMOS Power Consumption and Cpd Calculation application report
13.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on [Link]. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
13.4 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
13.5 Trademarks
TI E2E™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
13.6 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.

13.7 Glossary
TI Glossary This glossary lists and explains terms, acronyms, and definitions.

14 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 27

Product Folder Links: TXU0104
 PACKAGE OPTION ADDENDUM

[Link] 5-Oct-2021

PACKAGING INFORMATION

Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)

TXU0104BQAR ACTIVE WQFN BQA 14 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 TX0104

TXU0104DTRR ACTIVE X2QFN DTR 12 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 1KJ

TXU0104PWR ACTIVE TSSOP PW 14 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 TXU0104

TXU0104RUTR ACTIVE UQFN RUT 12 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 1J4

(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.

(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.

(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

Addendum-Page 1
 PACKAGE OPTION ADDENDUM

[Link] 5-Oct-2021

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

OTHER QUALIFIED VERSIONS OF TXU0104 :

• Automotive : TXU0104-Q1

NOTE: Qualified Version Definitions:

• Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects

Addendum-Page 2
 PACKAGE MATERIALS INFORMATION

[Link] 7-Oct-2023

TAPE AND REEL INFORMATION

REEL DIMENSIONS TAPE DIMENSIONS

K0 P1

B0 W
Reel
Diameter
Cavity A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
W Overall width of the carrier tape
P1 Pitch between successive cavity centers

Reel Width (W1)

QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE

Sprocket Holes

Q1 Q2 Q1 Q2

Q3 Q4 Q3 Q4 User Direction of Feed

Pocket Quadrants

*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TXU0104BQAR WQFN BQA 14 3000 180.0 12.4 2.8 3.3 1.1 4.0 12.0 Q1
TXU0104DTRR X2QFN DTR 12 3000 180.0 9.5 0.93 1.49 0.43 2.0 8.0 Q1
TXU0104PWR TSSOP PW 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
TXU0104RUTR UQFN RUT 12 3000 180.0 9.5 1.9 2.2 0.7 4.0 8.0 Q1

Pack Materials-Page 1
 PACKAGE MATERIALS INFORMATION

[Link] 7-Oct-2023

TAPE AND REEL BOX DIMENSIONS

Width (mm)
H
W

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TXU0104BQAR WQFN BQA 14 3000 210.0 185.0 35.0
TXU0104DTRR X2QFN DTR 12 3000 189.0 185.0 36.0
TXU0104PWR TSSOP PW 14 2000 356.0 356.0 35.0
TXU0104RUTR UQFN RUT 12 3000 189.0 185.0 36.0

Pack Materials-Page 2
 PACKAGE OUTLINE
PW0014A SCALE 2.500
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE

SEATING
PLANE
6.6 C
TYP
A 6.2
0.1 C
PIN 1 INDEX AREA
12X 0.65
14
1

2X
5.1 3.9
4.9
NOTE 3

4X (0 -12 )
7
8
0.30
14X
0.17
4.5 1.2 MAX
B 0.1 C A B
4.3
NOTE 4

(0.15) TYP
SEE DETAIL A

0.25
GAGE PLANE
0.15
0.05

0.75
0.50
0 -8
DETAIL A
A 20

TYPICAL

4220202/B 12/2023

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-153.

[Link]
 EXAMPLE BOARD LAYOUT
PW0014A TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE

14X (1.5) SYMM

(R0.05) TYP
1
14X (0.45) 14

SYMM

12X (0.65)

7 8

(5.8)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN
SCALE: 10X

SOLDER MASK METAL UNDER SOLDER MASK

METAL SOLDER MASK OPENING
OPENING

EXPOSED METAL EXPOSED METAL

0.05 MAX 0.05 MIN

ALL AROUND ALL AROUND

NON-SOLDER MASK SOLDER MASK

DEFINED DEFINED
(PREFERRED) SOLDER MASK DETAILS
15.000

4220202/B 12/2023
NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

[Link]
 EXAMPLE STENCIL DESIGN
PW0014A TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE

14X (1.5) SYMM

(R0.05) TYP
1
14X (0.45) 14

SYMM

12X (0.65)

7 8

(5.8)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL
SCALE: 10X

4220202/B 12/2023
NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.

[Link]
 PACKAGE OUTLINE
DTR0012A X2QFN - 0.4 mm max height
PLASTIC QUAD FLATPACK-NO LEAD

B 1.1 A
0.9

PIN 1 ID 1.8
1.6

(0.127) TYP

0.4 C
0.3
SEATING PLANE
0.04
0.00 0.08 C

4X 0.22
0.12
0.44 (0.24) TYP (0.127) TYP
0.25
4X 0.15
6
0.1 C A B 4X 0.25
0.15
7
0.05 C 5

(0.2) TYP
8
4
4X 0.28
0.18

3 9 1.38
0.73

(0.2) 10
2
TYP
(0.2) TYP

1 11

12
PIN 1 ID
4X 0.31
0.21 4X 0.26
0.16
0.1 C A B
0.05 C

4226527/B 04/2021
NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.

[Link]
 EXAMPLE BOARD LAYOUT
DTR0012A X2QFN - 0.4 mm max height
PLASTIC QUAD FLATPACK-NO LEAD
(1.03)
(1)
(0.44)

PKG

12

(R0.05) TYP

11
1

4X (0.2) 2 10
(0.69)

(0.2) TYP (0.37)

PKG
9
(1.7)
3

4X (0.23)
4 8
(0.2) TYP

5 7

4X (0.2)
4X (0.37)
6
4X (0.4) 4X (0.26)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN
SCALE: 40X

0.05 MAX 0.05 MAX SOLDER MASK

METAL
ALL AROUND ALL AROUND OPENING
SOLDER MASK METAL UNDER
OPENING SOLDER MASK

EXPOSED METAL EXPOSED METAL

NON- SOLDER MASK SOLDER MASK
DEFINED DEFINED
(PREFERRED)

SOLDER MASK DETAILS

NOT TO SCALE
4226527/B 04/2021

NOTES: (continued)

3. For more information, see Texas Instruments literature number SLUA271 ([Link]/lit/slua271).
4. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

[Link]
 EXAMPLE STENCIL DESIGN
DTR0012A X2QFN - 0.4 mm max height
PLASTIC QUAD FLATPACK-NO LEAD

(1.06)
(1.03)
(0.44)
PKG

12

(R0.05) TYP

11
1

4X (0.2) 2 10
(0.69)
(0.22) TYP
(0.37)
PKG
(1.73)
3 9

4X (0.23)
4 8
(0.22) TYP

5 7

4X (0.2)
4X (0.34)
6
4X (0.37) 4X (0.26)

SOLDER PASTE EXAMPLE

BASED ON 0.1 mm THICK STENCIL

SCALE: 40X

4226527/B 04/2021

NOTES: (continued)

5. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.

[Link]
 PACKAGE OUTLINE
RUT0012A SCALE 6.800
UQFN - 0.55 mm max height
PLASTIC QUAD FLATPACK - NO LEAD

1.8 A
B
1.6

0.6
PIN 1 INDEX AREA 0.4
0.25
2.1 (0.15) 0.15
1.9

PIN 1 ID

OPTIONAL TERMINAL & PIN 1 ID

0.55 MAX C

SEATING PLANE
0.05
0.00
0.08 C
SYMM
(0.15) TYP
6
10X 0.4
5
7

2X SYMM
1.6

11
1
12 0.25
12X
PIN 1 ID 0.15
0.6
(OPTIONAL) 12X 0.1 C B A
0.4
0.05 C

4220310/A 11/2016

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.

[Link]
 EXAMPLE BOARD LAYOUT
RUT0012A UQFN - 0.55 mm max height
PLASTIC QUAD FLATPACK - NO LEAD

SYMM

12X (0.7) 12
(R0.05) TYP
1

11

12X (0.2)

SYMM
(1.7)

8X (0.4)
7
5

6
(1.4)

LAND PATTERN EXAMPLE

SCALE:30X

0.05 MAX 0.05 MIN

ALL AROUND ALL AROUND

SOLDER MASK METAL METAL UNDER SOLDER MASK

OPENING SOLDER MASK OPENING
NON SOLDER MASK SOLDER MASK
DEFINED DEFINED
(PREFERRED)

SOLDER MASK DETAILS

4220310/A 11/2016

NOTES: (continued)

3. For more information, see Texas Instruments literature number SLUA271 ([Link]/lit/slua271).

[Link]
 EXAMPLE STENCIL DESIGN
RUT0012A UQFN - 0.55 mm max height
PLASTIC QUAD FLATPACK - NO LEAD

SYMM

12X (0.7) 12
(R0.05) TYP
1
11

12X (0.2)

SYMM
(1.7)

8X (0.4)
7
5

6
(1.4)

SOLDER PASTE EXAMPLE

BASED ON 0.1 mm THICK STENCIL
SCALE: 30X

4220310/A 11/2016

NOTES: (continued)

4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.

[Link]
 GENERIC PACKAGE VIEW
BQA 14 WQFN - 0.8 mm max height
2.5 x 3, 0.5 mm pitch PLASTIC QUAD FLATPACK - NO LEAD

This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.

4227145/A

[Link]
 PACKAGE OUTLINE
BQA0014A WQFN - 0.8 mm max height
PLASTIC QUAD FLAT PACK-NO LEAD

2.6 A
B 2.4

3.1
PIN 1 INDEX AREA 2.9

0.8 C
0.7

SEATING PLANE
0.05 1.1 0.08 C
0.00 0.9
2X 0.5 (0.2) TYP
7 8
8X 0.5
6
9

SYMM
2X 1.6
2 15 1.4

13
2
14X 0.3
0.2
PIN 1 ID 1 14 0.1 C A B
(OPTIONAL) SYMM 14X 0.5
0.3 0.05 C

4224636/A 11/2018

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for optimal thermal and mechanical performance.

[Link]
 EXAMPLE BOARD LAYOUT
BQA0014A WQFN - 0.8 mm max height
PLASTIC QUAD FLAT PACK-NO LEAD

(2.3)

(1)
2X (0.5)
1 14

2 13
8X (0.5)

2X (0.5) SYMM
(2) (1.5) (2.8)

9
6
14X (0.25)
(Ø0.2) VIA
TYP 14X (0.6)
7 8
SYMM

(R0.05) TYP

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN
SCALE: 20X

0.07 MAX 0.07 MIN METAL UNDER

ALL AROUND ALL AROUND SOLDER MASK

METAL
EXPOSED METAL

SOLDER MASK SOLDER MASK

EXPOSED METAL
OPENING OPENING

NON-SOLDER MASK
DEFINED SOLDER MASK
(PREFERRED) DEFINED

4224636/A 11/2018

NOTES: (continued)

4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 ([Link]/lit/slua271) .
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.

[Link]
 EXAMPLE STENCIL DESIGN
BQA0014A WQFN - 0.8 mm max height
PLASTIC QUAD FLAT PACK-NO LEAD

(2.3)

(0.95)
2X (0.5)
1 14

2 13
8X (0.5)

SYMM
(2) (1.38) (2.8)

9
6
14X (0.25)

14X (0.6)
7 8
SYMM

(R0.05) TYP

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

EXPOSED PAD
88% PRINTED COVERAGE BY AREA
SCALE: 20X

4224636/A 11/2018

NOTES: (continued)

6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.

[Link]
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