Module - 2

Module-2:

Bipolar Junction Transistors: Introduction, BJT Voltages & Currents, Common

Emitter Characteristics, BJT as a Switch. (Text 1: Chapter 4)
Field Effect Transistor: MOSFETs: Enhancement MOSFETs, Depletion Enhancement
MOSFETs, CMOS as an inverter (Text 1: 9.1,9.2,9.5) (8 Hours)

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Transistor as Switch:
A transistor can be used as a solid state switch. If the transistor is operated in
the saturation region then it acts as closed switch and when it is operated in the cut off
region then it behaves as an open switch.

The transistor operates as a Single Pole Single Throw (SPST) solid state switch. When
a zero input signal applied to the base of the transistor, it acts as an open switch. If a
positive signal applied at the input terminal then it acts like a closed switch.

When the transistor operating as switch, in the cut off region the current through the
transistor is zero and voltage across it is maximum, and in the saturation region the
transistor current is maximum and voltage across is zero. Therefore, both the on – state
and off – state power loss is zero in the transistor switch.

Circuit Diagram of Transistor as a Switch

Cut Off State (Open Switch)

When transistor operates in the cut off region shows the following characteristics −

• The input is grounded i.e. at zero potential.

• The VBE is less that cut – in voltage 0.7 V.
• Both emitter – base junction and collector – base junction are reverse biased.
• The transistor is fully – off acting as open switch.
• The collector current IC = 0 A and output voltage Vout = VCC.

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Saturation State (Closed Switch)

The transistor operating in the saturation region exhibits following characteristics −

• The input is connected to VCC.

• Base – Emitter voltage is greater than cut – in voltage (0.7 V).
• Both the base – emitter junction and base – collector junction are forward biased.
• The transistor is fully – ON and operates as closed switch.
• The collector current is maximum
IC=VCCRLIC=VCCRL
and Vout = 0 V.

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Introduction:
• A transistor is a semiconductor device that controls current with the application
of a small electrical signal.
• Transistors may be roughly grouped into two major families: bipolar and field-effect.
BJT utilize a small current to control a large current. But, FET utilizing a small voltage to
control current.
• FETs are unipolar rather than bipolar devices. That is, the main current through
them is comprised either of electrons through an N-type semiconductor (N-channel
FET) or holes through a P-type semiconductor (P-channel FET).
• In a JFET, the controlled current passes from Source to Drain, or from Drain to Source
as the case may be. The controlling voltage is applied between the Gate and Source.
Current flowing through this channel widely depends on the input voltage applied to its
Gate terminal.
• FETs generally of two types: 1) JFET (Junction Field Effect Transistors) and 2) MOSFET
(Metal Oxide Semiconductor Field Effect Transistors).

Junction Field Effect Transistors:

• JFET is a voltage controlled three terminal uni-polar semiconductor device. The

three terminals namely, Source (S), Gate (G) and Drain (D).
• As the voltage applied to the Gate with respect to the Source (VGS), controls
the current flowing between the Drain and the Source terminals. See fig.2.1. JFETs can
be classified into two types (i) n-channel JFET and (ii) p-channel JFET, depending on
whether the current flow is due to electrons or holes, respectively.

Constructional details of a) N-channel JFET b) P-channel JFET

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Components of FET:

1. Channel: This is the area in which majority charge carriers flow. When the
majority charge carriers are entered in FET, then with the help of this channel only they
flow from source to drain.
2. Source: Source is the terminal through which the majority charge carriers are
introduced in the FET.
3. Drain: Drain is the collecting terminal in which the majority charge carriers enter and
thus contribute in the conduction procedure.
4. Gate: Gate terminal is formed by diffusion of a type of semiconductor with another type
of semiconductor. It basically creates high impurity region which controls the flow of carrier
from source to drain.

Working of N-channel JFET:

Case I: No voltage is applied to the device (VDS = 0 and VGS = 0). At this state, the device
will be idle and no current flows through it (IDS = 0).

Case-II: When VDS is applied and VGS = 0 As shown in the following figure, the two PN
junctions at the sides of the N channel establish depletion layers. The electrons will flow
from Source to Drain through a channel between the depletion layers. The size of the
depletion layers determines the width of the channel and hence current IDS, conduction
through the bar.

Case-III: When VDS is applied and VGS = - ve The depletion region width increases, which
results in reduces the width of conducting channel, thereby increasing the resistance of n-
type bar. Consequently, the current from Source to Drain is decreased.
• If more (-VGS ) is applied, further reduces the channel width until no
current flows through the channel. At this - voltage at which the JFET channel is
called as pinched-off voltage, VP.
• At this state, the IDS current is restricted only by the channel-resistance.
However, once the pinch-off occurs (VDS = VP), the current IDS saturates at a
particular level IDSS.

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Circuit diagram of N-channel JFET

Output characteristics (Drain) V-I curves of JFET:

The characteristics curves of a JFET shown in the fig.2.4, reveals four different
regions of operation are given as:

Ohmic Region: When VGS = 0 the depletion region of the channel is very small and the JFET
acts like a voltage controlled resistor.

Cut-off Region: This is also known as the pinch-off region were the Gate voltage, VGS is
sufficient to cause the JFET to act as an open circuit as the channel resistance is at
maximum.

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Saturation or Active Region: The JFET becomes a good conductor and is controlled by
the Gate- Source voltage, (VGS) while the Drain-Source voltage, (VDS) has little or no effect.
Breakdown Region: The voltage between the Drain and the Source, (VDS) is high enough
to causes the JFET’s resistive channel to breakdown and pass uncontrolled maximum
current.
The characteristics curves for a P-channel junction field effect transistor are the same as
those above, except that the Drain current ID decreases with an increasing positive Gate-
Source voltage, VGS.

The Drain current IDS is zero when VGS = VP. For normal operation, VGS is biased to be
somewhere between VP and 0. Then we can calculate the Drain current, ID for any given
bias point in the saturation or active region as follows:

1. Drain current in the Active region: Drain current (ID) at the active region can
be calculated as follows: ID lies between (pinch-off) zero to IDSS.

2. Drain-Source Channel Resistance RDS:

Similarly, if we know drain source voltage Vds and drain current Id, we can calculate
the drain-source channel resistance.

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3. Transfer characteristics of JFET:

The transfer characteristics can be determined by observing different values of ID with

variation in VGS provided that the VDS should be constant as shown in the following
figure.

Notice that the bottom end of the transfer characteristic curve is at a point on the VGS axis
equal to VGS(off), and the top end of the curve is at a point on the ID axis equal to IDSS.

This curve shows that

i) ID = 0; when VGS = VGS(off)
ii) ID = IDSS when VGS = 0
iii) The transfer characteristic curve is expressed approximately as

Hence, JFETs are often referred to as square-law devices.

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Comparison of BJT and FET:

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Metal Oxide Semiconductor Field Effect transistor (MOSFET): The MOSFET, different from
the JFET, has no pn junction structure; instead, the gate of the MOSFET is insulated from
the channel by a silicon dioxide (SiO2) layer shown in the following figure.

MOSFET circuit symbols

• The MOSFET is widely used for switching and amplifying electronic signals.
Also, it is a core of ICs and it can be designed and fabricated in a single chip because
of smaller silicon chip area.

The two basic types of MOSFETs

1. Enhancement MOSFET (E-MOSFET) and 2. Depletion MOSFET (D-MOSFET).

Out of these two types, the enhancement MOSFET is more widely used.
2. The depletion mode MOSFETs are generally ON at (VGS = 0V). The conductivity
of the channel in depletion MOSFETs is less compared to the enhancement
type of MOSFETs. The following figure shows the depletion mode MOSFET.

MOSFET in depletion mode with gate voltage zero

Case I: When there is no Gate voltage (VGS = 0), from the above figure, maximum
current flows (ID = IS = IDSS).

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Case II: When VGS = -ve with respect to the substrate, the Gate repels some of the
electrons out of the N-channel.

This creates a depletion region in the channel, as illustrated in the following figure
and therefore, increases the channel resistance and reduces the Drain current, ID. The
more negative the gate, the less the Drain current.

In this mode of operation, the device is referred to as a depletion-mode MOSFET.

Here too much negative Gate voltage can pinch-off the channel. Then device is said to be
OFF.

MOSFET in depletion mode with gate voltage negative

Case III: When VGS = +ve, Gate attracts the negative charge carriers from the P-substrate
to the N- channel and thus reduces the channel resistance and increases the drain current,
ID. The more positive the Gate is made, the more Drain current flows. In this mode of
operation, the device is referred to as an enhancement-mode MOSFET. This is depicted in
the following figure.

MOSFET in depletion mode with gate voltage positive

Transfer and Drain characteristic of depletion MOSFET is shown in the following figure.

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Transfer characteristic and Drain characteristic of depletion MOSFET

Enhancement Mode:

The construction of an enhancement-type MOSFET is quite similar to that of the depletion-

type MOSFET, except for the absence of an N-channel between the drain and source
terminals.

The minimum value of VGS is required to form the induced N-channel, that turns the E-
MOSFET ON is called threshold voltage [VGS (th)]. For VGS below VGS (th), the drain
current ID = 0.

(i) When VGS = 0 V, VDS = +ve: There is no channel induced between Source and Drain.
The p- substrate has only a few thermally produced free electrons (minority carriers)
so that drain current is almost zero. For this reason, E-MOSFET is normally OFF when
VGS = 0V.

(ii) When VGS = VGS(th) = + ve, and VDS = + ve: The free electrons developed next to the
SiO2 layer and induced an N channel, as shown in the following figure. Now a Drain current
ID starts flowing. E-MOSFET is turned ON. Beyond VGS (th), if the value of VGS is increased,
the induced N channel becomes wider, resulting large ID. If the value of VGS decreases not
less than VGS(th), the channel becomes narrower and ID will decrease.

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MOSFET in enhancement mode with gate voltage positive

Since the conductivity of the channel is enhanced by the positive bias on the Gate, so this
device is also called the enhancement MOSFET or E- MOSFET.

Characteristics of E-MOSFET:

Drain Characteristics curve: The following figure shows the drain characteristics. It has
almost vertical and almost horizontal parts. The vertical components of the curves
correspond to the ohmic region, and the horizontal components correspond to the
saturation region (constant current). Note the following worthy points:

• ID depends on different values of VGS (from 0V to + VGS (max)).

• When VGS = 0, even for large increase in VDS, ID = 0. This is said to be cut-off
region. (MOSFET off state).

E-MOSFET circuit

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Drain characteristic of E-MOSFET

Transfer Characteristics curve:

i. When VGS < VGS(th), then ID =0. This is because under this state, the channel
will not be connecting between the drain and the source terminals. This is
called as cut-off region. (MOSFET off state). The tranfer curves of MOSFET is shown
in the following figure.

Transfer characteristic of E - MOSFET

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ii. When VGS > VGS(th),. then ID flows through the device, initially (Ohmic region)
and then saturates to a value (saturation region). That means, ID is controlled by the
Gate voltage, VGS.
iii. ID can be obtained by analytical expression:

CMOS Inverter : Working & Its Applications

The term “CMOS” stands for “complementary-symmetry metal–oxide–semiconductor”
which is pronounced as “see mos”. CMOS is a type of MOSFET, where its fabrication
process uses complementary & symmetrical P-type & N-type MOSFET pairs for logic
functions. The main CMOS devices characteristics are consumption of low static power &
high noise immunity. The inverter is accepted universally as the basic logic gate while
performing a Boolean operation on a single i/p variable. A basic inverter circuit is used to
accomplish a logic variable by complementing from A to A’. So, a CMOS inverter is a very
simple circuit, designed with two opposite-polarity MOSFETs within a complementary
way. This article discusses an overview of the CMOS inverter and its working with
applications.

What is CMOS Inverter?

CMOS inverter definition is a device that is used to generate logic functions is known as
CMOS inverter and is the essential component in all integrated circuits. A CMOS inverter
is a FET (field effect transistor), composed of a metal gate that lies on top of oxygen’s
insulating layer on top of a semiconductor. These inverters are used in most electronic
devices which are accountable for generating data n small circuits.

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CMOS Inverter Symbol & Truth Table --- CMOS Inverter Schematic Diagram
The logic element like an inverter reverses the applied input signal. In digital logic circuits,
binary arithmetic & switching or logic function’s mathematical manipulation are best
performed through the symbols 0 & 1. The CMOS inverter truth table is shown above. If
the input logic is zero (0) then the output will be high (1) whereas, if the input logic is one
(1), then the output will be low (0).

CMOS Inverter Circuit

The CMOS inverter circuit diagram is shown below. The general CMOS inverter structure
is the combination of both the PMOS & NMOS transistors where the pMOS is arranged at
the top & nMOS is arranged at the bottom.

The connection of both the PMOS & NMOS transistors in the CMOS inverter can be done
like this. The NMOS transistor is connected at the drain (D) & gate (G) terminals, a
voltage supply (VDD) is connected at the source terminal of PMOS & a GND terminal is
connected at the source terminal of NMOS. Input voltage (Vin) is connected to both the
gate terminals of transistors & output voltage (Vout) is connected to the drain (D)
terminals of the transistor.

It is very significant to observe that the CMOS device does not have any resistors, so it
will be more power-efficient. Once the input voltage of CMOS changes between 0 to 5
volts, then both the transistors state will be changed accordingly. If we design every
transistor like a simple switch that is operated through input voltage (Vin), then
operations of the inverter can be observed very simply:

CMOS Inverter Operation & Working

The working of CMOS inverter is the same as other types of FETs except depends on an
oxygen layer to divide electrons within the gate & semiconductor. They are designed with
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a power supply, input voltage terminal, output voltage, gate, drain, and PMOS & NMOS
transistors which are connected to the gate & the drain terminals.

When the low input voltage is given to the CMOS inverter, then the PMOS transistor is
switched ON whereas the NMOS transistor will switch OFF by allowing the flow of
electrons throughout the gate terminal & generating high logic output voltage.

Similarly, when the high input voltage is given to the CMOS inverter then, the PMOS
transistor is switched OFF whereas the NMOS transistor will be switched ON avoiding as
many electrons from attaining the output voltage & generating low logic output voltage.

Thus, direct current supplies from the supply voltage (VDD) to the output voltage (Vout)
& the load capacitor (CL) can be charged and shows that Vout = VDD. As a result, the
above circuit works like an inverter.

CMOS Inverter Characteristics

The characteristics of the CMOS inverter are discussed below.
Inverter Static Characteristics or VTC
The quality of the inverter can be measured frequently by using the VTC or voltage
transfer curve, which is plotted between input voltage (Vin) and output voltage (Vo).
From the following static characteristics, the parameters of devices like gain, operating
logic levels & noise tolerance, and noise can be obtained.

Voltage
Transfer Curve
The VTC or voltage transfer curve looks like an inverted step-function that specifies
accurate switching in between ON & OFF however in real devices, a gradual transition
region exists. The voltage transfer curve specifies that for less input voltage Vin, the
circuit generates high voltage Vout, whereas, for high input, it generates 0 volts.

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The transition region slope is a measure of quality – steep slopes yield exact switching.
The tolerance toward noise can be calculated by evaluating the smallest input to the
highest output for every region of ON or OFF operation.

Inverter Dynamic Characteristics

The CMOS inverter dynamic characteristics are shown below. So, some of the following
formal definitions of different parameters are discussed below. Here, all the percentage
(%) values are the steady-state values.

Dynamic
Characteristics of CMOS Inverter
• Rise Time or tr: Rise time is the time used to increase the signal from 10% to 90%.
• Fall Time or tf: Fall time is the time used to drop the signal from 90% to 10%
• Edge Rate or trf : It is (tr + tf )/2.
• The propagation delay from high to low or tpHL: The time used to drop from VOH –
50%.
• The propagation delay from low to high or tpLH: The time used to increase from 50%-
VOL.
• Propagation Delay or tp: It is (tpHL + tpLH)/2.
• Contamination Delay or tcd: It is the smallest time from the 50% input crossing to the
50% output crossing.
Advantages
The CMOS inverter advantages include the following.
• The CMOS inverter’s steady-state power dissipation is negligible virtually, apart from
small power dissipation because of leakage currents.

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• The VTC (voltage transfer characteristic) exhibits a complete o/p voltage swing in
between 0 V & VDD, and the transition of voltage transfer characteristic is normally
very sharp. Thus, the characteristics of the CMOS inverter look like an ideal inverter.
• These inverters use electricity once they are switched ON & OFF resulting in less power
consumption. As a result, these inverters generate extremely less waste heat to make
them highly efficient, so used in small and delicate electronic devices.
• These inverters include high noise immunity, which lets them block both incoming &
outgoing frequency spikes.
• These are low-cost to produce mass.
Disadvantages
The CMOS inverter disadvantages include the following.
• As compared to other inverters, the switching speed of the CMOS inverter is high.
• These are very difficult to fabricate due to both the transistors used on the same Silica
piece.
• It uses two transistors to make an inverter, so it uses more space on the IC as
compared to the NMOS inverter.
Applications
The applications of CMOS inverters include the following.
• CMOS inverters are used in different ICs (integrated circuits) like microprocessors, static
RAM, microcontrollers, data converters, image sensors & transceivers.
• These are found in mobile devices, digital cameras, home computers, cell phones,
routers, network servers, modems & virtually each other electronic device that needs
logic functions.

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Problems on FET:
Important Points:
FET Characteristics:

• At the point on the characteristic where Ip levels off, the drain current is referred to as
the drain-source saturation current (Idss) i.e., 10 mA in above figure.
• The drain source voltage at this point is termed the pinch-off voltage (Vp).
• he bias voltage required to Id=0 is termed the gate cutoff voltage VGS(off), and VGS(off) =
Vp.
• The transfer characteristic for a FET can be derived from the drain characteristics. A
line is drawn vertically on the drain characteristics to represent a constant Vps level.
The corresponding Ip and Vgs values along this line are noted and then used to plot the
transfer characteristic.

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• The drain current of Field Effect Transistor in terms of drain-source saturation current (IDSS)
and the pinch-off voltage (Vp or VGS(off)) is:

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• The voltage of Gate-Source(VGS) in terms of VGS threshold maximum

voltage(VGS(th)max) is:

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