SEQUENTIAL CIRCUITS

PART 2
REGISTERS
• Register is a group of flip flops used to
store multiple bits of data.

• Each flip-flop stores one bit, and together

they form a data word.

• Applications: Usage of storage of data,

data transmission.
SHIFT OPERATION
• Repeated addition makes system mores complex.

• Bitwise shifting offers a faster alternative.

Shift Left Shift Right

Multiplies the number by 2 Divides the number by 2

Example Example

5 (00000101) 8 (00001000)
Shifts left the number by 1 -> (00001010) Shifts right the number by 1 -> (00000100)
Number becomes 10. Number becomes 4.
Same as 5*2 Same as 8/2
SHIFT REGISTERS
• In shift registers bits stored can be made to move within the registers
and in/out of the registers by applying clock pulses.

• Output of one flipflop is connected to the output of the next flipflop.

• An n-bit shift register can be formed by connecting n flip-flops where

each flip-flop stores a single bit of data.

• The Flipflop holding the LSB receives the incoming count pulse
TYPES OF SHIFT REGISTERS
• SISO (Serial-In Serial-Out): Data enters and
exits one bit at a time.

• SIPO (Serial-In Parallel-Out): Data enters

serially, but all bits are output
simultaneously.

• PISO (Parallel-In Serial-Out): Data is loaded all

at once and shifted out one bit at a time.

• PIPO (Parallel-In Parallel-Out): All bits are

loaded and output simultaneously.
Mode Description Loading Reading Total
n-1 clocks to
SISO Serial-In Serial-Out n clocks to load data serially 2n - 1
read last bit out

All bits available

SIPO Serial-In Parallel-Out n clocks to load data serially n
simultaneously

n-1 clocks to
PISO Parallel-In Serial-Out 1 clock to load data in parallel shift out bits n
serially

All bits available

PIPO Parallel-In Parallel-Out 1 clock to load data 1
in parallel
 SISO (Serial-in Serial-out shift register)
SHIFT REGISTER
• The shift register which accepts serial input and produces a serial output.
SISO SHIFT REGISTER Clock Q1 Q2 Q3
Q4
(dout)
0 0 0 0 0

• Input bits: 1011 1 1 0 0 0

• Initial Qs: 0000 2 0 1 0 0

• Bits shift right 3 1 0 1 0

• Final Qs: 1011 4 1 1 0 1

5 0 1 1 0

6 0 0 1 1

7 0 0 0 1
module SISO (
input clk,
input rst,
input din, // Serial input
output dout // Serial output
);
reg [3:0] shift_reg;

always @(posedge clk or posedge rst) begin

if (rst)
shift_reg <= 4'b0000;
else
shift_reg <= {shift_reg[2:0], din}; // Shift left
//shift_reg <= {din, shift_reg[3:1]}; // Shift right
end

assign dout = shift_reg[3]; // Output last bit

endmodule
 PISO (Parallel-in Serial-out shift register)
SHIFT REGISTER
• The shift register which accepts serial input and produces a serial output.
PISO SHIFT REGISTER
Q0
Clock Q3 Q2 Q1
(dout)
•Input bits:1011
0 0 0 0 0
•Parallel load into Q3-Q0
1 (Load) 1 0 1 1
•Bits shift right →
2 0 1 0 1
•Q0 is the serial output
3 0 0 1 0

4 0 0 0 1
module PISO (input clk,input rst,input load, parallel inputinput [3:0] din,
output dout);
reg [3:0] shift_reg;

always @(posedge clk or posedge rst) begin

if (rst)
shift_reg <= 4'b0000;
else if (load)
shift_reg <= din; // Load all bits in one clock when load is high
else
shift_reg <= {shift_reg[2:0], 1'b0}; // Shift left, insert 0 at LSB
end
assign dout = shift_reg[3]; // Output MSB of the shift register
endmodule
module PISO_tb; // Apply reset
reg clk; #10;
reg rst; rst = 0;
reg load;
reg [3:0] din;
// Load parallel input
wire dout;
PISO uut ( .clk(clk), .rst(rst),.load(load),.din(din),.dout(dout) ); din = 4'b1011;
always #5 clk = ~clk; load = 1;
initial begin #10;
// Initialize signals load = 0;
clk = 0;
rst = 1;
$finish;
load = 0;
din = 4'b0000; end
endmodule
Implement PISO and SISO
shift registers
 SIPO (Serial-in Parallel-out shift register)
SHIFT REGISTER
• The shift register which accepts input serially and produces a parallel output.
 PIPO (Parallel-in Parallel-out shift register)
SHIFT REGISTER
• The shift register which accepts input in parallel and produces a parallel output.
UNIVERSAL SHIFT REGISTER

S0 S1 Operation
0 0 No change
0 1 Shift right
1 0 Shift left
1 1 Parallel load
CLOCK DIVIDER
• A clock divider converts an input clock signal to a clock signal with a
lower frequency.

• Applications: ADC Sampling, LED Blinking Circuits, Seven-Segment

Display Multiplexing

• Boolean Board Frequency: 100 MHz

module Clock_Divider( input clk_in,input reset,output reg clk_out);
reg [27:0] counter = 28'd0;
reg [7:0] count = 8'd0;
parameter DIVISOR = 28'd100000000;
always @(posedge clk_in or posedge reset) begin
if (reset) begin
counter <= 28'd0;
clk_out <= 1'b0;
end
else begin
counter <= counter + 28'd1;
if (counter >= (DIVISOR - 1)) begin
counter <= 28'd0;
end
clk_out <= (counter < DIVISOR/2) ? 1'b0 : 1'b1;
end
end
endmodule
clk_out <= (counter < DIVISOR/2) ? 1'b0 : 1'b1;

•For first half of cycle (0 to DIVISOR/2-1): output = 0

•For second half of cycle (DIVISOR/2 to DIVISOR-1): output = 1

•This creates a 50% duty cycle square wave

•Output frequency: 1Hz

 Frequency Division

Division Output
Stage Flip-Flops
Ratio Frequency
0 1 2¹ = 2 f₀ / 2

1 2 2² = 4 f₀ / 4

2 3 2³ = 8 f₀ / 8

3 4 2⁴ = 16 f₀ / 16

n n+1 2ⁿ⁺¹ f₀ / 2ⁿ⁺¹

 COUNTERS
• The counter counts the no. of times the specific event has occurred.

• A digital counter is a set of FFs whose states change in response to

pulses applied at the input to the counter.

• A counter can be used as a frequency divider.

Types of Counters based on count
• Up-counter counts in upward direction (0, 1, 2, 3 … N) and Down-
counter counts in downward direction (N, N-1, N-2 …. 1, 0).

• Each counts of the counter is the state of the counter.

• Number of states through which counter passes before returning to

starting state is modulus of the counter.

• If counter goes through all possible states it is called full modulus

counter.
Types of Counters based on clock input
• Counters can be asynchronous or synchronous counters.

• Asynchronous counters are also called ripple counters or series

counters

• These are easier to design and requires least hardware.

• Synchronous counters are faster as propagation delay is less

 Aspect Asynchronous Counters Synchronous Counters

Clocking Output of one FF is the clock for the next FF. All FFs receive the clock signal simultaneously.

Clock
FFs are not clocked simultaneously. FFs are clocked simultaneously.
Synchronization
Simple to design and implement even with Tedious and complex design as the number of
Design Complexity
many states. states increases.

Slower Faster
Speed (Due to cumulative delay through FFs (ripple (Total delay equals the delay of one FF as all are
effect)). clocked together)
Counter Terminologies
• 2 bit counter: mod-4 counter (Divide by 4 counter)

• 3 bit counter: mod-8 counter (Divide by 8 counter)

.
.
• n bit Counter: mod-2n counter (Divide by 2n counter)
Lockout
• At startup, the counter may enter an unused state. Further clock
pulses can keep it cycling through invalid states, rendering it
ineffective.

• This lockout condition can be avoided by resetting each flip-flop (FF).

Combination of Modulo Counters
• Counters of different mods can be combined to get another mod
counter.

• A mod-2 counter and mod-5 counter can be combined to get a mod-

10 counter.

• Single FF is mod-2 counter

Active High Reset & Low Reset
• Active high reset: Reset signal is
active when it is 1

• Active low reset: Reset signal is

active when it is 0

• Active high preset: Preset signal is

active when it is 1

• Active low preset: Preset signal is

active when it is 0
 UP COUNTER
module up_counter (
input clk,
input rst,
output reg [3:0] count
);
always @(posedge clk or posedge rst) begin
if (rst)
count <= 4'b0000;
else
count <= count + 1;
end
endmodule
module bidirectional_counter (
input clk, rst, dir, // Active high reset // Direction: 1 = up, 0 = down
output reg [3:0] count // 4-bit counter output
);
always @(posedge clk) begin
if (rst)
count <= 4'b0000; // Reset counter to 0
else if (dir)
count <= count + 1'b1; // Count up
else
count <= count - 1'b1; // Count down
end
endmodule
Asynchronous counters
• Invalid states are by-passed by providing suitable feedback.

• The number of FFs required for mod-N counter : smallest n for N<= 2n
2 bit Ripple Up Counter
MOD 8 COUNTER
• Six stable states: 000, 001, 010, 011,
100, 101, 110, 111

• When the 8th Clock pulse is applied it

goes to 1000 but immediately resets to
000.
Design a MOD8 Counter
MOD 8 COUNTER
module MOD8_COUNTER (input wire clk,input wire reset, output wire [2:0] Q);
wire q0, q1, q2;
wire reset_internal;
assign reset_internal = reset;

T_FF FF0 (.clk(clk), .reset(reset_internal), .T(1'b1), .Q(q0));

T_FF FF1 (.clk(q0), .reset(reset_internal), .T(1'b1), .Q(q1));
T_FF FF2 (.clk(q1), .reset(reset_internal), .T(1'b1), .Q(q2));

assign Q = {q2, q1, q0};

endmodule
 MOD 8 COUNTER : TESTBENCH

module TB_COUNTER; initial begin

reg clk; // Initialize
reg reset; reset = 1;
wire [2:0] Q; #10;
MOD6_COUNTER uut (.clk(clk),.reset(reset),.Q(Q)); reset = 0;
initial begin #100;
clk = 0; #50;
forever #5 clk = ~clk; // 10ns period $finish;
end end
endmodule
 Design a MOD64 Counter using
Combination of two MOD8 counters
module MOD64_COUNTER
(input wire clk,input wire reset,output wire [5:0] Q);
wire [2:0] q0, q1;

MOD8_COUNTER C0 (.clk(clk), .reset(reset), .Q(q0));

MOD8_COUNTER C1 (.clk(q0[2]), .reset(reset), .Q(q1));

assign Q = {q1, q0};

endmodule
 MOD 64 COUNTER : TESTBENCH

module TB_COUNTER; initial begin

reg clk; // Initialize
reg reset; reset = 1;
wire [5:0] Q; #10;
MOD64_COUNTER uut (.clk(clk),.reset(reset),.Q(Q)); reset = 0;
initial begin #750;
clk = 0; $finish;
forever #5 clk = ~clk; // 10ns period end
end endmodule