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 Semiconductor Science and Technology

Semicond. Sci. Technol. 38 (2023) 063002 (40pp) [Link]

Topical Review

GaN-based power high-electron-mobility

transistors on Si substrates: from
materials to devices
Nengtao Wu1,2,3,4, Zhiheng Xing1,3,4, Shanjie Li1,2,3, Ling Luo1, Fanyi Zeng1
and Guoqiang Li1,2,3,∗
1
State Key Laboratory of Luminescent Materials and Devices, South China University of Technology,
Guangzhou 510641, People’s Republic of China
2
School of Physics and Optoelectronics, South China University of Technology, Guangzhou 510641,
People’s Republic of China
3
Guangdong Choicore Optoelectronics Co., Ltd, Heyuan 517003, People’s Republic of China

E-mail: msgli@[Link]

Received 2 November 2022, revised 15 January 2023

Accepted for publication 5 April 2023
Published 25 April 2023

Abstract
Conventional silicon (Si)-based power devices face physical limitations—such as switching
speed and energy efficiency—which can make it difficult to meet the increasing demand for
high-power, low-loss, and fast-switching-frequency power devices in power electronic converter
systems. Gallium nitride (GaN) is an excellent candidate for next-generation power devices,
capable of improving the conversion efficiency of power systems owing to its wide band gap,
high mobility, and high electric breakdown field. Apart from their cost effectiveness, GaN-based
power high-electron-mobility transistors (HEMTs) on Si substrates exhibit excellent
properties—such as low ON-resistance and fast switching—and are used primarily in power
electronic applications in the fields of consumer electronics, new energy vehicles, and rail
transit, amongst others. During the past decade, GaN-on-Si power HEMTs have made major
breakthroughs in the development of GaN-based materials and device fabrication. However, the
fabrication of GaN-based HEMTs on Si substrates faces various problems—for example, large
lattice and thermal mismatches, as well as ‘melt-back etching’ at high temperatures between
GaN and Si, and buffer/surface trapping induced leakage current and current collapse. These
problems can lead to difficulties in both material growth and device fabrication. In this review,
we focused on the current status and progress of GaN-on-Si power HEMTs in terms of both
materials and devices. For the materials, we discuss the epitaxial growth of both a complete
multilayer HEMT structure, and each functional layer of a HEMT structure on a Si substrate.
For the devices, breakthroughs in critical fabrication technology and the related performances of
GaN-based power HEMTs are discussed, and the latest development in GaN-based HEMTs are
summarised. Based on recent progress, we speculate on the prospects for further development of
GaN-based power HEMTs on Si. This review provides a comprehensive understanding of

4
These authors contributed equally to this work.
∗
Author to whom any correspondence should be addressed.

1361-6641/23/063002+40$33.00 Printed in the UK 1 © 2023 IOP Publishing Ltd

Semicond. Sci. Technol. 38 (2023) 063002 Topical Review

GaN-based HEMTs on Si, aiming to highlight its development in the fields of microelectronics
and integrated circuit technology.
Keywords: GaN-on-Si, high-electron-mobility transistors, power electronics, epitaxial growth,
device fabrication
(Some figures may appear in colour only in the online journal)

1. Introduction with high speed, large current, and high breakdown-voltage

characteristics to optimise the low loss and provide a good fit
With the aim of achieving carbon neutralisation and redu- of the lateral integration. Their performance is far better than
cing emissions, the development of several energy-saving and that of Si MOSFETs and GaAs pHEMTs; moreover, their pro-
carbon-reducing applications has been promoted—including duction costs and process requirements are lower than those of
applications in the fields of consumer electronics, electric SiC MOSFETs [8].
vehicles, photovoltaic and wind power generation, and energy Research based on GaN devices can be traced back sev-
storage systems. Power electronic devices are involved in eral decades, beginning with the successful development
power conversion and control in all of these applications, gen- of AlGaN/GaN HEMTs by Khan et al [9, 10] in 1993.
erating total energy consumption equivalent to the sum of the Subsequently, the epitaxial growth and processing techno-
entire new energy generation process. Therefore, improving logy of GaN-based HEMTs has been a research hotspot
the energy conversion efficiency of power electronic devices is worldwide [11–13]. Continuous innovation and progress of
conducive to reducing energy consumption and carbon emis- GaN-based HEMT fabrication technology have stimulated the
sions. The switching speed and energy efficiency of con- demand and development of suitable substrates for GaN-based
ventional semiconductor devices—such as silicon (Si) and HEMTs. Nowadays, GaN-based materials are generally epi-
gallium arsenide (GaAs)—can make it difficult to meet the taxially grown on four types of substrates [14]—that is, GaN,
increasing demand for high power, miniaturised, and low-loss sapphire, SiC, and Si [15–19]. For commercial GaN-based
devices in power electronics [1, 2]. As a result, the third- HEMTs, researchers pay more attention to the thermal per-
generation wide-bandgap semiconductor materials represen- formance and price of devices, while meeting power electronic
ted by silicon carbide (SiC) and gallium nitride (GaN) stand application requirements. As shown in table 2, a GaN substrate
out amongst numerous materials owing to their large forbid- with high thermal conductivity and no lattice or thermal mis-
den bandwidth, high breakdown field, high carrier mobility, match is undoubtedly the best choice for GaN epitaxial growth
and high saturation velocity and have attracted considerable and device preparation. However, its high price and small size
attention [3–5]. The physical parameters of different semi- are unsuitable for commercial development. Sapphire sub-
conductor materials are listed in table 1, clearly showing the strates are widely used in light-emitting diode (LED) produc-
potential of GaN in high-frequency and high-power applica- tion owing to the maturity of GaN growth and device fabric-
tions. In addition, the Baliga’s figure of merit used to express ation technology [20]. However, sapphire has a low thermal
the comprehensive performance of a semiconductor can be conductivity of 25 W m−1 K−1 which severely hinders the
defined as follows: thermal dispatch in device applications, ultimately degrad-
( ) ing the device performance. Compared to GaN-on-Si, GaN-
V2BD /RON = qns µN E2c (1) on-SiC HEMTs have exhibited good electrical properties and
thermal conductivity owing to the low lattice and thermal mis-
where V BD denotes the breakdown voltage, RON denotes the matches between GaN and SiC [21, 22], but SiC substrates are
ON-resistance, q denotes the electronic charge, ns denotes the still costly and of small diameter, hindering the rapid develop-
two-dimensional electron gas (2DEG) density, µN denotes the ment of commercialised GaN-based HEMTs [3]. Therefore,
electron mobility, and Ec denotes the critical electric field. The researchers believe GaN-on-Si HEMTs will yet be the most
overall performance of GaN-based materials is better than that common devices used in power switching applications for the
of the previous two generations of Si and GaAs, as well as SiC- following reasons: (1) Si substrates feature excellent proper-
based materials. ties with high thermal conductivity and low hardness, which
In particular, GaN-based materials have high-density could improve the heat dissipation in chips, reduce manufac-
2DEG forming at the interface of the AlGaN/GaN hetero- turing complexity, and improve the device yield [20, 21]. (2)
junctions owing to piezoelectric and spontaneous polarisation Si substrates offer the benefits of high quality, low cost, and
[6, 7]. The 2DEG exhibits high electron mobility at the large-area substrates (up to 300 mm), which could greatly
AlGaN/GaN heterojunctions without intentional doping; con- reduce the fabrication cost of GaN-based HEMTs [23, 24]. (3)
sequently, the prepared heterojunction field-effect transist- During metal-organic chemical vapour deposition (MOCVD)
ors (HFETs) are referred to as high-electron-mobility tran- or molecular beam epitaxy (MBE) growth, GaN-based mater-
sistors (HEMTs). Moreover, GaN-based materials enable ials of acceptably good quality grown on Si substrates have
the development of high-power and high-frequency devices been realised by introducing innovative stress control layers

2
Semicond. Sci. Technol. 38 (2023) 063002 Topical Review

Table 1. Properties of Si, GaAs, 4H-SiC, and GaN.

Property Si GaAs 4H-SiC GaN

Band gap (eV) 1.12 1.42 3.25 3.45

Relative permittivity 11.4 13.1 9.7 8.9
Electronics mobility (cm2 V−1 s−1 ) 1400 8500 950 >2000 (AlGaN/GaN)
Breakdown field strength (MV cm−1 ) 0.3 0.4 2.5 3.3.
Thermal conductivity (W m−1 K−1 ) 118 52 419 130
Electronics saturation velocity (107 cm s−1 ) 1.0 2.0 2.0 2.7
Operating temperature (◦ C) 175 175 650 600
BFOM 1 11.2 51.9 179.3

Table 2. Properties of GaN, Sapphire, SiC, and Si substrates.

Properties GaN Sapphire SiC Si

Thermal conductivity (W m−1 K−1 ) 130 25 490 118

Lattice mismatch (%) — 13.2 3.5 17
Thermal mismatch (%) — 27 16 54
Commercial size (mm) 50–100 100 100–150 150–200
Substrate price High Medium High Low
References [29, 30] [31] [32, 33] [34]

to reduce the dislocation density and stress caused by the

large lattice and thermal mismatches between GaN and Si
[25, 26]. (4) GaN-based HEMTs on large-size Si substrates
exhibit excellent performance and can be integrated with well-
developed Si microelectronic circuit technologies [24, 27, 28].
Consequently, GaN-on-Si could offer a promising way to fab-
ricate low-cost and high-efficiency GaN-based HEMTs.
In this review, we focus on the current research and pro-
gress of GaN-on-Si power HEMTs from materials to devices.
First, the epitaxial growth of a complete multi-layer HEMTs Figure 1. Normally-ON (a) and normally-OFF (b) structures of
structure and each functional layer of the HEMTs structure GaN-based HEMTs on Si.
on a Si substrate are introduced in detail. Second, break-
throughs in device fabrication and the related performance of
GaN-based power HEMTs are discussed, and the latest devel- GaN-based HEMTs on a Si substrate, presenting the primary
opments are summarised. Finally, the prospects for further epitaxial process and its associated challenges. Figures 1(a)
development of GaN-based HEMTs for the power switching and (b) shows two kinds of GaN-based HEMT structures on
applications are considered. This review provides a com- Si substrate—namely, the normally-ON and normally-OFF
prehensive understanding of GaN-based power HEMTs on structures. During the growth process, stress control struc-
Si, aiming to promote further development of GaN-on-Si tures are first grown on the Si substrates, which is discussed
devices in the fields of microelectronics and integrated circuit in detail in section 2.2. The high-resistance buffer structures
technology. are then reviewed in section 2.3. Finally, (In)Al(Ga)N/GaN
and p-GaN/(In)Al(Ga)N/GaN structures are summarised in
sections 2.4 and 2.5, respectively. The subsequent overview
2. Epitaxial growth of GaN-based HEMT on Si
reveals that considerable progress has been made in epi-
substrate
taxial growth for GaN-based HEMTs for power switching
Based on the stabilised wurtzite structure of GaN, the Si(111) applications.
substrate with triple symmetry is deemed to be the most
useful orientation for the fabrication of GaN-based HEMTs,
2.1. GaN-based HEMT on Si substrate
as the Si(111) plane has a similar hexagonal arrangement
to the GaN (0002) plane [35]. Unless otherwise specified, GaN films are deposited on Si substrates mainly through
GaN and Si substrates represent the GaN stabilised wurtzite chemical reactions of the Ga and N sources on the substrate
structure and the Si(111) plane, respectively. The growth surface by MOCVD [36, 37] and MBE [38]. Since the initial
of GaN with wurtzite structures on Si(111) is reviewed in fabrication of GaN-based HEMTs on Si using MOCVD and
this section. Section 2.1 provides a summary and analysis of MBE [39, 40], fabrication techniques have undergone rapid

3
Semicond. Sci. Technol. 38 (2023) 063002 Topical Review

development, as indicated by µN growing from approximately 2.2.1. Aluminium nitride (AlN) nucleation layer. To avoid the
900 cm2 V−1 s−1 to more than 2000 cm2 V−1 s−1 [41]. Com- influence of melt-back etching and obtain high-quality GaN
pared to commonly employed MBE techniques, GaN-based films on Si substrates, nucleation layer structures between the
HEMTs on Si fabricated using MOCVD have resolved the GaN and Si substrate have been designed, including AlN [56],
paradox between the highly complex growth technology and aluminium arsenide (AlAs) [57], silicon nitride (SiNx ) [58],
the low device prices required for large volumes and wide SiC [59], and aluminium oxide (Al2 O3 ) [60]. Among these
applicability [41, 42]. Currently, MOCVD equipment is man- materials, SiNx nucleation layer mostly comes from in-situ
ufactured by Aixtron (Germany), Veeco (United States), and substrate nitridation, which makes it difficult for Ga atoms to
Advanced Micro-Fabrication Equipment Inc. (China). How- migrate resulting in low GaN nucleus density [58]. AlAs inter-
ever, the epitaxial growth of GaN-based HEMTs on Si sub- layer has high thermal stability and suppresses the nitridation
strates using MOCVD still faces at least three challenges [43]. of the Si substrate, but GaN is partially polycrystalline dur-
First, the large lattice mismatch (17%) between GaN and Si ing the growth [61]. GaN grown on the surface of SiC/Si has
leads to a large density of dislocations in the range of 108 – lower growth rate below 700 ◦ C and poor crystalline quality
1010 cm−2 [44]. These dislocation densities include stack- [59]. The stress transition of Al2 O3 to GaN layer varies with
ing faults, inversion domains, and misfit and threading dis- the thickness and is still under study [62]. Compared to these
locations in the GaN film, which induce the degradation of nucleation layers, the AlN interlayer as nucleation layer has
AlGaN/GaN heterojunction electrical characteristics, increase been widely applied, for the following reasons. First, AlN
vertical leakage paths, and cause other reliability issues [45]. (α = 0.3112 nm) has a smaller lattice constant than GaN
Second, the large thermal expansion coefficient mismatch (α = 0.3189 nm), which theoretically yields a lattice mismatch
(54%) between GaN and Si can induce GaN film cracking between AlN and GaN of 2.6%, which amounts to a compress-
[46], caused mainly by the tensile stress generated during ive stress of more than 11 GPa [63]. The compressive stress
the cool-down step of the growth process, arising due to the is considerably larger than that required to compensate for
substantially smaller thermal expansion coefficient of Si than the tensile stress generated by the thermal mismatch between
of GaN [47]. In particular, the GaN-based materials grown GaN and Si [64] (∼1.5 GPa), which offsets the tensile growth
on Si substrates of large diameter (⩾150 mm) exhibit a pro- and thermal stress in the growth of the GaN-on-Si substrates
nounced bowing effect, and tend to degrade the growth uni- [65]. Second, the inter-diffusion between Ga and Si can be
formity of surface roughness or doping, affecting the lattice avoided by inserting a thin AlN as a nucleation layer for the
stresses remaining in the epilayers [48]. This can lead to non- growth of (Al)GaN layers to circumvent the process of melt-
uniform electronic properties, such as VBD , and the wafer bow- back etching between Si and Ga atoms [66]. Finally, the role
ing can be too high to allow device processing [49]. Import- of the AlN nucleation layer is to provide nucleation centres
antly, the interface reaction between GaN and Si is prone to for the GaN crystallites and promote lateral growth of the film
melt-back etching during the epitaxial growth of GaN-on-Si [67]. Consequently, the growth of a high-quality AlN nucle-
at elevated temperatures, leading to the formation of Si-Ga ation layer on Si substrate is crucial for the subsequent high-
alloys and hampering the nucleation of GaN [50]. The main quality GaN or AlGaN epitaxial growth. For example, Lin et al
reason for melt-back etching is the formation of liquid metal [68] obtained low-stress GaN layers on a Si substrate without
Ga on the Si substrate, because the air pressure in the cavity is cracks with the introduction of a series of AlN interlayers.
higher than the vapour pressure of metal Ga and its interaction However, growing high-quality AlN films on Si can be chal-
with Si during the early stages of growth [51]. Meanwhile, the lenging because of the gas-phase parasitic reaction [69]—that
Ga-Si eutectic alloy is formed by interaction with the Si sub- is, insufficient mobility of the AlN species on the Si surface
strate in the 29.77 ◦ C–2237 ◦ C range, especially during the can inhibit structure rearrangement [70] and interfacial reac-
high-temperature stage [52]. During the process of early melt- tions that produce amorphous silicon nitride between AlN and
back etching, a large number of holes and pits in the surface Si can induce a large number of defects [71]. Considering the
of the GaN epitaxy layer are formed, hindering the epitaxial above problems, researchers achieved high-quality AlN film
growth process and causing parasitic conduction and the pre- growth by adjusting the growth conditions to hinder gas-phase
mature breakdown of GaN-based devices [53]. To address the parasitic reactions, improve the mobility of Al-species, and
above problems, a stress management structure grown on Si protect the Si substrate from nitridation [72]—for example, by
is proposed to restrain the melt-back etching process, reduce means of relatively low V/III ratios, and adjusting the growth
threading dislocation density, and eliminate cracks by balan- temperature and the trimethylaluminum pro-dose time. Fur-
cing the epitaxial layer tensile stress [54, 55]. thermore, a high-crystalline quality AlN layer on Si at growth
temperatures above 1100 ◦ C can be achieved [73], whereas the
growth of AlN layers at temperatures above 900 ◦ C can lead
2.2. Stress management structures
to the formation of an inverse channel [74]. Consequently, a
In this section, we discuss the key problems of stress manage- two-step growth method of low and high temperatures to grow
ment for the growth of high-quality GaN thin films on Si sub- the AlN layer has been proposed, which could suppress the
strates and summarise the recent advances in the GaN epitaxy formation of a conducting channel and improve the crystal-
of large-size Si substrates. line quality of the AlN films [75–77]. Although high-quality

4
Semicond. Sci. Technol. 38 (2023) 063002 Topical Review

Figure 2. The structural properties of AlN/Si hetero-interfaces

evaluated by (a) grazing incidence x-ray reflectometry (GIXR)
fitting curves and (b) TEM characterisation for 40 nm thick AlN
films. Reprinted from [87], with the permission of AIP Publishing.

AlN film has been grown on Si substrates at high temperatures Figure 3. Schematic diagram of the growth mechanism for AlN
using MOCVD or MBE [78], the epitaxy technique at low tem- films grown on Si substrates by PLD. Reprinted from [87], with the
perature (LT) has also been explored because the interfacial permission of AIP Publishing.
reactions at high temperatures produce an amorphous layer,
resulting in a high density of dislocations and defects at the of the AlN layer by PLD at LTs on Si, combined with the
AlN/Si interface [79]. growth of other structures by MOCVD at high temperatures,
To address these problems, a pulsed laser deposition (PLD) can be expected to realise the full structure growth of GaN-
technique has been used, which employs a highly energetic based HEMTs.
pulsed laser to ablate the growth target for the diffusion
and migration of AlN precursors on the substrates, to real-
ise the epitaxial growth of nitrides at relatively low growth 2.2.2. Buffer layer. Based on high crystal quality AlN film
temperatures [80]. The LT growth effectively suppresses the on Si substrate, GaN films can be grown on the AlN surface.
interfacial reactions between the films and substrates and However, one is faced with the high density of threading dislo-
avoids melt-back etching, reducing the energy consumption. cations or tensile stress generated during the post growth cool-
In 1995, Vispute et al [81] reported that single crystal AlN thin ing process, which can lead to cracks in the GaN layers when
films had been grown epitaxially on Si substrates by pulsed their thickness exceeds a critical value, especially in the case
laser ablation of sintered AlN targets for the first time. In of GaN epitaxial growth on large-size Si substrates [89]. The
2010, Li et al reported the epitaxial growth of high-quality traps induced by dislocations degrade the device performance,
AlN films by PLD, including insight into the effect of dis- resulting in an increase in buffer leakage. To epitaxially grow
tance between the target and Si substrates on the quality of thick GaN films of high crystal quality, two methods can be
epitaxial AlN films [82], the AlN epitaxial growth mechan- used to solve this problem. First, a thinner GaN layer can be
ism by PLD [83], AlN/Si interfacial reaction inhibition [84], deposited on a thicker or smaller Si substrate [90]; however,
the AlN stress regulation mechanism [85], and the high crystal this approach has no evident advantages in the actual produc-
quality uniformity AlN layer grown on large-size Si substrates tion process. Second, the stress control layer—including the
[86, 87]. In this study, high-quality AlN films were grown on LT-AlN interlayers, AlGaN buffer layer, and Al(Ga)N/GaN
Si substrates by PLD. As shown in figure 2, grazing incid- super-lattice (SL) buffer layer, as shown in figure 4—can be
ence angle x-ray reflectivity and high-resolution transmission applied to grow thick GaN layers of high crystal quality on
electron microscopy were employed to study the properties Si substrates [91–93], compensating for the tensile stress gen-
of AlN/Si hetero-interfaces, revealing AlN films to be 40 nm erated during cool down from the growth temperature to pre-
thick with no interfacial layer existing between the AlN and vent the generation of cracks [94]. In the following section,
Si. The growth schematic diagrams for AlN films grown on Si we describe the three technologies of the stress control layer
substrates by PLD are shown in figure 3. in detail.
However, there were no reports on GaN-based devices with
full structures fabricated by PLD epitaxial growth on Si sub- (1) Theoretically, a single layer of LT-AlN of thickness 10–
strates, mainly due to the limitation of the PLD process, which 20 nm is sufficient to balance the thermal tensile stress
can make it difficult to achieve efficient doping and precisely of a 0.7–1 µm thick GaN-on-Si substrate, while maintain-
control the film thickness. To this end, Wang et al [88] pro- ing or even improving the GaN quality [95]. To grow a
posed a two-step growth method to fabricate GaN-based LEDs thicker GaN layer without cracks on the Si substrate, an
on Si substrates, which was the result of combining the growth alternative technique has been developed to compensate
of LT-AlN templates by PLD at LTs with MOCVD to realise for the tensile strain in thick GaN layers by periodically
LED wafers at high temperatures. Consequently, the growth inserting LT-AlN layers [96]. Since the development of

5
Semicond. Sci. Technol. 38 (2023) 063002 Topical Review

Figure 4. SEM images of (a) multilayer LT-AlN [91]. John Wiley & Sons. Copyright © 2011 WILEY-VCH Verlag GmbH & Co. KGaA,
Weinheim. (b) AlGaN buffer. Reproduced from [92]. CC BY 4.0. (c) Al(Ga)N/GaN SL structure. Reproduced from [93]. © IOP Publishing
Ltd. All rights reserved.

this technique, important progress has been made in terms GaN channel and markedly increasing the VBD of GaN-
of their thickness and crystal quality. In 2011, Dadgar based HEMTs [100]. Recently, there have been numer-
et al [91] adopted a multiple LT-AlN insertion layer to ous reports on the use of AlGaN buffer layers to achieve
grow 14.6 µm thick high-quality crack-free GaN films crack-free GaN epitaxial film [97]. Cheng et al [102] suc-
on Si substrates at wafer scale. By inserting the LT-AlN cessfully fabricated high quality and uniform AlGaN/GaN
layer gradually, the compressive stress induced by GaN heterostructures on Si substrates by employing a single
growth could be relaxed—the last GaN layer being 4.5 µm AlGaN layer with low Al composition, exhibiting a high
thick. Subsequently, Wośko et al [54] altered the V/III µN of 2150 cm2 V−1 s−1 , and an ns of 9.3 × 1012 cm−2
mole ratio during growth of the GaN buffer with an LT- with Rsh at 313 ± 4 Ω sq−1 and ±1.3% variation. Sub-
AlN interlayer to achieve AlGaN/GaN heterostructures on sequently, Li et al [25] proposed carefully step-graded
Si, obtaining a maximum µN of 2057 cm2 V− 1 s−1 and AlGaN buffer layers to grow 3.0 µm thick high-quality
low Rsh of 392 Ω sq−1 in the process. However, stress GaN epitaxial films on Si substrates with full-width at half-
relaxation of the GaN caused many dislocations, result- maximums for GaN (0002) and GaN (1012) x-ray rocking
ing in low GaN crystal quality and limiting the thick- curves of 272 and 297 arcsec, respectively. Although con-
ness of the top GaN layer. Consequently, although a thick siderable progress has been made in exploring high-quality
crack-free GaN film could be obtained by inserting the AlGaN buffer layers, related material growth problems
multi-layered LT-AlN buffer, it was not suitable for the remain—including the precise control of composition and
preparation of HEMTs with strict GaN crystal quality thickness using graded AlGaN and the interface roughness
requirements. of AlGaN alloy materials. Consequently, improvements in
(2) AlGaN buffer layers include step-like graded AlGaN [97] the crystalline quality of step-graded and compositionally-
and linearly graded AlGaN structures [98, 99], where the graded AlGaN structures remain pre-requisites for fully
Al composition gradually changes from an AlN nucle- unleashing the potential of AlGaN buffer layers.
ation layer to GaN [100], the gradual change of the lat- (3) The Alx Ga1−x N buffer layer with high Al content suf-
tice constant and thermal expansion coefficient from AlN fers from numerous defects and a large surface roughness.
to GaN being achieved by the graded AlGaN buffer layer Nonetheless, in addition to AlGaN buffer layers, Al-rich
[101]. On the one hand, the AlGaN buffer layers between SL buffer layers used as stress buffer layers are among the
the AlN and the GaN introduce compressive stress dur- most commonly used schemes to grow GaN films [105].
ing the growth process to compensate for the tensile stress The SL buffer layer consists of a modulated doped SL and
generated during cool down from the growth temperature, component SL with periodic multilayer structures formed
improving the crystal quality and surface roughness of the by alternating the growth of two different doped semi-
GaN film [102, 103]. More importantly, this helps pre- conductor films or films of different compounds. Al-rich
vent wafer bending, dislocation formation, and cracking, SL structures were developed to simulate a continuous
improving crystalline quality and the performance of GaN- thick AlN layer, which could compensate for the strain
based devices—including the leakage current and break- using compressive strain [101, 106]. Moreover, a SL buf-
down voltage [104]. On the other hand, AlGaN buffer lay- fer can play the role of filtering dislocations, being super-
ers act as back barrier layers beneath conductive channels, ior in terms of vertical isolation compared to a graded
effectively providing better electron confinement in the buffer [107], which can be attributed to the existence of

6
Semicond. Sci. Technol. 38 (2023) 063002 Topical Review

the strain field, which is capable of reducing the bend- can be found in the structural, electrical, and optical properties
ing and density of dislocations by changing the propaga- due to temperature variations across the wafer. These could
tional direction and speed of dislocation [108]. The SL result in the non-uniformity of device properties at various
layer as a buffer structure has made considerable pro- positions on the wafer.
gress over several years since its initial fabrication [109]. Despite these challenges, GaN grown on large-size Si sub-
Subsequently, Al-rich SL structures—including AlN/GaN strates has still been studied closely due to its enormous market
[107], Alx Ga1− x N/Aly Ga1−y N [110], and Alz Ga1− z N/AlN potential. Recently, considerable progress has been made in
SL structures [111] have been employed as buffer lay- the growth of GaN-based materials on large-size Si substrates
ers to counterbalance the tensile strain of GaN-on-Si. In using the above three buffer structures. Lin et al [117] obtained
2014, Shen et al [112] reported an AlGaN/GaN hetero- crack-free GaN film grown on large-area Si substrates using
structure grown on a Si substrate by MOCVD, incorpor- multilayer AlN combined with a graded AlGaN layer as a
ating an AlN/GaN SL interlayer structure. Based on the buffer layer to balance stress. Frayssinet et al [118] used one
SL layer, an AlGaN/GaN heterostructure was grown with AlN interlayer to reduce the tensile strain generated during the
µN and ns achieving values of ∼1500 cm2 V−1 s−1 and growth of 4 µm thick GaN film on the 100 and 150 mm Si
1.2 × 1013 cm−2 , respectively. Ni et al [108] prepared substrates by MOCVD. Liu et al [119] demonstrated a GaN-
different periods (4, 8, 30, and 40) of AlN/GaN SL and based HEMT structure grown on a 150 mm diameter Si sub-
30 periods of AlN/GaN SL with relative AlN thicknesses strate by MOCVD employing high-temperature step-graded
(from 8% to 30%) for GaN-based HEMTs. This work Alx Ga1x N/AlN buffer layers. Su et al [120] demonstrated the
demonstrated that the strain state of the top GaN layer uniform growth of AlGaN/GaN on 200 mm Si substrates using
could be adjusted from tensile to compressive by increas- MOCVD, thickness uniformity of GaN by the contour map
ing the number of SL periods and/or the relative AlN thick- and histogram plot from photoluminescence, and crystal qual-
ness in the SL. Consequently, SL structures have shown ity at multiple locations from x-ray diffraction (XRD) meas-
that the epitaxial layers have a perfect heterojunction inter- urement as shown in figures 5(a)–(c). Moreover, the thick-
face and crystal quality, and that they can lower the dis- ness variation of GaN is 10% and the FWHM variation of
location density, and exhibit superior blocking voltage GaN (002) is <1.4%. From the above results, they revealed
capabilities with a lower trapping and a higher effective that the µN and ns achieved values of 1800 cm2 V−1 s−1
bandgap. and 1.0 × 1013 cm−2 , respectively, by Hall-effect measure-
ments. Furthermore, to verify the uniformity of 2DEG elec-
Among the above three buffer layer structures, the graded trical characteristics, these variations in the sheet resistance,
AlGaN and SL structures have been considered to be feasible mobility, and sheet carrier concentration of the GaN HEMTs
buffer structures for fabrication of GaN-based HEMTs on Si on Si were also measured. Hoke et al [121] examined the
substrates. Next, GaN-based materials grown on large-size Si highly uniform sheet resistance by a contour map created from
substrates is outlined. 29 measurements on 200 mm Si substrates, showed the aver-
age sheet resistance was 451.4 Ω sq−1 with a standard devi-
ation of 1.1% as shown in figure 5(d). Su et al [120] repor-
2.2.3. Epitaxial GaN growth on large-size Si substrate. ted the average 2DEG mobility, sheet carrier concentration,
Based on previous research, high-quality GaN-based HEMT and sheet resistance from 5 points (−90, −45, 0, 45, and
structures were grown on 50 and 100 mm diameter Si 90 mm) across the wafer, as seen in figure 5(e) with variations
substrates [105]. Consequently, to further highlight the cost <1.3%. Christy et al [122] used an Al0.3 Ga0.7 N buffer com-
advantages of GaN-based HEMTs on Si, the development of bined with a SL structure as a buffer layer to control strain
epitaxial technology with 150 mm and larger diameters has counterbalance on a 200 mm Si substrate, successfully achiev-
become a research hotspot [113]. Increasing the Si substrate ing a crack-free and high-crystalline quality AlGaN/GaN het-
size from 150 to 200 mm has the benefit of a ∼78% lar- erojunction with a maximum µN of 1500 cm2 V−1 s−1 and ns
ger wafer area, substantially reducing the cost of GaN-on-Si of 1.52 × 1013 cm−2 . Ikejiri et al [123] measured the vertical
power HEMTs comparable with Si-related equipment in the Si leakage current of GaN HEMTs using a 1/4 cleaved grown
industry [114]. However, the tensile stress generated in GaN wafer. The results showed high yield characteristics (vertical
epitaxial wafers on large diameter Si can create more severe blocking voltage >700 V) of over 96% on a 150 mm wafer and
problems [115]. First, GaN epitaxial films grown on the large that of 94% on a 200 mm wafer as shown in figures 5(f) and (g).
diameter Si exhibit a pronounced bowing effect, leading to The uniformity of AlGaN/GaN heterojunctions on large-size
a higher density of misfit and threading dislocations [114]. Si substrate has been systematically analysed from the mater-
Second, this strain varies throughout the process owing to the ial thickness, crystal quality to uniformity of 2DEG electronic
large thermal mismatch between Si and GaN, and can lead characteristics. With the continuous advancement of GaN epi-
to a temperature gradient through the wafer from underside taxial technology, substantial progress has been made in the
heating, which can increase the height at the wafer edge on growth of GaN on 300 mm high-resistivity (HR) Si substrates
a level surface from 56.2 µm (150 mm Si wafer diameter) to [23]. Presently, GaN films grown on 200 mm Si substrates are
100 µm (200 mm Si wafer diameter) [116]. Moreover, during available for purchase from manufacturers such as Innoscience
the growth of GaN on large-size Si substrates, non-uniformity and Enkris Semiconductor Inc.

7
Semicond. Sci. Technol. 38 (2023) 063002 Topical Review

Figure 5. Thickness uniformity and crystal quality of AlN and GaN on 200 mm Si. (a) AlN thickness, 0.71%, 1 s, [120] John Wiley &
Sons. Copyright © 2016 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim. (b) GaN thickness, 0.67%, 1 s, [120] John Wiley & Sons.
Copyright © 2016 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim. (c) crystal quality of AlN and GaN across the 200 mm Si wafer.
(a)–(c) [120] John Wiley & Sons. Copyright © 2016 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim. (d) Sheet resistance contour
map of an AlGaN/GaN HEMT created from 29 measurements taken across a 200 mm wafer. The average sheet resistance is 451.4 Ω sq−1
with a standard deviation of 61.1%. Reproduced from [121]. CC BY 4.0. (e) 2DEG properties by Hall measurement. [120] John Wiley &
Sons. Copyright © 2016 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim. (f)–(g) Vertical blocking voltage map and table of counts
and probability ratio for each Vb category, evaluated through multi-point vertical leakage current measurements (electrode area: 5 mm2 ).
Reproduced from [123]. © IOP Publishing Ltd. All rights reserved.

2.3. High-resistance GaN buffer structure age current and degrading the breakdown voltage [126, 128].
Consequently, it is extremely important to compensate for
After developing the key technology of GaN-based materi-
the background electron concentration and realise the high-
als on Si substrates, thick GaN films of high crystal qual- resistance GaN buffer layer without increasing the layer thick-
ity on large-size Si substrates could be achieved. For high- ness of the GaN-based HEMTs on Si. Currently, one approach
power switching applications of GaN-based HEMTs on Si, is to introduce edge-type dislocations containing acceptor-like
the increased power density compared to conventional Si states, such that they can capture electrons in the GaN by
MOSFET arises from a combination of a high V BD and large means of N-type background impurity compensation. Another
current [124]. Furthermore, high-resistance buffer layers are approach is to dope GaN and introduce an acceptor state to
indispensable in GaN-based HEMTs on Si for improving V BD . compensate for the background N impurity, thus achieving
From a material point of view, this is limited to improving high-resistance GaN.
V BD by increasing the thickness of the buffer layer [125]. In this way, the growth conditions can be tuned to intro-
However, this can lead to unintentional n-type doping due to duce a high density of deep acceptors caused by the dislocation
impurities—such as Si or O—and small inherent point defects density to realise a high-resistance buffer layer [129], which
in unintentionally doped GaN—such as N and Ga vacancies— indicates the absence of additional reactor contamination.
in the epitaxial growth of high-quality GaN. This can result in Yakimov et al [130] reported a high density of deep acceptors
intrinsic n-type doping for GaN with a rather high background with levels near Ev + 0.35 eV in the GaN buffer layer, which
carrier density of 1016 –1017 cm−3 [126]. The high background was produced using a high dislocation density to achieve
carrier density could cause vertical and lateral leakage paths HR materials. However, introducing a high dislocation dens-
(figure 6(a)) in the GaN-based HEMTs [127], which can ity unavoidably results in the degradation of the GaN-based
be detrimental to device characteristics, increasing the leak- HEMT properties, as dislocation lines may serve as vertical

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Semicond. Sci. Technol. 38 (2023) 063002 Topical Review

Figure 6. (a) Schematics of buffer trapping and primary OFF-state leakage paths (gate leakage I G , lateral leakage through buffer Is , and
vertical leakage I sub ) in lateral GaN-on-Si devices. The arrows show the electron flow direction. Carrier injection from the Si substrate can
be correlated with both buffer trapping and I sub , ultimately limiting V BD . © 2017 IEEE. Reprinted, with permission, from [127]. (b) Fe
distribution with and without exponential tail used in simulations. The shaded areas show the concentration of ionised Fe atoms at
equilibrium. Symbols are experimental SIMS depth profiles of Fe. Calculated conduction-band energy with and without an Fe exponential
tail and without Fe-doping. (b) Reproduced from [139]. CC BY 4.0. (c) SIMS profile showing carbon concentration in the C1 region of the
buffer layer. (d) Lateral leakage current versus applied voltage data of samples A–D at room temperature. (e) Breakdown voltage defined at
1 µA mm−1 plotted as a function of C-doping. The model between C-doping and breakdown voltage shows three regions. (f) The
measurement setup for buffer leakage measurements. (c)–(f) © 2020 IEEE. Reprinted, with permission, from [126].

leakage paths and the characteristics of 2DEG can be enorm- (1) Fe, mainly originating from a ferrocene precursor (Cp2 Fe,
ously affected. More importantly, its shortcomings—such as bis(cyclopentadienyl)iron), is a compensational deep-level
low reproducibility—could delay its commercial application dopant that produces a highly resistive Fe-doped buffer
as the mechanism between the insulating GaN buffer layer of GaN-based HEMTs by MOCVD [137]. The Fe-doped
and the growth conditions is not yet clear. Consequently, it buffer layer is located at +0.5 to +0.7 eV (figure 6(b))
is essential to develop a highly reproducible process to realise below the conduction band [138, 139]. Studies suggest
a high-resistance GaN buffer layer. that a highly resistive (>1 GΩ sq−1 ) GaN-on-Si can usu-
This, researchers have been committed to achieving high- ally be achieved at lower Fe concentrations in the range of
resistance GaN by artificially introducing compensational 1017 cm−3 as shown by secondary ion mass spectroscopy
deep-level dopants in the GaN buffer, such as iron (Fe) [131], (SIMS) measurements [36, 131]. In fact, many recent
magnesium (Mg) [132], manganese (Mn) [133], carbon (C) reports have indicated that GaN-based HEMTs with an
[126, 134], zinc (Zn) [135], and chromium (Cr) [136], which Fe-doped GaN buffer on Si successfully suppress prema-
has become an important method of achieving high-resistance ture failure caused by Si-induced breakdown, and exhibit
GaN and effectively control bulk leakage. Among them, the a lower leakage current and higher VBD when compared
most common dopant used in high-resistive GaN buffers is with conventional devices [36, 140]. For example, Chiu
obtained by means of Fe- or C-doping—that is, they form deep et al [141] successfully fabricated high-performance GaN-
acceptors, which act as electron traps. based HEMTs with a lower I GS of 8.22 × 10−6 mA mm−1

9
Semicond. Sci. Technol. 38 (2023) 063002 Topical Review

and V BD,buffer of 1324 V through intentional Fe-doping dopant distribution be adjusted. That is, to better control
into a GaN buffer layer with an Fe-doped concentration of the C-doped concentration in GaN-based HEMTs, it is
8 × 1017 cm−3 . During growth, the Fe-doped GaN buffer extremely important to design the epitaxial structure and
layer is ensured of doping regardless of the growth con- change growth conditions for the incorporation of C by
ditions, exhibiting a linear dependence on the precursor MOCVD.
partial pressure [128]. However, it has the drawbacks of
unintentional Fe impurity incorporation from the memory Unfortunately, plenty of bulk traps or buffer traps exist
effect and surface diffusion/segregation of an Fe precursor, in the GaN buffer stack grown on Si substrate, resulting
potentially causing Fe contamination of the active region from high-density (108 –1010 cm−2 ) of crystalline defects or
which can degrade the device characteristics [125]. dislocations and traps induced in the C/Fe-doped GaN buf-
(2) C-doping has been proposed and introduced in GaN buf- fer due to the large lattice mismatch and huge difference in
fers on either the N or Ga site to reduce the leakage current thermal expansion coefficients between GaN and Si substrate
of GaN-based HEMTs for power switching applications [127, 153]. Previous studies have shown that the use of buf-
[142]. Based on recent theoretical calculations and spec- fer doping may enhance charge-trapping effects, resulting
troscopy measurements [143], C has a complex range of in channel electrons being captured by the trap in the buf-
deep levels in the gap, whereas CN —as a deep acceptor fer and limiting the dynamic performance of the devices
in n-type GaN sitting 0.9 eV above the valence band— [152, 154, 155], such as dynamic RON and Coss losses.
is more important [144]. C-doping as a deep acceptor Due to the time-dependent electron trapping/de-trapping in
is most commonly used to control the resistivity of the the HEMT structure, the transient V BD of GaN HEMTs is
GaN buffer, which reduces the background carrier concen- also dynamic or time dependent [156]. Such behaviour was
tration by yielding the compensating centres to improve mainly ascribed to the V BD of GaN HEMT. It is determ-
the OFF-state blocking voltage [128]. The source of C- ined by the peak electric field (E-field) in GaN-based mater-
specific impurities originates primarily from intrinsically- ials because the traps in GaN HEMTs impacts the E-field
doped GaN with trimethyl gallium [145] or extrinsically- distribution [157]. Compared to the static V BD , the dynamic
doped GaN, such as propane and ethylene [146]. Yacoub V BD , was found to be generally 65%–200% higher than the
et al [147] compared these two doping methods and con- rated voltage, and it was frequency-dependent [158]. Cur-
firmed that extrinsic doping delivers better dynamic prop- rently, research on traps in the GaN buffer has primarily
erties for AlGaN/GaN HEMTs. However, the source of focused on understanding their physical mechanisms [159]
C-specific impurities and the formation energies of C- and minimising the current collapse [134, 139]. Joshi et al
doped GaN is closely related to the MOCVD growth con- [160] reported the reduction of C-doping-induced acceptor
ditions, such as temperature, pressure, and the V/III ratio trap concentration without affecting V BD of the GaN HEMT,
[148]. HR GaN layers of relatively high crystal quality can resulting in an improved dynamic RON . Furthermore, some
be prepared by using optimal growth conditions. Lesnik novel buffer structures were proposed such as SL buffer
et al [149] and Remesh et al [126] showed that C-doping structures [150], AlGaN back barrier [161], and AlN insert
for GaN buffer layers increased from [C] = 5 × 1017 layer [162]. The Coss loss at high frequencies can be reduced
to 1.2 × 1019 cm−3 for semi-insulating properties using up to 70% by the buffer engineering [163]. Furthermore, find-
SIMS, increasing the lateral breakdown voltage of the ings about the dynamic V BD physics and ruggedness of GaN
power devices (figure 6(c)). However, figures 6(d)–(f) HEMTs have provided important new insights [164, 165].
show the GaN-based device with highest breakdown does These solutions can provide a highly insulating buffer with
not correspond to the buffer layer with the highest carbon a good crystal quality or an electrostatic barrier to chan-
content because of the formation of shallow donor traps nel electrons for limiting leakage and improving dynamic
by carbon atoms occupying Ga vacancies (CGa ) [126]. A C behaviours.
doping around mid-1019 cm−3 is expected to be optimum Therefore, although C/Fe-doping in the GaN buffer intro-
for the GaN buffers for high lateral breakdown voltages duced the traps, this is still the most effective way to sup-
[126]. Furthermore, Heuken et al [150] demonstrated the press current collapse of GaN HEMTs. Among the two meth-
C-doped AlGaN/AlN SL buffer structure for GaN-based ods, Fe-doping in the buffer layer can result in unintentional
HEMTs grown on 200 mm Si, which can be expected to Fe impurity incorporation from the memory effect and sur-
result in a low buffer leakage and reasonable breakdown face segregation of an Fe precursor during growth. Com-
margin for 650 V operation. Moreover, the C-doping of pared to Fe-doping, the C-doping process has no memory
GaN buffer layers for GaN-based HEMTs can be helpful in effects—which can control the doping concentration in dif-
obtaining a high V BD . However, detrimental effects—such ferent layers—enabling better control of the impurity level in
as C-related dispersion, threading edge dislocations, and the channel region. Furthermore, C-doping in the buffer layer
diffusion of C into neighbouring epilayers at increased C is currently the simplest process and is suitable for industri-
concentrations—have been reported for C-doping in GaN- alised production, whether involving intentional or uninten-
based HEMTs, leading to a lower electron mobility of the tional doping. However, excellent epitaxial materials are not
AlGaN/GaN heterojunction [151]. Based on these prob- limited to the high-resistance buffer layer, but also come from
lem, Trankle et al [152] proposed that the doped buffer the GaN channel heterojunction with high electron mobility.
be placed away from the channel layer, and that the C The high electron density arises from the 2DEG formed by the

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Semicond. Sci. Technol. 38 (2023) 063002 Topical Review

Figure 7. (a) The 2DEG concentration and mobility variation in samples A1, A2, and A3. Reprinted from [175]. Copyright (2020), with
permission from Elsevier. (b) Measured (solid) and simulated (dashed) carrier concentrations and sheet resistances in different
multi-channel structures. (c) Simulated band structure and carrier concentration (N3D ) of the five-channel wafer chosen for device
fabrication. The sheet carrier concentration in each channel (N2D ) obtained by integrating N3D in the quantum well is indicated. (b) and (c)
© 2020 IEEE. Reprinted, with permission, from [185].

heterojunction of the GaN-based power HEMTs, discussed in 1820 cm2 V−1 s−1 and Rsh as low as 211 Ω sq−1 could
detail in the next section. be obtained by reducing strain during growth. Moreover, as
an alternative concept, AlN/GaN SL structures consisting of
thin alternating AlN-GaN layers were proposed [176, 177],
2.4. (In)Al(Ga)N/GaN heterojunction which could enhance the polarisations to improve µN and
Materials used to improve GaN-based HEMT power device ns by simply increasing the Al composition during growth,
performance play a prominent part in reducing the sheet res- which could reduce alloy disorder scattering and maintain
istance (Rsh ) and enhancing the polarisation effect in the het- similar breakdown characteristics compared with conven-
erostructure of GaN-based HEMTs. Rsh is related to the carrier tional AlGaN-channel HEMTs [178]. For example, Shimizu
mobility (µN ) and the sheet carrier concentration (ns ) can be et al [178] fabricated GaN-based HEMTs using an ultrathin
expressed as follows: GaN/AlN SL as a barrier layer, showing the 2DEG Rsh , ns ,
and µN values to be 250 Ω sq−1 , 1.6 × 1013 cm−2 , and
1520 cm2 V−1 s−1 , respectively. Based on this SL structure,
1
Rsh = , (2) better performances than those of conventional AlGaN/GaN
ns eµN structures could be demonstrated, which could be applied to
high-power and high-frequency device applications.
where Rsh is intrinsically determined by the electric conduct- Compared to the AlGaN/GaN heterostructure, AlN/GaN
ivity of 2DEG; and ns and µN denote the electrical parameters heterostructures with all-binary alloyed AlN exhibited no dis-
of 2DEG. This finding reveals that ns and µN are related to the orderly scattering of the AlGaN ternary alloys and a stronger
polarisation effect and roughness scatterings caused by alloys polarisation effect, which improved the 2DEG ns and µN [179].
of the (In)Al(Ga)N/GaN heterojunction [106, 166]. Theoretically, the ns of AlN/GaN heterostructures can exceed
Currently, the (In)Al(Ga)N/GaN heterojunction of GaN- 5 × 1013 cm−2 for extremely thin AlN barriers (⩽6 nm)
based HEMTs includes AlGaN/GaN, InAlN/GaN, AlN/GaN, due to the combination of maximum spontaneous piezoelec-
GaN/AlN SL barrier layers and multi-channel AlGaN/GaN tric polarisations [180]. In 2020, Yang et al [179] achieved
layers [167–172]. In the traditional heterojunction, the a low Rsh in the AlN/GaN heterostructure on Si substrate,
AlGaN/GaN structure is most used to fabricate GaN-based which exhibited very a low Rsh of 85 Ω sq−1 , a high µN of
HEMTs. Generally, spontaneous and piezoelectric polarisa- 2470 cm2 V−1 s−1 , and a corresponding ns of 3.0 × 1013 cm−2 .
tion allows AlGaN/GaN heterojunctions of thickness ∼20– However, it can be difficult to control the growth of an ultrathin
25 nm and an Al mole-fraction of ∼20%–25%, featuring a AlN barrier layer on GaN and to obtain excellent electrical
2DEG density well above 1013 cm−2 . Although the 2DEG car- characteristics. For example, AlN/GaN HEMTs may suffer
rier density increases considerably with the Al-rich AlGaN from large gate leakage currents and a low gate breakdown
barrier due to spontaneous polarisation [173], the mobility voltage due to the thin AlN barrier layer [181]. Consequently,
and sheet resistance can be affected due to the alloy scat- it must be well protected or deposited on a dielectric layer.
tering induced surface deterioration of the Al-rich AlGaN Meanwhile, lattice matching Inx Al1− x N/GaN (x ∼ 17%) het-
barrier and the increasing lattice mismatch, as shown in erostructures offer several additional advantages owing to
figure 7(a) [174, 175]. To increase the 2DEG carrier density their larger band gap discontinuity (∆Ec ∼ 0.68 eV), which
while keeping high mobility, Yamada et al [173] reported provides more than twice the 2DEG ns (2–3 × 1013 cm−2 )
that Al-rich Al0.6 Ga0.4 N/GaN HEMTs with µN as high as [182].

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Semicond. Sci. Technol. 38 (2023) 063002 Topical Review

In 2020, Xing et al [183] reported In0.17 Al0.83 N/GaN considered to be a solution, effectively raising the GaN con-
HEMTs grown on a HR 200 mm Si substrate, in which duction band of the AlGaN/GaN HEMTs above the Fermi
the 2DEG had an average Rsh of 206.4 Ω·sq−1 , ns of level and pinching off the 2DEG at a zero gate bias [189, 190],
2.27 × 1013 cm−2 , and µN of 1430 cm2 V−1 s−1 . This het- as shown in figure 8(a). Recently, numerous studies have
erostructure produced a high drain current density and an been conducted on the growth of p-(Al)GaN structures [188].
unstrained barrier, which led to improved device DC char- A p-(Al)GaN layer with an Mg-doping concentration of
acteristics and reliability. However, the high-quality InAl- ∼3 × 1019 cm−3 , thickness of 60–150 nm, and hole concen-
N/GaN heterostructures was limited by the different growth trations of 1017 –1018 cm−3 is usually required to fully deplete
temperatures (more than 200 ◦ C) between InN (growth 2DEG electrons with a density of ∼1013 cm−2 [191–193] as
at LTs < 800 ◦ C) and AlN (grown at high temperat- shown in figures 8(b) and (c). Furthermore, whether the 2DEG
ures > 1000 ◦ C) binary alloys [184]. under the gate can be exhausted is related to key aspects,
The above-mentioned heterojunction was based on a single including the design of the barrier layer, the growth of p-GaN,
channel structure. Recently, multi-channel heterostructures— and the high barrier height of metals on p-GaN [194]. Among
where several AlGaN/GaN layers can be stacked to achieve these factors, the growth of p-GaN plays a crucial role in
multiple 2DEGs—have been proposed to induce more car- exploiting E-mode HEMTs with a higher and stable threshold
riers, avoiding problems induced by high-Al-content barrier voltage (V TH ). Although the Mg-doping concentration of p-
materials and the parasitics introduced at the interconnections GaN has reached 1020 cm−3 , the Mg activation efficiency of p-
[185]. By doping the AlGaN barrier layer, the electrical prop- GaN is lower than 1% (a hole concentration of approximately
erties of the heterojunction linearly increase when doping in 1017 cm−3 ) after annealing at temperatures higher than 700 ◦ C
the second or additional barrier layers, and greatly improve due to limitations on the high activation energy of acceptors
the current driving ability of the device [186]. Erine et al [185] (160–180 meV) in Mg-doped GaN and formation of Mg-H
fabricated and simulated a series of multi-channel wafers with bonds during growth [195]. This is related to growth paramet-
different multi-channel structures, as demonstrated by the ns ers such as the Mg flow, growth temperature, growth time, and
and Rsh , as shown in figures 7(b) and (c). Furthermore, the five- thermal annealing conditions [193, 195, 196].
channel structure obtained a low Rsh of 103 Ω sq−1 , a total ns However, increasing the Mg concentration above
of 4.03 × 1013 cm−2 , and a µN of 1650 cm2 V−1 s−1 by Hall- 2 × 1019 cm−3 does not increase the hole concentration
effect measurements. Nela et al [187] reported a multi-channel [197]. During MOCVD growth, the problems associated
nanowire-based HEMT with a low Rsh of 83 Ω sq−1 , a large ns with Mg doping for higher hole concentrations include: (1)
of 3.9 × 1013 cm−2 , and a very high µN of 1930 cm2 V−1 s−1 , a large volume of crystal defects being introduced by mag-
nearly four times higher than that of conventional AlGaN/GaN nesium ion implantation [198]; (2) the low p-type activation
single-channel structures. These results convincingly demon- of Mg-H into GaN, which can lead to higher resistivities than
strated that an extremely small Rsh value of multi-channel those with similar hole concentrations [199]; (3) the self-
structures could be achieved, despite the high µN . However, compensation effect due to the nitrogen vacancy donor (VN )
a serious self-heating effect was evident in multi-channel het- and its complexes, which determines its resistivity [200], (4)
erojunction devices, which could lead to the degradation of the Mg segregation on threading dislocation, which can lead
device performance. to degraded crystal quality and defects [194], and (5) Mg dif-
Alloy disorder scattering can be considerably reduced by fusion, which can induce an increase in the 2DEG Rsh and
inserting a 1 nm AlN layer between the high-Al-content bar- V TH shifts [201]. To date, several growth techniques have
rier layer and the GaN layer, which in turn enhances the trans- been shown to solve the above problems—such as the defect
port properties of the channel. The high-Al-content barrier, quasi Fermi level control process [199], chemical potential
AlN/GaN SL, InAlN/GaN, AlN/GaN, and multiple channel control [202], metal modulation epitaxy [203], phase shift
heterojunctions have all been extensively explored to increase epitaxy [204], and the use of an AlN interlayer between the
the 2DEG ns . They present excellent DC and dynamic char- p-GaN and AlGaN structures [193]. Based on the contribu-
acteristics, demonstrating the potential of this technology tions of numerous researchers, Dai et al [193] reported that a
for future power devices. For enhanced GaN-based HEMT hole concentration of 1.3 × 1018 cm−3 with a high activation
devices, the increased 2DEG density yields a more negative efficiency of 2.2% was achieved in the p-GaN/AlN/AlGaN
VTH , which could be detrimental to achieving a normally-OFF structure. Chiu et al [205] reported that a p-GaN layer with
operation based on current technical levels. Consequently, we a hole concentration of 1 × 1018 cm−3 was achieved, which
next discuss how to exhaust the 2DEG to realise enhanced exhibited a V TH of 2.1 V, as shown in figure 8(d). Ke et al [206]
devices at a material level. reported that a high Mg activation efficiency of 5% could be
achieved for p-GaN films. These results can be ascribed to
2.5. P-GaN/(In)Al(Ga)N/GaN structure
the reduced H-passivation of p-GaN, the increasing activation
rate at the same Mg-doping level, and the reduced diffusion of
High-quality (In)Al(Ga)N/GaN HEMTs are normally-ON Mg atoms. As research progresses, the hole concentration of
devices. However, the normally-OFF function of GaN-based p-GaN will undoubtedly increase further, and the VTH of GaN-
HEMTs can be indispensable for power switching applications based HEMTs will likewise improve. Nowadays, the adjust-
[188]. For most common, commercially available normally- ment of material structures and growth technology tend to be
OFF GaN-based HEMTs, the p-GaN/AlGaN/GaN structure is stable—that is, GaN-based HEMTs are available in the market

12
Semicond. Sci. Technol. 38 (2023) 063002 Topical Review

Figure 8. (a) Energy band structure at the gate position for composite barrier (CB) and standard (STD) p-GaN gate HEMTs.
(b) Cross-sectional structure, TEM images, and AlN etching stop layer of CB p-GaN gate HEMTs. (c) The hole concentration (red solid
squares) and activation efficiency (open squares) of the p-GaN:Mg layer as a function of the Mg-doping concentration. (d) The I DS −V GS &
I GS −V GS transfer and I DS –V DS output characteristics of both devices, the V TH distribution of 30 samples for STD and CB p-GaN HEMTs.
(a) and (d) Reproduced from [205]. CC BY 3.0. (b) © 2018 IEEE. Reprinted, with permission, from [192]. (c) Reproduced from [193]. CC
BY 4.0.

and used in the process of device fabrication. Consequently, applications is reviewed in this section. Figure 9 shows two
the key factors that determine the material properties in device kinds of GaN-based HEMTs on Si structures—that is, the
structure design and their mechanisms are summarised in the metal–insulator semiconductor (MIS)-GaN and p-GaN gate
following sections. HEMTs. Consequently, device isolation processes—such as
mesa dry etching and ion implantation—are analysed in depth
in section 3.1, after which the ohmic contacts technology used
3. GaN-based HEMT fabrication process to decrease the barrier height of metal on AlGaN are dis-
cussed in section 3.2, with a discussion on the technologies for
In recent years, substantial fabrication technology advances normally-OFF operation being concluded in section 3.3. The
have been made in GaN-based HEMTs for power elec- gate contact engineering including the MIS and p-GaN gate
tronic applications with the development of epitaxial growth HEMTs structures are summarised in section 3.4. Passivation
techniques of GaN-based materials on Si substrates, since and field plate (FP) engineering are reviewed in section 3.5.
Chumbes first reported AgaN/GaN heterostructures on Si From a high-power switching application viewpoint, this
substrates in 2001 [207]. Recent progress in the prepar- fabrication technology aims to improve the performance of
ation of GaN-based HEMTs on Si for power electronic GaN-based HEMTs, which demands gate control and specific

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Semicond. Sci. Technol. 38 (2023) 063002 Topical Review

Figure 9. (a) MIS-GaN HEMTs and (b) p-GaN gate HEMTs.

conduction characteristics, including a low ON-resistance,

positive V TH , low gate-leakage current, and high breakdown
voltage. Furthermore, as a power switching device, the switch-
ing frequency, conduction losses, and switching losses should
be considered. Additionally, the switching time is determ-
ined by charge and discharge times of the gate-drain capacit-
ance CGD due to the Miller effect [208]. The conduction loss
depends on the ON-state resistance (RON ), whereas the switch- Figure 10. Three-dimensional schematics of AlGaN/GaN HEMTs
ing loss depends on the gate charge (QG ) [8]. A figure of merit isolated by (a) 131 Xe+ implantation and (b) mesa etching. (a) and
(b) [212] John Wiley & Sons. Copyright © 2017 WILEY-VCH
(FOM) RON ·QG is proposed, and decreasing FOM provides Verlag GmbH & Co. KGaA, Weinheim. Silvaco ATLAS-simulated
technological improvement [209]. electric-field distribution (linear scale, units: MV cm−1 ) for the
mesa-etched device (c) and implanted device (d). A voltage of
1200 V is applied between two ohmic contacts. The inset figures
3.1. Device isolation show the electric field in the vertical direction. (c) and (d)
Reproduced from [218]. © IOP Publishing Ltd. All rights reserved.
In device fabrication, device isolation is a fundamental process
of GaN-based HEMTs on Si substrates, engaged to separate
the 2DEG electrical connection of every GaN-based HEMT as SiO2 , SiNx , or Al2 O3 —can also be deposited, leading to
on a wafer. Device isolation plays a crucial role in exploit- a lower gate-leakage current and a higher buffer breakdown
ing the power capabilities of GaN by limiting leakage currents voltage.
and high electric fields on the wafer [210]. Commonly used To avoid problems introduced by plasma dry etching, other
GaN-based HEMT isolation methods include mesa dry etch- isolation processing and implantation isolation technology can
ing and ion implantation [211, 212], as shown in figures 10(a) be used to achieve planar device isolation in AlGaN/GaN
and (b). Moreover, one of the device isolation processes can HEMTs using different ion species with multiple energies
be achieved by mesa etching techniques using a BCl3 /Cl2 and doses—such as N+ , P+ /He+ , O+ , Fe+ , Ar+ , Kr+ , and
as plasma source—for example, using inductively coupled Zn+ [219–225]. This can produce lattice damage, introdu-
plasma (ICP) or reactive ion etching [211]. This is a relat- cing a large volume of deep-level defects to reduce the car-
ively simple process and has the advantages of the low cost of rier concentration in the injection region and creating highly
process equipment. Consequently, it has been widely accep- resistive regions in the AlGaN/GaN HEMT structure. To date,
ted by a large number of researchers [213–215]. However, several research groups have studied the impact of factors
such processes may also increase the degradation of device affecting ion implantation, such as implanted ion types ran-
performance—such as I GS and V BD —due to plasma etching ging from heavy ions to light ions, and the temperature of
damaging the side wall where the mesa is induced [216]. More post-implantation thermal annealing [211, 218]. To achieve
importantly, the passivation layer is introduced to passivate high resistance regions using ion implantation, Taube et al
mesa side walls, which can add an additional leakage path [226] examined the effect of annealing temperature on Rsh
owing to the direct contact of 2DEG with passivation layer, after Al+ and C+ ion implantation, and demonstrated that isol-
yielding a substantial IGS and non-uniform V BD [217]. ation was stable up to 600 ◦ C (Rsh ∼ 1 × 1012 Ω sq−1 ) for
Sun et al [218] simulated the electric-field distribution both Al+ and C+ ions. Simultaneously, to study the break-
between the source and drain pads isolated by the mesa etch, down induced by ion implantation, Lo et al [219] showed
as shown in figure 10(c). The mesa etch structure not only that the N ion-implantation isolation of AlGaN/GaN HEMTs
shows a higher peak electric field, but also a high electric yielded a higher isolation V BD of 900 V with a leakage cur-
field near the metal edge, which extends deeper into the GaN rent of 1 µA mm−1 . The ion-implanted isolation on the GaN-
buffer (as shown in the inset), this being the reason for its based HEMT device can provide good device isolation by cre-
higher I GS . To tackle this problem, a blocking layer between ating a highly resistive region on the sidewall of the device
the gate metal and the sidewall of the 2DEG channel—such [211]. Conversely, it maintains the planarity of the chip to

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Semicond. Sci. Technol. 38 (2023) 063002 Topical Review

avoid the gate from touching the 2DEG channel at the mesa- 3.2.1. Thermal annealing technique. For conventional
sidewalls, which can result in the reduction of the gate-leakage ohmic metal schemes—such as Ti, Al, Ni, and Au—rapid
current and enhancement of V BD [212]. To further analyse thermal annealing (RTA) at approximately 800 ◦ C–900 ◦ C is
the electric-field distribution, Sun et al [218] simulated the required to realise ohmic contacts with low contact resistance
electric-field distribution between the source and drain area on the AlGaN/GaN heterostructure. Among these metals, the
isolated by ion implantation, as shown in figure 10(d). These bottom metal is usually titanium (Ti) or tantalum (Ta), which
results indicate that the planar geometry of the implantation- can be thermally alloyed to form semi-metallic TiN or TaN and
isolated device yields a better field termination to improve increase the doping concentration of n-GaN under the metal
V BD for the same specific ON-resistance, compared to isol- contacts [244]. The TiN or TaN can penetrate the AlGaN layer
ation using mesa etch technology. Today, ion implantation for by establishing a direct contact to the 2DEG [245]. The second
device isolation remains an important process for commercial- metal is typically aluminium (Al) due to its low work func-
ising GaN device technology. Besides, a method using polar- tion. However, Al has a low melting point (660 ◦ C), resulting
ization isolation has been proposed to effectively reduce the in poor thermal stability of the ohmic electrodes [235]. The
leakage current and improve the breakdown performance of top metal is usually gold (Au), owing to its excellent, stable
the device, it is a promising alternative toward the plasma- conductivity. An isolation metal between the Al and Au—
damage-free isolation for GaN HEMTs [227]. such as nickel (Ni)—should be added to the surface of the
stable Au electrode, inhibiting Au diffusion into the GaN. For
example, Sun et al [238] reported that a Ti/Al/Ti/TiN ohmic
3.2. Ohmic contacts technology
contact obtained by sputtering deposition in 2017, exhibited
Because of the high Schottky barrier height of numerous the best electrical performance after high-temperature anneal-
metals on AlGaN (⩾1 eV), it is essential to reduce the ing at 850 ◦ C/45 s, with an Rc of 1.07 Ω mm. To optimise the
contact resistance between the AlGaN and metal for suffi- electrode structure of ohmic contacts, Fan et al [239] reported
cient current to flow from the 2DEG in the channel to the that Tix Aly , rather than a Ti/Al structure, was deposited on i-
source/drain (S/D) electrodes. For GaN-based HEMTs, low- AlGaN/GaN HEMTs by magnetron sputtering in 2019, and an
resistance ohmic contacts (Rc , Rc ⩽ 1 Ω mm) of GaN-based Rc of <0.1 Ω mm was achieved after annealing at 880 ◦ C/60 s.
HEMTs with good thermal and electrical stability, a smooth For the fabrication of ohmic contacts, many factors—
surface morphology, and good edge acuity are essential to including the temperature, atmosphere, and thickness of
achieving a high transconductance (gm ) and high saturation the metal—can affect its resistance. For example, high-
current [228]. There are two main reasons for this. On the temperature (>800 ◦ C) annealing can degrade GaN-based
one hand, the high ohmic contact resistance can degrade the HEMT performance due to the formation of nitrogen defi-
DC characteristics of the device, such as the saturation cur- ciencies and the oxidation of the bare (Al)GaN surface [246],
rent, knee voltage, and the accumulation of heat [229]. On the which can limit the development of the gate-first process. Con-
other hand, if the electrode surface has a rough metal bound- sequently, the laser annealing process of the ohmic contact
ary and surface morphology, the surface peak electric field region and low-thermal-budget Au-free ohmic contacts have
at the electrode edge caused by the sharp spikes could gen- been applied in power device fabrication. Additionally, high
erate additional leakage current and reduce the breakdown temperatures (800 ◦ C–900 ◦ C) can be produced using a laser.
voltage [230]. Consequently, high-quality ohmic contacts are Tzou et al [247] reported that the implanted dopants in the
helpful in achieving GaN-based HEMTs with high current AlGaN layer under the ohmic contact region could be activ-
densities, high extrinsic gain, and low Joule heating loss ated using a laser annealing process. In this regard, Li et al
to allow high-temperature operation [228]. For conventional [248] developed a selective annealing method to obtain ohmic
ohmic contacts by solid-phase reactions between the metal contact using a focused laser, such that temperature sensitive
and (Al)GaN, Ta/Al/Ni/Au, Ti/Al/Ni/Au, Ti/Al/Ti/Au, Ti/Al/ parts were not thermally affected, as shown in figure 11.
Mo/Au, and Ti/Al/Pt/Au multiple metallisations are com- After calculation and analysis, an Rc of 0.3 Ω mm was
monly used to fabricate low resistance Au-based ohmic con- achieved, the root mean squared roughness being approxim-
tacts for AlGaN/GaN HEMTs [231–235]. However, Au acts ately 12 nm. Using this technology, the wafer was undamaged
as a deep-level contaminant with high diffusivity into the by the laser, and the ohmic contact metal could absorb the
Si [236]. To lower manufacturing costs and diffusion of Au laser energy to gain its annealing effect. Moreover, the rough
on Si, other metals—such as TiN, TiW, W and Cu, which surface of the ohmic contact metal could be demonstrated
have good chemical stability, high electrical conductivity, and using the RTA process under a high-temperature atmosphere
excellent thermal stability—can be used to replace Au. Free- (>800 ◦ C) due to the Al melting temperature being 660 ◦ C,
Au-based ohmic contacts—such as Ti/Al/TiN, Ti/Al/Ti/TiN, resulting in Ni-Al aggregation and TiN deep alloy spikes form-
Tix Aly /TiN, Ti/Al/W, Ti/Al/Ni/TiN, Ti/Al/Ti/TiW, Ti/Al/N- ing along the dislocations. Consequently, this can affect the
i/Cu, Ti/Al/TiN/Cu and Ti/Al/Ti/TiN/Cu—have been applied performance of GaN-based HEMTs [249]. Based on this tech-
to AlGaN/GaN HEMTs [228, 237–243]. Currently, sev- nique, RTA at a LT of ∼600 ◦ C was proposed to prepare ohmic
eral technologies to improve the metal/semiconductor con- contacts by reducing the Schottky barrier height between the
tact characteristics have been proposed, including thermal metal and AlGaN [250]. In 2018, Li et al [250] used Al/Ti/Au
annealing [231], implantation-based [217], and selective stacks to achieve ohmic contacts with an Rc of 1.4 Ω mm at
regrowth [39] techniques. LT (below 600 ◦ C), with the assistance of the ICP dry etching

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Semicond. Sci. Technol. 38 (2023) 063002 Topical Review

the heterointerface-induced 2DEG increases due to the AlN

spacer layer, has a very wide bandgap, and substantially deteri-
orates ohmic contact resistance [256].
Based on these problems, implantation-based techniques
can use the regions under the source/drain electrode Si ion
implantation, followed by high-temperature activation anneal-
ing at 1200 ◦ C–1400 ◦ C, to create heavily doped GaN sur-
face regions, which can enhance electron tunnelling between
the electrode and the heavily doped n-GaN, reducing the low
resistivity of ohmic contacts [255]. Based on this technology,
Nanjo et al [255] used Si ion-implantation doping to fab-
ricate Alx Ga1− x N/GaN HEMTs, using an AlN spacer layer
to achieve a low contact resistance and higher drain cur-
rent. This confirmed that AlN spacer layer insertion could
increase the 2DEG characteristics, and Si ion-implantation
doping could effectively reduce the contact resistance of GaN-
Figure 11. (a) Schematic illustration of micron-scale annealing.
based HEMTs.
SEM (b) and XRD (c) images showing the morphologies of
electrode materials processed by micron-scale annealing in a For high-temperature activation annealing, Recht et al
vacuum. (d) The contact resistance of the processed electrodes [257] demonstrated AlGaN/GaN HEMTs using Si-ion
calculated using the transmission line method. © 2018 IEEE. implantation activated in an MOCVD system, with an Rc
Reprinted, with permission, from [248]. of 0.96 Ω mm and a maximum drain current of 1 A mm−1 .
However, annealing temperatures above 1500 ◦ C are required
to partially activate the Si implanted in the GaN and recover
process. The mechanisms responsible for this ohmic contact to
the crystal-induced damage [258]. Such annealing temperat-
the GaN-based HEMT have been studied. In addition, Zhang
ures can degrade the GaN and cause loss of N from the surface
et al [251] confirmed that field emission is the primary current-
of the device if it is not protected. To reduce these undesirable
transport mechanism using such partially-recessed and over-
effects, protective layers—such as SiO2 [259], AlN [260], or
recessed-AlGaN-barrier structures, while both field emission
Si3 N4 [261]—can be employed. Placidi et al [258] demon-
and thermionic emission contribute to traditional Ti/Al/Ni/Au
strated the relevance of a SiO2 cap layer in yielding consider-
ohmic contacts. Based on this ohmic contact, the ratio of the
ably more uniformity of a relatively low ρc of approximately
thickness between Ti and Al, and the annealing temperature
10−5 Ω cm2 . For AlGaN/AlN/GaN using implantation-based
and duration are major contributors to the resistance of ohmic
techniques, the enhancement of the drain current density of
contacts.
GaN-based HEMTs without an increase in the barrier layer
Zhang et al [252] fabricated an Au-free ohmic contact with
thickness is the result of the successful combination of an AlN
an Rc as low as 0.21 Ω mm, revealing that the formation of AlN
spacer in the structure design, as well as Si ion-implantation
is crucial to realising a low contact resistance with reduced
doping in the process design.
annealing temperatures. The above technology is only applied
to the ohmic contact electrode and does not affect the material
3.2.3. Selective regrowth technique. In addition to for-
characteristics of the GaN-based HEMTs. Consequently, this
eign doping in the AlGaN/GaN HEMTs, regrown ohmic con-
method can be applied to GaN-based HEMTs with gate-first
tacts to enable ultra-low contact resistance in the contact
technology to achieve better electrical performance. Further-
region have been proposed [262]. Recently, an Si-doped n++ -
more, the integration between GaN-based HEMT on Si sub-
GaN structure was selectively grown on the etched source
strates with the gate-first technology and Si CMOS will be
and drain contact regions using MBE to ensure contact with
applied because it is used in all processes above 45 nm in the
the 2DEG channel of the AlGaN/GaN heterojunction, giv-
traditional Si-based CMOS process [253, 254]. The gate-first
ing rise to substantially reduced ohmic contact resistance
technology of GaN-based HEMT in the CMOS processes can
[183]. Compared to conventional ohmic contacts, the regrown
effectively reduce the complexity and cost, and improve the
ohmic contacts exhibited lower resistance and non-alloyed
yield. However, the uniformity of resistance induced by etch-
contacts, which could be ascribed to the regrown n++ -
ing and the reliability of devices still needs to be focused on.
GaN contacts and high 2DEG concentration [262]. Further-
more, the dominant current-transport mechanism between the
3.2.2. Implantation-based technique. Conventional ohmic ohmic metal and regrown n++ GaN was tunnelling or field
contact by RTA can yield a low Rc with smooth sur- emission [263].
face morphology, which is the desired outcome. How- Recently, Xing et al [183] demonstrated that the etched
ever, a thin AlN spacer layer is often inserted into the source and drain contact regions of HEMTs can be backfilled
AlGaN/GaN heterojunction to increase the ns and µN of with 80 nm thick Si-doped n++ GaN by MBE, yielding an Rc
the 2DEG and avoid alloy scattering originating from the of 0.05 Ω mm. Zhou et al [264] adopted regrown ohmic con-
AlGaN layer due to enhanced 2DEG confinement [255]. tact without a contact ledge structure to fabricate InAlN/GaN
The potential barrier between the source/drain electrodes and HEMTs with an Rc of 0.13 Ω mm. Based on the regrown ohmic

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Semicond. Sci. Technol. 38 (2023) 063002 Topical Review

Figure 12. (a) Schematic diagram of AlGaN/GaN HEMTs. (b) Cascode structure. (c) Recessed gate. (d) Fluorine treatment. (e) P-type
(Al)GaN gate.

contact and the low Rsh of the InAlN/GaN heterojunction, an Subsequently, the multi-channel in-plane-gate field-effect
I DS,MAX of 2.8 A mm−1 and RON of 0.47 Ω mm could be transistor combines the highly conductive multi-channel struc-
achieved. This approach could obtain ultra-low resistance non- ture with the proposed in-plane gate geometry [185], enabling
alloyed ohmic contacts using barrier recess and regrowth pro- the efficient control of multiple parallel 2DEG channels, res-
cesses. However, the preparation process is inherently more ulting in a peak transconductance of 2.05 S mm−1 . This offers
complex than alloyed ohmic contact formation and requires advantages in terms of a lower intrinsic gate capacitance com-
a larger thermal budget. Consequently, it can be difficult to pared to tri-gate structures. To achieve enhancement-mode
apply in a larger commercial context. (E-mode) operation, the tri-gate width on the source side can
be tuned to achieve channel depletion, which effectively con-
trols the depletion of the 2DEG. A normally-OFF GaN-based
3.3. Technologies for normally-OFF operation
HEMT was developed by Ma et al [268] and Nela et al [187],
Conventional GaN-based HEMTs are normally-ON (depletion yielding a positive V TH of 0.82 V and 1.8 V, respectively, at
mode, D-mode) devices (figure 12(a)) because of their strong 1 µA mm−1 .
spontaneous and piezoelectric polarisation-induced high- For practical power switching applications, GaN-based
density 2DEG at the AlGaN/GaN heterojunction interface HEMTs are preferred for their normally-OFF (enhanced
[265], which has the negative V TH of GaN-based HEMTs— mode, E-mode) characteristics (V TH > 0 V), which hold inher-
that is, V TH < 0 V, V TH being defined as the gate voltage ent advantages, including low-power consumption, enhanced
(V GS ) at a drain current (I DS ) of 1 µA mm−1 [266]. Since system safety, and simple circuit configurations [270]. Cur-
the production of the first AlGaN/GaN HEMTs, research on rently, several ways of fabricating E-mode GaN-based
this device has always been concerned with the AlGaN/GaN HEMTs have been proposed, including the cascode [271],
heterojunction’s capacity to maintain considerably higher cur- recessed gate [272], fluorine treatment [273], p-type (Al)GaN
rent densities. The structure has also demonstrated excellent gate [11], thin barrier [274], interface charge engineering
thermal and chemical stability, as well as superior 2DEG and [275], and p-type NiO [276] methods. In this section, the
breakdown field characteristics, which could be applied to fab- cascode structure, recessed gate, fluorine treatment, and p-
ricate GaN-based HEMTs for power switching and radio fre- type (Al)GaN gate methods are discussed, as summarised in
quency (RF) applications. To achieve multiple 2DEGs, multi- figures 12(b)–(d).
channel heterostructures stacked using several AlGaN/GaN
layers have been proposed to increase the heterostructure 3.3.1. Cascode structure. The monolithic integrated E-
conductivity [267]. Based on multiple channels heterostruc- mode cascode HEMT can be integrated using an E-mode Si
tures with a higher ns , the conventional top-gate structure MOSFET and a D-mode GaN-based HEMT, which have a
can be quite challenging, resulting in a more negative V TH stable V TH and the gate drive circuit of the Si MOSFET [271].
to achieve the normally-OFF operation and low transconduct- Meanwhile, D-mode GaN-based HEMTs exhibit superior per-
ance values [268]. Consequently, the multi-channel tri-gate formance for power devices, including a low ON-state resist-
GaN-based HEMT was achieved by combining the multi- ance and high blocking voltage [277]. Based on monolithic
channel heterostructure and a tri-gate architecture, allowing integrated E-mode cascode HEMTs, the V TH can easily reach
excellent control over multiple parallel 2DEG channels and more than 3 V, the applied gate voltage being larger than
taking advantage of the high conductivity of multiple 2DEG 20 V. This ensures a margin to guarantee safe device operation
channels [185, 186]. Ma et al [269] successfully fabricated a [278]. At present, monolithic integrated E-mode cascode
multi-channel tri-gate AlGaN/GaN MOS HEMT with a V TH HEMTs have been successfully put to commercial use and are
of −3.6 V, gm,max of 156.6 mS mm−1 , and a higher on/off widely accepted. Moreover, the conventional Si-GaN cascode
ratio over 1010 . These HEMTs used the tri-gate to control the configuration can be achieved using the two-chip co-package
multi-channels, providing enhanced electrostatics and device approach between the Si MOSFET and GaN-based HEMT
performance. with a large interconnection distance [43]. However, the large

17
Semicond. Sci. Technol. 38 (2023) 063002 Topical Review

interconnection distance can cause undesirable ringing during

fast switching, resulting in lower system stability and higher
switching loss, relating to the parasitic inductors of the device
package and printed circuit board layout [279]. To minimise
the parasitics caused by long interconnection distances and
to decrease the interconnection length, the integrated E-mode
cascode HEMT was developed using monolithic heterogen-
eous integration [279], wafer bonding [280], and transfer print-
ing technologies [271].
Ren et al [279] reported that monolithic integrated cascode
Figure 13. Simulated conduction-band diagrams of
GaN-based HEMTs could be fabricated on the same substrate, (a) conventional D-mode AlGaN/GaN HEMTs without CF4 plasma
yielding a V TH of 3.2 V, an I DS of 630 mA mm−1 at a gate bias treatment and (b) E-mode AlGaN/GaN HEMTs with CF4 plasma
of 15 V, and a V BD of 696 V. Xidian University’s Hao et al treatment. © 2006 IEEE. Reprinted, with permission, from [291].
[271] first proposed a transfer printing and self-aligned etch-
ing method to integrate E-mode cascode HEMTs with a V TH of
approximately 2.2 V, substantially decreasing the interconnec- which can lead to low current density and a large ON-
tion distance of E-mode cascode field-effect transisters (FETs) resistance [288, 289]. With the ongoing development of etch-
and improving the large gate voltage swing and uniformity of ing technology and the continuous improvement of equip-
the device. Nowadays, there are many enterprises that have ment etching accuracy, the characteristics of recess-gated
adopted this route to producing GaN-based HEMTs in TO-220 GaN-based HEMTs, such as reliability and uniformity, should
packaging—including Transphorm Inc. and Xinguan Tech- improve.
nology Co., Ltd. Nevertheless, although this technology is
simple, the bonding packaging between chips inevitably intro-
3.3.3. Fluorine treatment. Fluorine (F) ions can be
duces large parasitic inductance, restricting the switching rate
implanted into the region of the AlGaN barrier layer under the
of E-mode cascode FETs.
gate using CF4 plasma in a plasma system, referred to as fluor-
ine plasma implantation. Consequently, GaN-based HEMTs
3.3.2. Recessed gate. The gate recess scheme depletes with a positive V TH (⩾0 V) have been developed using fluor-
the 2DEG under the gate by thinning the barrier layer to ine treatment, the strong electronegativity of the fluorine ions
weaken its polarisation effect, realising normally-OFF GaN- forming a negative charge after implantation into the AlGaN
based HEMTs [281]. The recess-gated GaN-based HEMT barrier, and effectively depleting the electrons in the channel
device can be considered to be a promising solution owing [290]. This technology can be useful in modulating the energy
to its large V TH , high ON/OFF current ratio, and larger tol- band in the AlGaN/GaN heterostructure and effectively rais-
erance to the gate swing voltage [282]. In 2006, Saito et al ing the potential in the AlGaN barrier and the 2DEG channel,
[167] fabricated a recess-gated GaN-based HEMT device with depleting the 2DEG under the gate in the region [291]. The
a V TH of 0.14 V and a GaN-based HEMT without the recess- conduction-band profiles of AlGaN/GaN HEMTs structures
gated structure with a V TH of approximately −4 V. In 2014, with and without fluorine ions incorporated in the AlGaN
Hao et al [272] used the self-terminating gate recess process layer were simulated, as shown in figures 13(a) and (b).
to fabricate normally-OFF recess-gated AlGaN/GaN HEMTs, In 2006, Chen et al [291] obtained a V TH controllable
which exhibited a V TH as high as 5 V and an excellent ON/OFF enhancement-mode GaN-based HEMT for the first time using
current ratio of ∼1010 . The proposed gate recess scheme was a fluoride-based plasma treatment, demonstrating that the
simple, reducing the fabrication costs. However, the conven- VTH of AlGaN/GaN HEMTs shifted from −4 V to 0.9 V.
tional gate recess process suffers from uncontrollable etch Subsequently, the diffusion mechanism [292], defect forma-
depth and undesirable etching damage associated with plasma tion and annealing behaviours [290], thermal stability [293],
dry etching [283]. This results in V TH inhomogeneity and poor and reliability [294] of fluorine-implanted HEMTs have been
gate reliability for recess-gated GaN-based HEMTs, restrict- widely studied. Yang et al [295] developed enhancement-
ing its suitability for large-scale commercial application. mode GaN-based HEMTs using 10 keV fluorine ion implant-
To address these problems, gate dielectrics such as SiO2 ation with a V TH as high as +3.3 V and a high ON/OFF cur-
[284], SiNx [281], and Al2 O3 [270, 272], a plasma surface rent ratio of 109 . The SiNx layer was deposited on AlGaN as
treatment technique using O2 and N2 O [285, 286], and a digital a gate dielectric and energy-absorbing layer, slowing down
etching process [287] were proposed to prepare a recess-gated the high energy (10 keV) F− to reduce the implantation dam-
GaN-based HEMT with a low gate-leakage current. However, age. To analyse the diffusion mechanism, Wang et al [292]
stable and uniform recess-gated GaN-based HEMT perform- showed that the diffusion of fluorine ions in GaN could be
ance is still a restrictive factor in its industrialisation. At the assisted by implantation-induced vacancies, especially dif-
same time, the fully recessed barrier with GaN-based HEMTs fusing to vacancy-rich regions. However, the reliability of F
suffers from serious dielectric interface scattering, degrad- ion implantation under high gate electric fields remains to be
ing channel mobility and increasing the channel resistance, examined further.

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Semicond. Sci. Technol. 38 (2023) 063002 Topical Review

3.3.4. P-type (Al)GaN gate. The p-(Al)GaN gate HEMT time-consuming or included BCl3 plasma-induced damage. In
forms a p-type GaN gate on top of a AlGaN/GaN HEMT addition to these solutions, an AlN etching stop layer could be
wafer through the process of dry etching the region under gate, included instead of the Al component in AlGaN, it being oxid-
such that the 2DEG channel is depleted at a zero gate voltage, ised to Al2 O3 . Lükens et al [305] reported an AlN etching stop
conducting only at a sufficient positive gate bias [189]. In layer combined with a self-terminated digital etching tech-
2007, Uemoto et al [296] successfully fabricated a normally- nique, which was used to obtain uniform p-GaN gate HEMTs
OFF AlGaN/GaN HEMT using hole injection from the p- with a V TH of 1.7 V. The AlN etching stop layer effectively
AlGaN to the AlGaN/GaN heterojunction for the first time, increased the etching selectivity, avoiding the influence of
demonstrating a positive V TH of +1 V for the device. Among oxygen on the AlGaN barrier layer. This etching selectivity
various normally-OFF HEMT technologies, the p-GaN gate technique could have an important role to play in the fabrica-
HEMT solution (p-GaN E-HEMTs) has been commercialised, tion of E-mode GaN-based HEMTs owing to its controllabil-
as it can preserve the 2DEG channel without downgrading the ity and reproducibility. However, high stability etching equip-
channel mobility [297], and has excellent features including ment is still required in practice.
its low cost, device reliability, and market availability [298]. To reduce damage induced by the complex etching process
Today, commercial products have been launched based on of p-GaN at the access regions, the hydrogen plasma treat-
this technology, represented by companies such as Navitas, ment, Mg thermal diffusion, and selective regrowth have been
Power Integrations, and EPC (United States), Innosecience proposed to fabricate the p-GaN gate [192, 299, 302, 306–
(China), Panasonic (Japan) and GaN System (Canada). How- 308]. In 2016, Hao et al [309] reported normally-OFF p-
ever, there are two major challenges in fabricating p-GaN gate GaN/AlGaN/GaN HEMTs that were fabricated by introducing
HEMTs [192]. Firstly, the etching depth uniformity and pre- the hydrogen plasma treatment instead of using etching tech-
cision of non-gated active regions is the single major chal- nology, which yielded a normally-OFF operation with a V TH
lenge for p-GaN gate HEMTs, as it can lead to a decline of 1.75 V. In this process, the Mg-acceptors in the p-GaN
in the device output characteristics or even device failure region outside the gate were successfully passivated using the
[299]. Secondly, another challenge is the meticulously optim- hole compensation mechanism. Meanwhile, the 2DEG was
ised plasma-induced damage by chlorine-based dry etching, released in the 2DEG channel and a HR area was formed. In
which can cause unreliable and degraded device character- 2020, Li et al [307] successfully fabricated p-(Al)GaN gate
istics, including large sub-threshold swings and a large V TH GaN-based HEMTs by Mg thermal diffusion after the etch-
hysteresis [300]. To improve the uniformity and precision ing treatment, achieving a normally-OFF GaN-based HEMT
of the etching depth, a selective etching technique employs with a V TH of 1.4 V, and a low gate leakage current of
self-terminated digital etching of p-GaN over AlGaN using 2 × 107 mA mm−1 at a zero gate voltage for the first time. This
oxygen-contained chlorine-based gas, which is required to method effectively avoided extensive damage of the access
stop smoothly at the surface of the AlGaN barrier layer based region and enabled careful consideration of the etching accur-
on a high selectivity ratio, enhanced controllability, and low acy. However, Mg can be difficult to dope to high Al compon-
etching damage, whereas the p-GaN outside of the gate area is ents of the barrier layer due to the similar properties of Mg and
removed by dry etching [301]. For this technology, ICP etch- Al. Furthermore, Mg-doping diffusion can cause lateral rather
ing parameters such as the flow rate of O2 , RF bias power, than downward diffusion. Consequently, novel epitaxial struc-
ICP power, and chamber pressure can be employed to adjust tures and process technologies must be developed to achieve
the high selectivity etching ratio of p-GaN and AlGaN. Based p-GaN gate HEMT with high V TH .
on the high selectivity etching ratio of p-GaN over AlGaN, The above GaN-based HEMTs device adopted a tradi-
the normally-OFF AlGaN/GaN HEMTs with a p-GaN gate tional AlGaN/GaN heterojunction, and its thin AlGaN barrier
were fabricated. Taube et al [302] and Iwata et al [303] repor- layer was generally less than 20 nm, achieving a relatively
ted a high etching rate ratio of GaN to AlGaN by chan- high V TH , at the price of a static ON-resistance and break-
ging the O2 flow rate in oxygen-contained chlorine-based down voltage [305, 310]. Consequently, a thick AlGaN bar-
gas plasma, which achieved good etch depth control for p- rier heterostructure was proposed to achieve E-mode p-GaN-
GaN-gated HEMTs. The realisation of this technology bene- based HEMTs with lower RON and transconductance [311].
fits from the formation of high bonding energy Al-O bonds Moreover, normally-OFF GaN-based HEMTs with a p-GaN
due to the exposed AlGaN surface layer (approximately 6– gate have been achieved through p-GaN regrowth techniques.
7 nm thick), which is oxidised to Al2 O3 by the O2 plasma. Recently, numerous efforts have been made to develop this
Al2 O3 is a stable interfacial oxide layer that cannot be easily p-GaN regrowth technique. Zhong et al [312] fabricated a
etched using dry etching techniques and contributes to the self- normally-OFF HEMT using a regrown p-GaN gate to obtain
termination. However, this technology also causes oxidation a positive V TH of +1.7 V at an I DS of 10 µA mm−1 , and a
of the AlGaN surface (to Al2 O3 ) and reduces the polarisation high I on /I off ratio of 5 × 1010 . Normally-OFF HEMTs with
effect between AlGaN and GaN. Consequently, several etch- regrown p-GaN gates boast improved stability, reproducibil-
ing technologies alternately use the dry and wet etching steps ity, and controllability. However, the etching damage and non-
[304], and the O2 oxidation/BCl3 cyclical etching steps [305] uniformity caused during the process of dry recessing can res-
have been proposed. However, these methods have been either ult in low reliability and V TH instability. To solve this problem,

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Semicond. Sci. Technol. 38 (2023) 063002 Topical Review

Zhong et al [299] used thermal cleaning by MOCVD prior Table 3. Physical properties of dielectric materials.
to the p-GaN regrowth to effectively reduce residual etching Relative Band gap
damage of the etched surface, achieving E-mode GaN-based Materials permittivity (eV) References
HEMTs with a high I on /I off ratio of 4 × 1010 and a positive
V TH of +1.7 V at an IDS of 10 µA mm−1 . Compared with SiO2 3.9 8.9 [368, 370]
GaN-based HEMTs without thermal cleaning, the GaN-based SiNx 7 5.1 [289]
HEMTs with thermal cleaning by MOCVD perform consid- Al2 O3 9 8.7 [282]
AlN 8.5 6.2 [345]
erably better. With further improvement in the gate reliability
HfO2 20 5.8 [341, 371]
and regrowth technique, normally-OFF HEMTs with regrown ZrO2 25 5.8 [349]
p-GaN gates hold great promise for practical application. Ta2 O5 20–50 4 [372]
E-mode GaN-based HEMTs can be applied to commercial La2 O3 27 4.3 [373]
applications including integrated E-mode cascode FETs and p- TiO2 55 3.5 [352]
GaN gate HEMTs. With continuous technology development, LaLuO3 28 5.3 [354]
p-GaN gate HEMTs could emerge as the preferred single-chip
E-mode GaN power transistors, because integrated E-mode
cascode FETs are limited to Si MOSFET devices. Based on
on Schottky barrier height [330], gate metal resistivity
the above techniques, the V TH of p-GaN-based HEMTs can
[331], reliability [332], and transport mechanisms [333]. For
reach 1.5 V, but should generally not exceed 2 V. The p-GaN-
example, Ao et al [331] prepared a Cu gate AlGaN/GaN
based HEMTs with low threshold and gate voltages are incom-
HEMT with a low gate-leakage current of 3.5 × 10−8 A, which
patible with the driving circuits of traditional Si-based MOS-
was considerably lower than that of a Ni/Au-gate device. By
FETs. Consequently, novel gate driving circuitry is required.
optimising the gate Schottky contact, a decreased gate-leakage
current as well as an increased drain breakdown voltage could
3.4. Gate contact engineering be successfully obtained without degrading the transistor’s
transconductance. Simultaneously, the gate contact of GaN
For GaN-based HEMTs in power conversion applications,
HEMTs face the reliability and physical-of-failure degradation
the 2DEG channel transport is modulated by a Schottky gate
under high-thermal bias test [334], high-temperature gate bias
[313]. The Schottky gate usually employs a Schottky metal
stress-induced instability [335, 336], and long-term reliability
possessing a high work function, strong adhesion, and thermal
under electric stress bias [337, 338]. Many studies [339, 340]
stability, such as Pt (5.65 eV) [314], Ni (5.15 eV) [315], Mo
on gate reliability have been reported, and the underlying
(4.6 eV) [316], Ir (5.46 eV) [316], W (4.5 eV) [317], TiN
physical mechanisms have been clarified. In this section, the
(4.82) [318], Cu (4.65 eV) [319], Pd (5.12 eV) [320] or Au
MIS-HEMT and p-GaN-based HEMT structures are system-
(5.1 eV) [321]. The Schottky metal is effective in improving
atically studied here.
the Schottky barrier height between III-nitride layers and the
gate contact metal, determining the electrical characteristics
including the current collapse and leakage current [316, 322]. 3.4.1. MIS-HEMT structure. It is beneficial to introduce
The gate-leakage current in its ON/OFF state—including the a gate insulator layer between the gate metal and AlGaN
forward and reverse gate-leakage current—is an important barrier layer to overcome the leakage current and sur-
parameter for GaN-based HEMTs [323]. The forward gate- face problems of AlGaN/GaN HEMTs, comprising MIS-
leakage current limits the gate voltage swing and causes drive HEMTs [341, 342]. Currently, various dielectric materi-
losses, while the reverse can lead to OFF-state power con- als have been deposited on the surface of the AlGaN/GaN
sumption and limit the breakdown voltage. Furthermore, a heterojunction—including SiO2 [343], SiNx [344], AlN
higher leakage current has a stronger self-heating effect and [345], Al2 O3 [346], HfO2 [347, 348], ZrO2 [349], Gd2 O3
higher device temperature, leading to potential power losses [350], La2 O3 [351], TiO2 [352], LaHfOx [353] and LaLuO3
in the ON-state, restricting the efficiency of power conversion [354]. These dielectric deposition methods include in situ
[324]. More importantly, switching losses incurred by the MOCVD [355], plasma-enhanced chemical vapour depos-
charging and discharging cycles of the gate is related to the ition (PECVD) [356], low-pressure chemical vapour depos-
measured gate-current because the gate-charge is determined ition (LPCVD) [357], and atomic layer deposition (ALD)
by the time integral of the measured gate-current [325, 326]. [358], amongst others. The physical properties of the dielec-
Thus far, Fowler–Nordheim tunnelling, Poole–Frenkel emis- tric materials are listed in table 3. However, high-density
sion, trap-assisted tunnelling, or their combination through trap states (1010 –1014 cm−2 eV−1 ) or large volumes of inter-
dislocations have been considered to be the main current- face charges (∼1013 cm−2 ) induced by structural damage
transport mechanisms [327, 328]. [357, 359], oxidation-induced defects, or dangling bonds exis-
Among the Schottky metals, Ni/Au systems with high ted in the oxide dielectric/III-N interface [360], leading to the
metal work functions and good adhesion are now widely used degradation of the 2DEG density or V TH shift [361]. Some
as Schottky contacts to fabricate AlGaN/GaN HEMTs [329]. study showed that V TH shift may be related to gate bias elec-
However, the gate-leakage current of a Ni/Au-gate device trical stress and bias stress time [362, 363]. Under the elec-
still requires improvement. Consequently, most reports of trical stress, the long-term reliability of the gate dielectric
Schottky contact for GaN-based HEMTs have been focused could get challenging [364, 365]. To estimate its lifetime, both

20
Semicond. Sci. Technol. 38 (2023) 063002 Topical Review

electric-field-accelerated and temperature-accelerated time- I on /I off ratio of 9 × 108 . Either ZrO2 or HfO2 as a gate
dependent dielectric breakdown (TDDB) tests were performed dielectric layer were effective in reducing the gate-leakage
on the MIS-HEMTs [366, 367]. Next, the dielectric materials current by suppressing the gm reduction [386, 387]. Com-
and related reliability of MIS HEMTs will be analysed and pared to the impact induced by nitride-based or oxide-based
summarized. dielectrics, nitride-based dielectric materials hold consider-
Among these insulators in practical use, SiO2 and SiNx able advantages, such as the suppression of the interface trap
deposited by plasma-enhanced-chemical vapour deposition density due to oxide-based dielectric materials introducing
(CVD) as a dielectric layer are attractive, as they have the unfavourable Ga-O bonds which could cause current collapse
largest band gap and mature process technology [357, 368], [341]. For example, Zhu et al [361] reported AlGaN/GaN
which can be useful in reducing the number of Ga bonds at HEMTs with AlN dielectrics deposited by ALD with a higher-
the interface by forming Ga-O bonds, considerably suppress- peak transconductance of 289 mS mm−1 and a smaller VTH
ing the interface trap density of (Al)GaN [369]. shift of 0.8 V, attributed to plasma-enhanced atomic layer
Kirkpatrick et al [374] deposited a SiO2 layer as a dielec- deposition-grown AlN considerably reducing the interface
tric layer for MOS HEMTs, leading to a three orders of mag- charges at the dielectric/III-N interface (from 1.2 × 1013 to
nitude reduction in gate-leakage current compared to conven- 8 × 1012 cm−2 eV−1 for interface traps, and from 1.01 × 1013
tional Schottky-gate HEMTs. Compared with the passivation to 3.1 × 1011 cm−2 for fixed charges). This demonstrated that
mechanism of SiO2 , N atoms of SiNx combined with Ga atoms the high-k dielectric/GaN interface had far fewer fixed charges
on the AlGaN surface to form Ga-N bonds, demonstrating that as well as trap states than the low-k dielectric/GaN interface,
the VN -related surface defects were effectively suppressed, and indicating the excellence of the dielectric/III-N interface using
that the trap states at AlGaN surfaces during high-temperature the ALD-grown high-k dielectric.
annealing were reduced [375]. Dutta et al [376] used an ICP- Moreover, previous reports have shown that the increase
CVD technique to deposit the SiNx layer as a gate dielec- in the 2DEG density was caused by the enhanced piezo-
tric for MIS-HEMTs at a LT (70 ◦ C). The device exhibited electric polarisation field—that is, the strain induced by dif-
a small capacitance-voltage hysteresis (∼68 mV) with a gate ferent lattice distances—due to the dielectric layers depos-
swing of −10 to +5 V, and low I DS –V GS hysteresis character- ited on the AlGaN surface—such as SiO2 , SiNx , and HfO2
istics. To obtain stable GaN-based HEMTs with a low inter- [343, 344, 347, 348]. This is known as the strain effect.
face state density at the dielectric/AlGaN interface, several For example, Jeon et al [388] investigated the relationship
technologies have been developed, including in-situ grown between the 2DEG density and thickness of the Si3 N4 pas-
Si3 N4 [377], surface treatment [346], LPCVD-deposited SiNx sivation layer deposited by PECVD. Consequently, the stress-
[357], post-deposition annealing [378], and the use of a plasma induced charge density of the GaN-based HEMTs increased
oxide interlayer [359]. Moreover, the dielectrics have been with increasing Si3 N4 thickness, leading to the maximum
achieved by surface treatments using thermal oxidation/nitrid- drain current increasing from 769 to 858 mA mm−1 . The res-
ation, which could produce Al2 O3 or AlN on the surface of the ults showed that a dielectric layer could be deposited on the
2DEG supplying barrier [379, 380]. Sun et al [377] demon- surface of AlGaN to enhance the output characteristic of GaN-
strated the residual shift of V TH after reset is much smaller based HEMTs.
in MIS-HEMTs with in-situ Si3 N4 cap, which is consistent
with the lower density of trap states deduced from the C–V 3.4.2. P-GaN-based HEMT structure. For the gate struc-
measurement compared with the LPCVD deposited SiNx . Fur- ture of p-GaN-based HEMTs, the metal/p-GaN/AlGaN/GaN
thermore, the 10 years lifetime prediction of the 63% fail- layer consists of a metal/p-GaN junction and a hetero p-i-n
ure level using combined TDDB models over a wide range junction (the i-region consisting of undoped AlGaN), which
of field for the MIS-HEMTs with and without in-situ Si3 N4 is very different from that of a AlGaN/GaN- or MIS-HEMT
cap is 16.5 and 17.7 V, respectively. These were also reported [323, 389, 390]. Presently, two types of gate contacts between
by other researchers [355, 367]. Simultaneously, other ALD- the gate metal and p-GaN layer can be differentiated by their
deposited novel dielectric layers with large bandgaps, relat- electrical properties—namely the Ohmic- and Schottky-type
ively high dielectric constants, and a high breakdown field gate contacts [391, 392]. The Schottky-gate contact features
strength have been fabricated based on the fact that a lar- a lower gate-leakage current, larger gate swing, and sizeable
ger dielectric constant could translate to more efficient gate gate voltage, given that the metal/p-GaN Schottky junction
modulation [381–383]. is reverse biased at a positive V GS . Compared to a Schottky-
Currently, MIS-HEMTs have made great progress in redu- type gate, an Ohmic-type gate contact formed by the p-GaN
cing gate-leakage current. For example, Zhang et al [384] pro- layer and gate metal by post-annealing process at 550 ◦ C in
posed a novel gate dielectric and passivation technique for air has been achieved [393, 394]. For an Ohmic-type contact,
AlN/GaN MIS-HEMTs, exhibiting an enhanced high I on /I off the forward gate voltage is limited by the built-in potential
ratio of 107 , the reduction of gate leakage by five orders of of the p-i-n junction, and it has a large gate current. How-
magnitude at a bias voltage of 5 V, and suppressed current- ever, p-GaN gate HEMTs with an Ohmic-type gate contact
collapse degradation. Joseph et al [385] reported that recess- have shown impressive stability and reliability [395, 396].
gated GaN-based HEMTs with an Al2 O3 layer deposited as Furthermore, they are current-driven devices defined as gate
a dielectric layer, achieved a breakdown voltage of 825 V, injection transistors (GITs), as shown in figure 14(a) [397].
a lower leakage current of 10−8 mA mm−1 , and a high The p-GaN gate HEMTs face the most serious problems

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Semicond. Sci. Technol. 38 (2023) 063002 Topical Review

Figure 14. Schematic cross-sections of the (a) GIT and (b) HD-GIT.

during high-voltage switching operation (>600 V), the so-

called current-collapse phenomena, which degrades RDS-ON
and I DS [397].
Recently, a hybrid-drain-embedded GIT (HD-GIT) was Figure 15. The dynamic ON-state resistance RON (t = 3 µs) of the
proposed to suppress the current collapse for a high drain HD-GIT and GIT as a function of the applied voltage V DD . Inset
voltage, as shown in figure 14(b). The HD-GIT has an addi- shows the circuit used in the switching measurement. Reprinted
tional p-GaN region between the gate and the drain, electric- from [399], with the permission of AIP Publishing.
ally connected to the drain, such that holes can be injected to
compensate for the charge of the trapped electrons in the OFF-
state [398]. Tanaka et al [399] compared the dynamic RDS-ON shift results from the trapped holes and the positive V TH shift
of the conventional GIT and HD-GIT, which showed that the gets induced by the holes emission and electrons trapping.
dynamic RDS-ON of the HD-GIT did not increase up to 800 V, The comprehensive research on threshold voltage instability
while a sudden increase of RDS-ON at 550 V was evident in is of great significance for improving the reliability of p-GaN
the GIT, as shown in figure 15. This result demonstrates that HEMTs and promoting its commercial application in future.
the introduction of an additional p-GaN region in the HD-GIT
helps inject holes in the OFF-state, effectively suppressing
3.5. Passivation and FP engineering
the current collapse. Recently, the gate stability characteristics
and physical mechanisms for both Schottky- and Ohmic-type Due to a large number of surface states on the surface of the
gated devices caused widespread concern. Zeng et al [395] AlGaN/GaN heterojunction, without proper compensation the
analysed the impact of these two gate contacts on the gate sta- charged surface states formed between the gate and the drain
bility performance of p-GaN gate AlGaN/GaN HEMTs, and electrodes by electrons injected from the gate to the surface
found that gate instability of the Schottky-gate devices was states can function as a virtual gate (figure 16(a)), leading
evident under a positive gate bias and elevated temperatures, to depletion of the channel electrons and an increase in the
whereas the opposite was true for the Ohmic-type contact gate. leakage current [344]. More seriously, the trapped electrons
However, the p-GaN layer hole injection could then caused by the virtual gate effect increase dramatically under
cause unfavourable gate instability problems, such as V TH high-voltage stress, thereby leading to part or full depletion
shift [188]. To date, several potential mechanisms regard- of the 2DEG channel electrons [403, 404]. The reduced I DS
ing forward-gate-bias induced V TH instability have been pro- represents an increase in the dynamic RON —known as current
posed, such as charges (electrons and holes), storage/emission collapse or RON dispersion, respectively—and has emerged as
within the floating p-GaN layer [324, 400], and the ionisation a critical issue in high-voltage devices [405]. To suppress cur-
of acceptor-like traps in the p-GaN depletion region [401]. rent collapse, the introduction of surface passivation combined
Recently, many studies have investigated the V TH instabil- with a FP has been proposed to reduce the surface state density
ity of the p-GaN HEMTs such as positive bias temperat- and modulate distribution of the electric field at the drain edge
ure instability [335], negative bias temperature instability of the gate (figure 16(b)) [406–408].
[334], instability induced by OFF-state drain stress [362], The passivation can reduce the interface state dens-
stress-induced gate current degradation [336], and instability ity between the dielectrics and AlGaN as discussed in
induced high-temperature reverse gate bias [402]. Yang et al section 3.4.1, thus decreasing the leakage current and improv-
[334] examined the threshold voltage shift under negative- ing gate reliability. Similarly, the passivation also provides
bias temperature instability stress conditions, revealing the electrical isolation between the electrodes and air. To fur-
physical mechanism of threshold voltage shift under different ther suppress the current collapse, moderation of the surface
stress conditions. Sayadi et al [400] showed that the balance electric field by the FP engineering of HEMTs has also been
between the supply and emission of holes in the p-GaN layer developed. Presently, the FP can be divided into the gate field
causes V TH shift. Wu et al [402] reported the time-resolved plate (GFP) [409], source field plate (SFP) [410], and drain
threshold voltage instability of p-GaN gate HEMT under the field plate [411]. Recently, Hasan et al [406] compared the
high-temperature gate bias, showing that the negative V TH dynamic ON-resistance and breakdown voltage of GaN-based

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Semicond. Sci. Technol. 38 (2023) 063002 Topical Review

the 2DEG channel by capacitive action [420]. The optimum

electric-field peak decreases with increasing thickness and
permittivity, on account of the same capacitive action and
the fact that a stronger FP influence is required to manage
a higher 2DEG concentration. By depositing high-k dielec-
trics by ALD, the surface traps on the GaN can be passiv-
ated, and the electric-field intensity at the drain edge of the
gate in GaN-based HEMTs can be reduced [416]. However,
Figure 16. Schematic diagrams of the ON-state device operation
considering the plasma damage or failure to eliminate inter-
for AlGaN/GaN HEMTs (a) without a field plate (FP) and (b) with a face states between the GaN and the passivation layer depos-
FP. © 2013 IEEE. Reprinted, with permission, from [406]. ited by PECVD, and the higher production costs required for
depositing a passivation layer by ALD, multilayer dielectrics
such as HfO2 /SiNx [421], AlN/SiNx [266], ZrO2 /SiNx [416],
HEMTs with and without a GFP. GaN-based HEMTs with and AlN/Al2 O3 [266] have been proposed to overcome this.
a GFP evidently improved the RON and V BD . Onodera et al The high-k/low-k passivation layer plus the FP structure can
[405] showed that the SFP structure was effective in improving achieve a weaker electric-field distribution, effectively redu-
the breakdown voltage. Yu et al [412] fabricated AlGaN/GaN cing the direct tunnelling effect. Moreover, Cai et al [416] fab-
double-gate HEMTs with a SFP and GFP for the first time ricated three samples using PECVD-SiNx , Al2 O3 /SiNx , and
to demonstrate that the GFP improved dynamic performance ZrO2 /SiNx passivation, obtaining a VBD of 885, 1092, and
more than the SFP owing to the combined effects of positively- 1207 V, respectively, extracted at drain leakage current of
induced extra electrons and the negative-voltage-modulated 10 µA mm−1 , as shown in figure 17(c). Combined with low-
peak electric field at the drain-side gate edge. k dielectrics, the multilayer dielectrics show a remarkable
However, the effectiveness of the FP in E-field engineer- improvement in the breakdown and dynamic characteristics
ing is highly dependent on passivation and FP engineering. compared with the single dielectrics (figure 17(d)).
Chen et al [413] developed a physics-based analytical model Second, the breakdown voltage is proportional to the FP
to analyse the FP parameters of AlGaN/GaN HEMTs, such as length within a certain range, because the electric field at the
the FP length, passivation thickness, and dielectric constant of drain edge of the gate is reduced [422]. With the length of
the passivation material, showing that the optimal E-field dis- the FP > 0, as shown in figure 18(a), an electric-field peak
tribution, the minimum effective FP length, and the optimum is formed at the edge of the FP near the drain electrode, effect-
passivation thickness should be favoured for minimising the ively reducing the electric-field peak on both sides of the gate,
over-design of FPs for AlGaN/GaN HEMTs. especially at the edge near the drain electrode, so as to improve
Next, we can summarise the influence of FP engineering the breakdown voltage of the device [413, 423].
on device performance [414, 415]. In FP engineering of GaN- However, when the length of the FP reaches a certain
based HEMTs, the passivation thickness and constant under length, the electric-field peak does not decrease with the
the FP, and the length, shape, and structure of the FP are increasing length of the FP [405]. Furthermore, the gate-drain
designed to reduce the gate-edge peak electric field, which can capacitance and switching loos are increased with the GFP
lead to an improvement of the breakdown voltage and suppres- length [424]. Karmalkar et al [422] revealed the V BD does not
sion of an increase in RON . increase with the increasing FP length beyond a certain point,
First, the constant, thickness, and structure of the pas- as the field distribution along the 2DEG channel decays bey-
sivation layer under the FP can be considered to reduce ond the FP edge. Consequently, an optimum value of LFP to
the electric-field peak, demonstrating that the electric-field obtain the high breakdown voltage must exist.
drop weakens from the drain to the gate [414, 416, 417]. Third, the FP shapes comprise primarily parallel FPs and
Based on Gauss’s law, the electric field across a dielec- slant FPs [425]. In one study, a parallel FP was deposited
tric is inversely proportional to its relative permittivity at a above a dielectric film in a specific area [407]. However, a slant
constant voltage [418]. The results showed that the passiv- FP has a transition angle between the gate and the FP by means
ation layer with a higher constant (figure 17(a)) could fur- of precise control over the thickness and angle of the sloped
ther reduce the electric-field peak at the drain edge of the oxide in the vertical direction (less than 90◦ ), so controlling the
gate, making the electric-field profiles more uniform [413]. slant FPs (figure 18(b)) can be challenging [426, 427]. Com-
Consequently, the improvement of the gate hard breakdown pared to the parallel FP, the slant FP spreads the electric field
voltage becomes more significant. Increasing the physical more effectively, improving the V BD of lateral power devices.
thickness of the dielectric layer can reduce the direct tunnel- Slant FPs were introduced in AlGaN/GaN HEMTs to achieve a
ling effect and prevent a strong electric field at the drain edge breakdown voltage of 1900 V at I DS of 1 mA mm−1 , as shown
of the FP, leading to an increase in the drain lag and current in figures 18(c) and (d) [428]. Coffie et al [429] designed step
collapse [419]. Consequently, there is an optimum thickness and slant FPs, proving that the slant FPs could be useful in the
for the passivation layer to minimise the buffer-related drain management of electric fields.
lag and current collapse in AlGaN/GaN HEMTs (figure 17(b)). The peak electric field in each insulator decreases with the
The optimum V BD increases with increasing thickness and transition angle, which can improve the breakdown voltage of
permittivity because the FP influences the electric field along GaN-based HEMTs. In addition to the vertical slant FP, the

23
Semicond. Sci. Technol. 38 (2023) 063002 Topical Review

Figure 17. (a) Electric-field profiles along the AlGaN/GaN interface for a field-plate (FP) length of 1 µm. (b) Simulated and analytical
optimum passivation thickness topt and optimum gate and lateral FP E-field Emin,peak at the heterointerface with different passivation
materials at V DS = 200 V and V GS = 0 V. (a) © 2019 IEEE. Reprinted, with permission, from [413]. Copyright 2019 Institute of Electrical
and Electronics Engineers Inc. (c) Off-state breakdown characteristics of the fabricated AlGaN/GaN MIS-HEMTs with PECVD-SiNx
passivation (black lines), Al2 O3 /SiNx passivation (red lines), or ZrO2 /SiNx passivation (blue lines). (Inset figure: the OFF-state breakdown
characteristics of 11 representative MIS-HEMTs for each sample). (d) Benchmarking of V BD versus specific ON-resistance (RON,SP ) for
devices in this work and state-of-the-art gate recess free GaN-based MIS-HEMTs. (b)–(d) Reproduced from [416]. CC BY 4.0.

slanted tri-gate can be easily and accurately engineered using a new electric-field peak at the terminal of the FP. In 2010,
a lateral approach, by lithographically varying the width of Saito et al [431] compared the influence of a single source
the tri-gate nanowires. Ma et al [427] reported that GaN-based FP and dual FP using a combination of gate and source FPs
HEMTs using the slanted tri-gate achieved a V BD of ∼1350 V on the electric-field peaks, as shown in figure 18(e). From
at 1 µA mm−1 with an LGD as small as 10 µm. these results, we can conclude that the dual-FP structure can
Finally, FP structures—including the single-FP, dual-FP, reduce electric-field peaks and improve the uniformity of the
and multi-FP structures—have been used to improve the uni- electric-field distribution. The current collapse is effectively
formity of the electric-field distribution [408, 423]. These suppressed.
evolved structures may increase the capacitance resulting in Thus far, the combined configuration of the GFP and SFP
the deterioration of the switching performance of these devices has shown the best results in terms of dynamic RDS-ON . The
[430]. However, some reports showed total losses induced multistep FP structure composed of multiple SFPs and GFPs,
by the single-FP device were more than that for the dual- can reduce the size of the peaks by spreading the electric-field
FP device [326]. In this structure, the dual FP combines the concentration. Although the multistep FP structure is effective
gate FP and the source FP, effectively overcoming the adverse for suppressing the current collapse phenomena, the switch-
effects of an increased gate-drain capacitance and modulating ing speed is degraded by the gate-FP electrode because the

24
Semicond. Sci. Technol. 38 (2023) 063002 Topical Review

Figure 18. (a) Simulated and analytical results of lateral E-field distribution using different LFP values of 0.5, 2, and 2.5 µm at V DS = 200 V
and V GS = 0 V, the passivation material is SiNx and T pass is 0.2 µm. © 2019 IEEE. Reprinted, with permission, from [413]. (b) Schematics
showing the slant-field-plate gates with single integrated self-aligned FPs made using Process-b. (c) V BD versus Lgd studied on devices with
or without Fluorinert. After passivation, the standard-gated devices have a similar breakdown voltage with or without Fluorinert. (d)
V BD = 1900 V is measured on a device with Lgd = 20 µm. (Lsg = 1 µm, Lg = 1 µm, W g = 200 µm). (b)–(d) © 2006 IEEE. Reprinted, with
permission, from [428]. (e) Cross-sectional structure of the fabricated GaN HEMTs. © 2006 IEEE. Reprinted, with permission, from [431].

gate charge increases with the gate electrode area [411, 432]. AlN/AlGaN buffer structure, and crack-free GaN films
Thus, the FP structure must be designed considering the grown on 300 mm Si substrates with very smooth sur-
total device performance, which includes the on-resistance faces have also been successfully achieved. Furthermore,
and switching speed. The factors affecting passivation and GaN on 200 mm Si with a high-resistance buffer structure
FP engineering have been analysed and summarised, includ- using C-doping or Fe-doping techniques has enabled a ver-
ing the thickness, dielectric constant, and structure of pas- tical breakdown voltage of up to 1200 V, equivalent to a
sivation materials, as well as the length, shape, and struc- high breakdown field of 2.3 MV cm−1 for GaN-on-Si. For
ture of FPs, and how they can help to achieve the optimal (In)Al(Ga)N/GaN heterojunctions the 2DEG in AlGaN/GaN
E-field distribution. Simulations, combined with experimental exhibited a µN as high as 2000 cm2 V−1 s−1 . Without affect-
results, show that the optimum passivation and FP paramet- ing the mobility, Inx Al1− x N/GaN (x ∼ 17%) heterostructures
ers can dramatically improve the performance of AlGaN/GaN with 2DEG ns (2–3 × 1013 cm−2 ), AlN/GaN heterostruc-
HFETs. tures, and multi-channel AlGaN/GaN layers with 2DEG ns
(>4 × 1013 cm−2 ) have been achieved. Finally, the active
Mg concentration within the p-GaN layer has been as high as
4. Conclusions 1018 cm−3 .
All these results show that large-size GaN-on-Si HEMT
In this review, both the theoretical and the experimental epi-wafers lay the foundation for the development of innovat-
advances of GaN-on-Si HEMTs for power applications from ive technology and high-performance GaN-based HEMTs on
materials to devices have been comprehensively analysed Si substrates for power switching applications. The key tech-
and summarised, highlighting the development of high- nologies for fabricating GaN-based HEMTs on Si substrates
performance GaN-based HEMTs on large-size Si substrates are well developed, including device isolation, ohmic con-
for power switching applications. tacts technology, technologies for normally-OFF operation,
After in-depth study, major breakthroughs of large-size gate contact engineering, and passivation and FP engineering.
GaN-on-Si HEMTs epi-wafers of low cost and high quality High performance GaN-based HEMTs on Si substrates have
have been achieved, and each functional layer has demon- been achieved.
strated excellent structural and electrical properties. With For the ohmic contacts, a lower Rc of 0.05 Ω mm has
the advancement in stress control technologies, 10 µm thick been achieved using n++ -GaN regrowth techniques. How-
GaN-on-Si with low threading dislocations of 107 cm−2 ever, other methods for normally-OFF operation, including
has been achieved using an Al-composition step-graded cascode HEMTs, gate recess etching, and F- plasma treatment,

25
Semicond. Sci. Technol. 38 (2023) 063002 Topical Review

Table 4. Characteristics of GaN-based power HEMTs on Si substrates.

No. Structure V TH (V) RON (Ω·mm) V BD (V) References

1 P-N Junction/AlGaN/GaN HEMTs 1.7 26.1 1213 [433]

2 Enhance-mode junction AlGaN/GaN HEMT 1.21 — 1283 [215]
3 E-mode GaN MIS-HEMT 3.8 11.62 1778 [434]
4 p-GaN gate HEMTs 1.1 — 1781 [435]
5 p-GaN gate HEMTs 2.2 20.0 1549 [436]
6 p-NiO gate HEMTs 1.73 11.8 1205 [276]

have achieved a V TH > 3 V, and p-GaN gate HEMTs with a (4) The GaN-on-Si HEMTs fabrication process is compatible
stable V TH > 1.5 V are likely to emerge as the mainstream with Si-CMOS, but GaN-on-Si HEMTs still face a new
single-chip E-mode GaN power transistors in the market. challenge to gate driving circuits due to their relatively
Moreover, GaN-based HEMTs on Si substrates have shown low V TH (approximately 1.5 V), which could lead to integ-
a V BD of 1300 V at an I DS of 1 µA mm−1 using passivation rated GaN-on-Si HEMTs being more complex. Nonethe-
combined with FP engineering. Over the years, GaN-based less, high efficiency, high stability, and miniaturised GaN-
HEMTs on Si substrates have exhibited superior performance, on-Si HEMTs are likely to be achieved.
as shown in table 4.
Currently, GaN-based HEMTs on large-size Si substrates With a comprehensive and in-depth study based on the
with excellent performance and low prices have been widely above issues, both the quality of GaN and the performance
deployed in power switch applications, such as fast charging, of GaN-based HEMTs on large-size Si substrates should be
data centres and LIDAR, amongst others. continuously improved by advancing the structural design and
Although GaN-on-Si HEMTs have made clear progress and technological innovation, and highlighting the performance
have been broadly applied in power switching applications in advantages of GaN-based HEMTs on Si substrates, which is
the medium voltage field, some challenges, which can hinder now close to those of GaN-based HEMTs on SiC substrates.
their replacement of Si-based power devices in the future, Consequently, in the near future we foresee that GaN-based
remain. HEMTs on Si substrates will be widely used, not only in low-
voltage fields such as consumer electronics, but also in more
(1) Although GaN with a low dislocation density (107 cm−2 ) complicated high-voltage fields with higher performance and
on Si without cracks has been achieved, large-size GaN- reliability requirements, such as electric vehicles and smart
on-Si HEMT epi-wafers with a high dislocation density of grids, amongst others.
108 cm−2 can lead to poor crystal quality of the epitaxial
GaN film, the wafer bow being too high to prepare devices.
Consequently, GaN-on-Si HEMTs with a low dislocation Data availability statement
density and the stress control engineering on large-size
substrates (>200 mm) needs to be further explored, partic- No new data were created or analysed in this study.
ularly in the field of p-type GaN-based HEMT epi-wafers.
(2) The stress control layers and HR-GaN between Si
Acknowledgments
and AlGaN/GaN heterojunctions have been inserted to
improve the crystal quality and electrical characteristics,
This research was supported by the National Key Research
but can produce higher interface thermal resistance, res-
and Development Project (No. 2018YFB1801900 and
ulting in problems with device heat dissipation. Moreover,
2018YFB1801902), the Key Area Research and Development
device miniaturisation and the associated high-power
Project of Guangdong Province (No. 2020B010170001), and
density requirements can impact the thermal reliability
Sail Plan of Guangdong Province (No. 2017YT05C007).
of GaN-on-Si HEMTs. Consequently, it is worth redu-
cing the thickness of GaN-on-Si HEMTs without changing
their performance. Conflict of interest
(3) GaN-on-Si HEMTs have been applied in consumer elec-
tronics today. However, they are still limited by current The authors declare no conflict of interest
collapse caused by buffer/surface traps, making it diffi-
cult to develop high-voltage switching applications, such
as new electric vehicles. Consequently, the reliability and ORCID iDs
failure physics of GaN-based HEMTs on Si under voltages
in excess of 650 V, perhaps as high as 1200 V, should be Shanjie Li  [Link]
further examined. Guoqiang Li  [Link]

26
Semicond. Sci. Technol. 38 (2023) 063002 Topical Review

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