Week 2: Assignment 2
Question 1: The CMOS inverter can be used as an amplifier when:
a. NMOS operates in linear region and PMOS operates in saturation region.
b. NMOS operates in saturation region and PMOS operates in linear region.
c. Both NMOS and PMOS operates in linear region.
d. Both NMOS and PMOS operates in saturation region.
Ans: (d) Both NMOS and PMOS operates in saturation region.
Question 2: An ideal inverter exhibits ____ input impedance and ____ output impedance.
a. High; High
b. High; Low
c. Low; High
d. Low; Low
Ans: (b) High; Low
Question 3: A logic family shows the following values: 𝑉𝑂𝐻 = 3.3 𝑉, 𝑉𝑂𝐿 = 0.1 𝑉, 𝑉𝐼𝐻 = 3 𝑉 and
𝑉𝐼𝐿 = 0.5 𝑉. The noise margins 𝑁𝑀ℎ𝑖𝑔ℎ and 𝑁𝑀𝑙𝑜𝑤 are _____ and _____.
a. 0.5V; 0.3V
b. 0.6V; 3.6V
c. 3.2V; 2.5V
d. 0.3V; 0.4V
Ans: (d) 0.3V; 0.4V
Question 4: A fast CMOS inverter can be made by keeping ______.
a. High output capacitance
b. Low output capacitance
c. High on resistance
d. Low input impedance
Ans: (b) Low output capacitance
Question 5: An inverter using very wide transistors is used as a “clock buffer” in a microprocessor to
deliver a 2-GHz clock to various flipflops. Suppose the buffer drives five million transistors (1 million
= 106) with an average width of 1 𝜇𝑚. If the gate length is 0.18 𝜇𝑚, 𝐶𝑂𝑋 = 10 𝑓𝐹/𝜇𝑚2 and the gate
capacitance is approximated by 𝑊𝐿𝐶𝑂𝑋 , determine the power dissipated by the clock buffer. Consider
𝑉𝐷𝐷 = 1.8𝑉.
a. 58.32 𝑊
b. 29.65 𝑊
c. 50.46 𝜇𝑊
d. 11.66 𝜇𝑊
Ans: (a) 58.32 𝑊
Question 6: In a CMOS inverter short circuit power is consumed ______.
a. During charging and discharging of load capacitor
b. Due to Leaking diodes and transistors
c. Due to short circuit paths between supply rails during switching
d. None of the above
Ans: (c) Due to short circuit paths between supply rails during switching
Question 7: In a CMOS inverter, increasing the PMOS width improves _______, but it also degrades
______.
a. tpHL; tpLH
b. tpLH; tpHL
c. VOH; VOL
d. VOL; VOH
Ans: (b) tpLH; tpHL
Question 8: Suppose that in a given process technology, that a unit transistor has an equivalent
resistance of 12 𝑘𝛺 and the equivalent gate/drain capacitance is 2 𝑓𝐹. What is the delay of a FO6
inverter in picoseconds?
a. 299.4 ps
b. 349.3 ps
c. 232.9 ps
d. 116.4 ps
Ans: (c) 232.9 ps
Question 9: When the input of a CMOS inverter is equal to its switching threshold, the transistors are
operating in:
a. NMOS in cut-off and PMOS in saturation
b. PMOS in cut-off and NMOS in saturation
c. Both the transistors are in linear region
d. Both the transistors are in saturation region.
Ans: (d) Both the transistors are in saturation region
Question 10: For the inverter chain shown below, find the minimum delay through the inverter chain.
Consider self-loading (γ=1), input capacitance of A1 to be C1 and load capacitance CL = 27C1.
a. 18 tp0
b. 15 tp0
c. 12 tp0
d. 9 tp0
Ans: (c) 12 tp0
Week 2: Assignment 2: Brief Explanation
Q1. Explanation:
When both NMOS and PMOS are in saturation, the inverter remains in its transition region. Here
small changes in input voltage can cause a large change in output voltage.
Q2. Explanation:
An ideal inverter exhibits high input impedance and low output impedance.
Q3. Explanation:
𝑁𝑀ℎ𝑖𝑔ℎ = 𝑉𝑂𝐻 − 𝑉𝐼𝐻 = 3.3 − 3 = 0.3𝑉
𝑁𝑀𝑙𝑜𝑤 = 𝑉𝐼𝐿 − 𝑉𝑂𝐿 = 0.5 − 0.1 = 0.4𝑉
Q4. Explanation:
A fast CMOS inverter can be made by keeping low output capacitance and decreasing the on
resistance of the transistors.
Q5. Explanation:
𝑓 = 2 × 109
𝐶𝑔𝑎𝑡𝑒 = 𝑊𝐿𝐶𝑂𝑋 = 1 × 0.18 × 10 = 1.8 𝑓𝐹
𝐶𝑡𝑜𝑡𝑎𝑙 𝑙𝑜𝑎𝑑 = 5 × 106 × 1.8 × 10−15 = 9 𝑝𝐹
𝑃 = 𝐶𝐿 𝑉𝐷𝐷 2 𝑓 = 9 × 10−9 × 1.82 × 2 × 109 = 58.32 𝑊
Q6. Explanation:
Short circuit power is consumed due to short circuit paths between supply rails during
switching. While dynamic power is consumed during charging of load capacitor and leakage
power is due to leakage currents of the transistors,
Q7. Explanation:
Improving the PMOS width improves tpLH of the inverter increasing the charging current, but it also
degrades tPHL by causing a large parasitic capacitance. Because as you go on increasing the PMOS
width right, the PMOS itself might be doing very good, but then it will start loading your external
load capacitance.
Q8. Explanation:
An inverter consists of two transistors with only one on at a time, So
𝑅𝑒𝑞 = 12 𝑘Ω
𝐶𝑒𝑞 = 2 × 2 𝑝𝑓 = 4 𝑝𝑓.
𝑡𝑖𝑛𝑣 = ln(2) 𝑅𝑒𝑞 𝐶𝑒𝑞 = 33.27 𝑝𝑠
𝑑𝑒𝑙𝑎𝑦 = 7 × 𝑡𝑖𝑛𝑣 = 232.9 𝑝𝑠
Q9. Explanation:
When the input of the CMOS inverter is equal to switching threshold Voltage, both the transistors are
operating in saturation region.
Q10. Explanation:
𝑁
√𝐹
𝑡𝑝 = 𝑁𝑡𝑝𝑜 (1 + 𝛾
) = 3 × (1 + 3) = 12 𝑡𝑝𝑜
