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SOEN228 Tutorial 8 Sol

The document covers various exercises related to input/output systems in computer hardware, including the importance of clearing input status bits, address decoding for devices, arbiter priority schemes, and PCI protocol signals. It explains how to determine device addresses, the sequence of service grants, and the differences between DEVSEL# and TRDY# signals. Additionally, it discusses the timing diagram for output operations on the PCI bus.

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51 views12 pages

SOEN228 Tutorial 8 Sol

The document covers various exercises related to input/output systems in computer hardware, including the importance of clearing input status bits, address decoding for devices, arbiter priority schemes, and PCI protocol signals. It explains how to determine device addresses, the sequence of service grants, and the differences between DEVSEL# and TRDY# signals. Additionally, it discusses the timing diagram for output operations on the PCI bus.

Uploaded by

suriyapara45
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd

SOEN 228: System Hardware

Tutorial 8: Input/output System

Summer, 2025
Exercise 1
• The input status bit in an interface circuit,
which indicates that new data are
available, is cleared as soon as the input
data register is read. Why is this
important?
Exercise 1
• Otherwise, the same data could be read
twice.
Exercise 2
• The address bus of a computer has 16
address lines,A15−0. If the hexadecimal
address assigned to one device is 7CA4
and the address decoder for that device
ignores lines A8 and A9, what are all the
addresses to which this device will
respond?
Exercise 2
• The device would appear at addresses
7CA4, 7DA4, 7EA4 and 7FA4.
Exercise 3
• An arbiter controls access to a common resource.
It uses a rotating-priority scheme in responding
to requests on lines R1 through R4. Initially, R1
has the highest priority and R4 the lowest
priority. After a request on one of the lines
receives service, that line drops to the lowest
priority, and the next line in sequence becomes
the highest-priority line. For example, after R2
has been serviced, the priority order, starting
with the highest, becomes R3, R4, R1, R2. What
will be the sequence of grants for the following
sequence of requests: R3, R1, R4, R2? Assume
that the last three requests arrive while the first
one is being serviced.
Exercise 3
• After R3 is serviced, the priority order is
R4, R1, R2. Service will proceed in this
order, regardless of the time of arrival of
the requests.
Exercise 4
• Each of the two signals DEVSEL# and
TRDY# of the PCI protocol in Figure 7.19
represents a response from the initiator.
How do the functions of these two signals
differ?
Exercise 4
• The DEVSEL# signal is a response from
the target device to indicate to the
initiator that the device has recognized its
address and is ready to participate in a
data transfer operation. However, data
are not transmitted in every clock cycle.
The TRDY# signal is asserted only during
clock cycles in which data transfer actually
takes place.
Exercise 5
• Draw a timing diagram for transferring
three words to an output device
connected to the PCI bus.
Exercise 5
• The timing diagram for an output
operation is similar to that in Figure 7.19,
with one important difference. Clock cycle
2 in Figure 7.19 is used to turn the AD
lines around. The initiator turns off its bus
drivers, and the target turns on its bus
drivers. This action is not needed in the
case of an output operation, because both
the address and the data are sent by the
initiator. Hence, the initiator may start
sending data in cycle 2
Exercise 5

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