POSSESION OF MOBILES IN EXAM IS UFM PRACTICE

Name ______________ Enrollment No. ______________

Jaypee Institute of Information Technology, Noida

End Semester Examination, December 2017
[Link]. IIIrd Semester

Course Title: Computer Organisation and Architecture Max. Marks: 35

Course Code: 15B11CI313/ 10B11CI613 Max. Time: 2 Hour

Q1 [6 MARKS]. Write the sequence of

micro-operations required for the given
CPU structure in the figure to add a
number to the AC when the number is
a. an immediate operand; ADI 80h
b. a direct-address operand; ADD X
c. an indirect-address operand; ADD [X]

Q2[4 MARKS]. Given following values in various registers/memory of a 8086 system:

IP = 12F6h CS= 0400h DS = 22F8h SS =0400h ES= 0FF5h BX = 2FECh
[25F6C] = 08F0h [2B190] = 0AB8h [25FF5]= 4554h Displacement = 5224h
Find the branch address for a branch instruction that uses:
a. Near Indirect addressing using BX register in register mode.
b. Near Indirect addressing using BX register in register relative mode.

Q3[4 MARKS]. For a 8085 based system, a interrupt service routine is given to transfer 255
bytes from an I/O device (address 80H) to memory. The routine runs following instructions.
(The HL register address and counter C are initialized in the calling program)
ISR: IN 80h
MOV M, A
INX H
DEC C
RET
A DMA controller can also be used to implement the same transfer. Suppose the DMA
requires 20 clock cycles for initialization and other overheads, and each DMA transfer takes
two clock cycles to transfer one byte of data from the device to the memory. What is the
approximate speedup when the DMA controller based design is used in place of the interrupt
driven program based input-output?
Q4 [3+4 MARKS]. A system with 10 MHz clock uses a two level cache. The first level
cache (L1) is direct–mapped, with 4KB capacity and 8 Byte blocks. The second level cache
(L2) is a four way set associative, with 4MB of total capacity and 16-Byte blocks. L1 cache
has a miss rate of 5%, whereas the L2 cache has a miss rate of 10%. L1 hits cause no stalls
with access time of 1 clock cycle. The L2 hit time is 10 cycles. Main memory access time is
100 cycles. There is a 64-bit bus between memory and L2 cache, and between L1 and L2.
a. How many bits are used for line/set address for each cache?
b. What is the average memory access time for any instruction?

Q5 [5+3 MARKS]. An 8085 based system uses two 8255 ships as I/O modules (IOM1 and
IOM2). The I/O module IOM1 has control register address F3h and IOM 2 has A3. The ports A
and B of the two modules are being used as follows:
Port A of IOM1: As input port in mode 1 with programmed I/O.
Port B of IOM2: As output port in mode 1 with programmed I/O.
The control word format is given as:
D7 D6 D5 D4 D3 D2 D1 D0
I/O/BSR Port A mode Direction Direction Port B Direction Direction
A C upper mode B C lower
Status word formats in mode 1 for input and output are given below:
I/O 7 6 5 4 3 2 1 0
Input I/O I/O IBFA INTEA INTRA INTEB IBFB INTRB
Output OBFA INTEA I/O I/O INTRA INTEB OBFB INTRB
a. Write an 8085 assembly language program to (i) initialize I/O modules (IOM 1 and IOM2)
in mode 1 as above, (ii) to get a 10 bytes of data from Port A of IOM 1 and send it to port
B of IOM2 using programmed I/O.
b. Show the appropriate IO interfacing Diagram with 8085 Microprocessor giving address
line decoding.

Q6 [6 MARKS]. A pipelined processor uses a 4-stage instruction pipeline with the following
stages: Instruction fetch (IF), Instruction decode (ID), Execute (EX) and Writeback (WB).
The arithmetic operations as well as the load and store operations are carried out in the EX
stage. The sequence of instructions corresponding to the statement X = (S – R * (P + Q))/T is
given below. The values of variables P, Q, R, S and T are available in the registers R 0, R1, R2,
R3 and R4 respectively, before the execution of the instruction sequence.
ADD R5, R0, R1; R5 R0 + R1
MUL R6, R2, R5; R6R2* R5
SUB R5, R3, R6; R5R3 – R6
DIV R6, R5, R4; R6R5/ R4
STORE R6, X; XR6
The IF, ID and WB stages take 1 clock cycle each, and the EX stage takes 1 clock cycle each
for the ADD, SUB and STORE operations, and 3 clock cycles each for MUL and DIV
operations. Operand forwarding from the EX stage to the ID stage is used. Find the number
of clock cycles required to complete the sequence of instructions given above.
 T3 Paper Solution

Q1 (2 marks for each)

a.
t1: Y<--(IR(address))
t2: Z<--(AC)+(Y)
t3: AC<--(Z)

b.
t1: MAR<--(IR(address))
t2:MBR<--Memory
t3:Y<--(MBR)
t4: Z<--(AC)+(Y)
t5: AC<--(Z)

c.
t1: MAR<--(IR(address))
t2:MBR<--Memory
t3:MAR<--(MBR)
t4:MBR<--Memory
t5:Y<--(MBR)
t6: Z<--(AC)+(Y)
t7: AC<--(Z)

Q2. (2 marks each)

a. PA =DS*10+BX
=22F80 +2FEC
=25F6C
[25F6C]= 08F0
IP= 08F0
PA of branch = CS*10 + IP
= 048F0

b.
PA = DS*10 +BX +DISP
= 22F80 + 2FEC + 5224
= 2B190
[2B190] = 0AB8
IP = 0AB8
PA of branch address = CS*10 +IP
= 04000 + 0AB8
= 04AB8
Q3. (2 marks for DMA time, 2 marks for Interrupt Time, 1 for Speedup)
Time taken with DMA = 20 +2 * 255
= 530 cc
Total T- states in interrupt service routine = 37 cc
Time taken by interrupt service routine to transfer 255 bytes of data = 37 * 255
= 9435
Speedup = TInterrupt/ TDMA
= 9435/ 530
= 17.8
Q4. (3 marks each)
a.
L1 CACHE capacity = 4KB
Line size of L1 = 8 B
No. Of Lines = 4 KB/ 8B= 29
No of bits for Line Address = 9
L2 cache capacity = 4 MB
Line Size of L2 4-way set associative Cache= 16 B
No of Sets in L2 cache = 4 MB/ (4*16 B) = 216
No. Of bits for set address = 16

b.
Hit Ratio L1 = 0.95
Hit Ratio L2 = 0.90
L1 Access Time = 1 cc
L2 Access Time 10 cc
Memory Access Time = 100 cc
Average Memory Access Time = HitRatioL1* AccessTimeL1 + (1- HitRatioL1)*
(MissPenaltyL1)
Miss Penalty L1 = HitRatioL2(AccessTimeL1 +AccessTimeL2) + (1- HitRatioL2) *( Miss
PenaltyL2)
Miss Penalty L2= 1cc+ 10 cc+ 2*100 cc; two transfer from Memory to L2
= 211 cc
Miss Penalty L1 = 0.9 *11 + 0.1 * 211
= 31 cc
Average Memory Access Time= 0.95 * 1+ 0.05* 31
= 2.5 cc
= 2.5 *0.1 us
= 0.25 us
 Q5. ( 2 marks for initialization and 3 for transfer code and 3 for diagram.)
IOM1
F3-Control register
F2 –Port C
F1-Port B
F0-Port A
IOM2
A3-Control register
A2 –Port C
A1-Port B
A0-Port A

Control Word:

IOM1: 1011 0000=B0H

IOM2: 1000 0100=84H

(i) MVI A, B0H

OUT F3H
MVI A, 84H
OUT A3H
(ii) MVI C, 0AH
LOOP1: IN F2
ANI 20H
JZ LOOP1
IN F0H
MOV B, A

LOOP2: IN A2H
ANI 02H
JZ LOOP2
MOV A,B
OUT A1H
DCR C
JNZ LOOP1
HLT

Note: Make diagram

Q6. (6 Marks for correct 12 cc else cut 1 marks if error in forwarding EX to ID stage)
Pipelining is a technique in which the instructions are performed in parallel by executing
different phases of the instructions. Generally, if two operations are performed in which
second operation has dependent operands on first then, the second should not fetch operands
until the first one executes as it will otherwise fetch incorrect operands. Hence, stalls are
created. Now to overcome this, operand forwarding technique was introduced in which there
is an interface through which the operand results are transferred. So, even if the incorrect
operands were fetch during the fetch operations during the execution phase the incorrect
operands are replaced by the
correct operands.

Thus, in the given question, though MUL is dependent on ADD due to R5,SUB is dependent
on MUL due to R6 DIV is dependent on SUB and STORE dependent on DIV still we can
perform Instruction fetch and decode operations in the pipelined processor.

Where,
IF-instruction fetch
ID-instruction decode
EX-execute
WB-write back
As shown in the table 12 clock cycles will be taken to perform the given instructions.