Eng. Ayman Metwali – 966592867601 – [Link]@yahoo.

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 Eng. Ayman Metwali – 966592867601 – [Link]@[Link]

 In Chapter 4 we saw that MARIE have an instruction length of 16 bits and could have, at most, 1 operand
 In another architecture, those could be different
 So, computer architectures generally differs by their Instructions Set format.

 The Instruction set’s features are: (How is the instruction set's differ from each other?)

 Number of bits per instruction: 12, 32 and 64 are the most common
 Type of the CPU elementary memory: Stack-based or register-based (this will affect the instruction
format)
 Number of operands per instruction: Zero, one, two, and three being the most common.
 Operand location: register-to-register, register to-memory or memory-to-memory instructions.
 Types of operations: not only types of operations but also which instructions can access memory and
which cannot.
 Type and size of operands: operands can be addresses, numbers, or even characters.

 During the design phase of a computer architecture, the Instruction set must be optimized.
 The instruction set must match the architecture.
 It must also maximize the efficiency of the computer architecture.

How we measure the efficiency of an ISA? ‫ﻛﯾف ﻧﻘﯾس ﻛﻔﺎﺋﺗﮭﺎ‬

 Instruction set architectures are measured according to:
• Main memory space occupied by a program.
• Instruction complexity: amount of decoding necessary to execute an instruction (number of clock
cycles per instruction)
• Instruction length (in bits).
• Total number of instructions in the instruction set.

 So, things to consider when designing an instruction set include:

• Instruction length
 Short Vs long instructions:
 shorter instructions take up less space in memory 
 shorter instructions can be fetched quickly 
 shorter instructions limit the number of instructions 
 shorter instructions limit the number of operands 
 Variable length VS fixed length instructions:
 Fixed length instructions are easier to decode 
 but Fixed length instructions waste space 
• Number of operands
- Fixed number : Zero, one, two, and three being the most common
- Variable number of operands (even if we have a fixed length instructions): Expanding opcode
(to be explained in this lecture!)
• Addressable registers
- How many? (number of registers)
- How are they stored in the CPU?
• Memory organization
- Word addressable or byte addressable?
- A byte addressable architecture uses little or big endian concept? (to be explained in this
lecture!)
• Addressing modes
- Direct, indirect, immediate, indexed, etc. (to be explained in this lecture!)

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Little VS Big Endian

 If we have a 32 bit data word, how we store this word in a byte addressable memory? The Least significant byte
first? Of the most significant byte first?
 Byte ordering, or endianness, is a major architectural consideration
 We distinguish two concepts for byte ordering:
• Little Endian: A byte with a lower significance is stored in a lower address
• Big Endian: A byte with a higher significance is stored in a lower address

 Example 1: consider an integer requiring 4 bytes:

• On a little endian machine, this is arranged in memory as follows:

Base Address + 0 → Byte0

Base Address + 1 → Byte1
Base Address + 2 → Byte2
Base Address + 3 → Byte3
 Example 2: consider an integer requiring 4 bytes:
• On a big endian machine, this long integer would then be stored as:

Base Address + 0 → Byte3

Base Address + 1 → Byte2
Base Address + 2 → Byte1
Base Address + 3 → Byte0

 Example 3: On a byte-addressable machine, the 32-bit hex value 12345678 is stored at address 0. How is this
value stored in memory if the machine uses a Big Endian concept? A little Endian concept?
• Answer:

 Advantages of Big Endian:

• Is more natural: The most significant byte comes first (lower address).
• The sign of the number can be determined by looking at the byte at address offset 0.
• Strings and integers are stored in the same order.
 Advantages of Little Endian:
• Makes it easier to place values on non-word boundaries.
• High-precision arithmetic is fast and easy.

Final Question: Show how 456789A116 would be stored by machines with 32-bit words, using little endian
and then big endian format. Assume each value starts at address 1016. Draw a diagram of memory for each,
placing the appropriate values in the correct (and labeled) memory locations.( 7.5 Marks)
Ans.
Address 1016 1116 1216 1316
Big Endian 45 67 89 A1
Little Endian A1 89 67 45

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 Eng. Ayman Metwali – 966592867601 – [Link]@[Link]

Internal Storage in the CPU

 Another consideration for architecture design concerns how the CPU will store data.
 We have three choices:
• A stack architecture.
• An accumulator architecture.
• A general purpose register architecture.
 Designers choosing an ISA must decide which will work best in a particular environment and examine the
tradeoffs carefully

 Stack Architecture
• A stack is used to execute instructions
• Instructions and operands are implicitly taken from the stack
• Advantages
- Good code density (an enough number of instruction)
- Simple model for evaluation of expressions ‫طرﯾﻘﺔ ﺳﮭﻠﺔ ﻟوﺿﻊ اﻟﻘﯾم وﺗﻧﻔﯾذ اﻟﻌﻣﻠﯾﺎت‬
• Disadvantages
- A stack cannot be accessed randomly
- Difficult to generate efficient code ‫ﺻﻌوﺑﺔ اﻟﺣﺻول ﻋﻠﻰ اﻟﻛود اﻟﻔﻌﺎل وذﻟك ﻟﻛﺛرة اﻟﻌﻣﻠﯾﺎت‬

 Accumulator architectures
• One operand of a binary operation is implicitly in the accumulator
- Example: MARIE
• Advantages
- Reduce the internal complexity of the machine
- Allow very short instructions
• Disadvantages
- Memory traffic is very high (because I use the memory many times)

 General purpose register architectures (GPR)

‫ وھﻲ أﺳرع ﻣن اﻟﻣﯾﻣوري‬General Purpose Registers ‫ھو اﻟﻧوع اﻟﻣﻧﺗﺷر ھذه اﻷﯾﺎم وھو ﯾﺳﺗﺧدم ﻣﺟﻣوﻋﺔ ﻣن‬ 
‫ ھذه اﻷﯾﺎم‬architecture ‫وھو اﻟﻧوع اﻟﻣﻘﺑول ﻣن اﻟـ‬
• General purpose registers can be used instead of memory
• Advantages
- Registers are faster than memory
- Easy for compilers to deal with
- Can be used very effectively and efficiently ‫ﻣن اﻟﻣﻣﻛن اﺳﺗﻌﻣﺎﻟﮫ ﺑﻛﻔﺎءة وﻓﺎﻋﻠﯾﺔ‬
• Disadvantages
- Long Instructions, long fetch and decode times

 General purpose register architectures (GPR)

• GPR are the most widely accepted models for machine architectures today
• There are three types of GPR
- Memory-memory architectures: may have two or three operands in memory, allowing an
instruction to perform an operation without requiring any operand to be in a register.
- Register-memory architectures: require a mix, where at least one operand is in a register and
one is in memory.
- Load-store architectures: require data to be moved into registers before any operations on
that data are performed.

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Number of operands and Instruction Length

 On current architectures, instructions can be formatted in two ways:

• Fixed length: Wastes space but is relatively fast.
• Variable length: Complex to decode but saves storage space.
 In this course, we will be interested in Fixed length instructions.
In such instructions, we define the maximum number of operands (this number has a direct impact on the length of
the instruction itself)

 Example:
• MARIE uses a fixed-length instruction with a 4-bit opcode and 12-bit operand.
• In MARIE the maximum number of operands is one. Though, some instructions for MARIE have no
operand (for instance: halt).

 The most common instruction formats include zero, one, two, or three operands:
• Zero operand
- OPCODE only
• One operand (usually a memory address)
- OPCODE + 1 Address
• Two operands (usually registers, or one register and one memory address)
- OPCODE + 2 Addresses
• Three operands (usually registers, or combinations of registers and memory)
- OPCODE + 3 Addresses

 Machine instructions that have no operands must use a stack

 In architectures based on stacks, most instructions consist of opcodes only; however, there are special
instructions that have just one operand:
• Push X places the data value found at memory location X onto the stack
• Pop X removes the top element in the stack and stores it at location X

 Example: Suppose we wish to evaluate the following expression: Z = (X x Y) + (W x U)

 The assembly code would be:

For a Three For a Two operand ISA For a one operand ISA (such as
operand ISA MARIE!)

Mult R1, X, Y Load R1, X Load X

Mult R2, W, U Mult R1, Y Mult Y
Add Z, R2, R1 Load R2, W Store Temp
Mult R2, U Load W
Add R1, R2 Mult U
Store Z, R1 Add Temp
Store Z

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 Eng. Ayman Metwali – 966592867601 – [Link]@[Link]

 Example: Suppose we wish to evaluate the following expression: Z = (X x Y) + (W x U)

• In a stack architecture the assembly code would be :

Final Question: Write code to implement the x = (x1 + x2 ) * (x3 + x4) expression on 2-address machine. In
accordance with programming language practice, computing the expression should not change the values of its
operand. [18 marks]

The Answer
Load R1, x1
Add R1, x2
Load R2, x3
Add R2, x4
Mult R2, R1
Store x, R2

Expanding Opcodes
 We have seen how instruction length is affected by the number of operands supported by the ISA.
 In any instruction set, not all instructions require the same number of operands.
 Operations that require no operands, such as HALT, necessarily waste some space when fixed-length
instructions are used.
 One way to recover some of this space is to use expanding opcodes.
 The idea of expanding opcodes is to make some opcodes short, but have a means to provide longer ones when
needed.
 When the opcode is short, a lot of bits are left to hold operands
 So, we could have two or three operands per instruction
 If an instruction has no operands (such as Halt), all the bits can be used for the opcode
 Many unique instructions are hence available
 In between, there are longer opcodes with fewer operands as well as shorter opcodes with more operands.

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 Eng. Ayman Metwali – 966592867601 – [Link]@[Link]

 Example 1: Consider a machine with 16-bit instructions and 16 registers.

• The instruction format can have several structures:
- Opcode + Memory address (such as MARIE):
→ If we have 4KB byte addressable memory we need 12 bits to specify an address
location
→ The remaining 4 bits are used for the opcode: 16 instruction are hence available

- Opcode + Registers Addresses

→ we need 4 bits to select one of the 16 available registers
→ Suppose we have 4 bits opcode, we could encode 16 different instructions with three
operands each (3 x 4 bits = 12 bits).

 Example 2: Consider a machine with 16-bit instructions and 16 registers. And we wish to encode the following
instructions:
- 15 instructions with 3 addresses
- 14 instructions with 2 addresses
- 31 instructions with 1 address
- 16 instructions with 0 addresses

 Can we encode this instruction set in 16 bits?

• Answer: Yes if we use expanding opcodes
 The solution will be as following :
• The first 15 instructions account for:
15x24x24x24 = 15 x 212 = 61440 bit patterns
• The next 14 instructions account for:
14 x 2 x 2 = 15 x 28 = 3584 bit patterns
4 4

• The next 31 instructions account for:

4
31 x 2 = 496 bit patterns
• The last 16 instructions account for 16 bit patterns
• In total we need 61440 + 3584 + 496 + 16 = 65536 different bit patterns
16
• Having a total of 16 bits we can create 2 = 65536 bit patterns
• We have an exact match with no wasted patterns.
• So our instruction set is possible.

• Example 3: Is it possible to design an expanding opcode to allow the following to be encoded with a 12-bit
instruction? Assume a register operand requires 3 bits.
• 4 instructions with 3 registers
• 255 instructions with 1 register
• 16 instructions with 0 register
• Solution:
• The first 4 instructions account for:
• 4x23x23x23 = 4 x 29 = 2048 bit patterns
• The next 255 instructions account for:
• 255 x 23= 2040 bit patterns
• The last 16 instructions account for 16 bit patterns
• In total we need 2048 + 2040 + 16 = 4104 bit patterns

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 Eng. Ayman Metwali – 966592867601 – [Link]@[Link]

• With 12 bit instruction we can only have 212 = 4096 bit patterns
• Required bit patterns (4104) is more than what we have (4096), so this instruction set is not possible
with only 12 bits.
•
 Example 4: Consider a machine with 16-bit instructions and 16 registers. How can we encode this instruction
set in 16 bits? Is there something missing from this instruction set?

• How do we know if the instruction set we want is possible when using expanding opcodes?
• We must determine if we have enough bits to create the desired number of bits patterns

Final Question: Instruction Set Architectures (16 Marks)

1. In a computer system, the instruction length is 11 bits. The instruction set consists of 110 different
operations. All instructions have an operation code part (opcode) and an address part (allowing for only one
address).
a) How many bits are needed for the opcode? (3 Marks)
110 instructions implies 27 (26 will only give us 64 instructions), so 7 bits for the opcode are needed.
b) How many bits are left for the address part of the instruction? (2 Mark)
11 - 7 = 4 bits
2. In order to add more flexibility to this system, we decide to use expanding opcodes to create the following
instruction set:
05, 2-address instructions
45, 1-address instructions
32, 0-address instructions

a) Prove that we can encode the previous instruction set with an 11 bits instruction (assume a 4-bit address
part). (9 Marks)
5, 2 address instructions need:
5x24 x24= 1280 bit patterns (2 Mark)
45, 1-address instructions need:
45 x24 = 720 bit patterns (2 Mark)
32, 0-address instructions need:
32 bit patterns (1 Mark)
In total we need: 1280 + 720 + 32 = 2032 bit patterns (1.5 Mark)
While we have 211 = 2048 bit patterns (1.5 Marks)
So yes, it is feasible by using expanding opcodes because the available bit patterns are more than the needed
ones. (1 Mark)
b) How many unused bit patterns do we have? (2 Mark)
2048 – 2032 = 16 unused bit patterns.

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 Eng. Ayman Metwali – 966592867601 – [Link]@[Link]

Instruction types
 Instructions fall into several broad categories:
• Data movement instructions
- The most frequently used instructions
- Data is moved from memory into registers, from registers to registers, and from registers to
memory
- Examples: Load, Store, Move, Push, Pop, etc.

• Arithmetic instructions
- Include those instructions that use integers and floating point numbers.
- As with the data movement instructions, there are sometimes different instructions for
providing various combinations of register and memory accesses in different addressing
modes.
- Examples: Add, Subtract, Multiply, Increment, Decrement, etc.

• Boolean Instructions
- Perform Boolean expressions.
- Commonly used to control I/O devices.
- Examples: Not, Or, Xor, Test, compare, etc.

• Bit manipulation instructions

- Used for setting and resetting individual bits (or sometimes groups of bits) within a given data
word.
- Examples: Shift left, shift right, rotate left, rotate right

• I/O instructions
- Used to communicate with input/output devices
- Examples: Input, Output.

• Control transfer Instructions

- Include branches, skips and procedure calls.
- Examples: For MARIE we have Jump, skipcond and JnS.

• Special purpose Instructions

- Include those used for string processing, high-level language support, protection, flag control,
and cache management.

 When designing an instruction set for a given architecture, we must respect the following:
• Create a complete instruction set.
• Be careful not to add redundant instructions
• We should respect instructions orthogonality
- Each instruction should perform a unique function without duplicating any other instruction

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Addressing
 Addressing modes specify where an operand is located.
 They can specify a constant, a register, or a memory location.
 The actual location of an operand is its effective address.
 Certain addressing modes allow us to determine the address of an operand dynamically.

 Immediate addressing
• The data is part of the instruction.
• Example: Load 008
- The numeric value 8 is loaded into the AC
 Direct addressing
• The address of the data is given in the instruction.
• Example: Load 008
- The data value found at memory address 008 is loaded into the AC
 Register addressing
• The data is located in a register.
• Example: Load R1.
- The contents of R1 register is used as the operand.
 Indirect addressing
• Gives the address of the address of the data in the instruction.
• Example Load 008
- The data value found at memory address 008 is actually the effective address of the desired
operand.
 Suppose we find the value 2A0 stored in location 008.
 2A0 is the “real” address of the value we want.
 The value found at location 2A0 is then loaded into the AC
 Register indirect addressing
• Uses a register to store the effective address of the data.
• Works exactly the same way as indirect addressing mode, except it uses a register instead of a memory
address to point to the data.
• Example: Load R1
- The effective address of the desired operand is found in R1.
 Indexed addressing
• uses a register (implicitly or explicitly) as an offset, which is added to the address in the operand to
determine the effective address of the data.
• Example: Load X, where the index register holds the value 1.
- The effective address of the operand in actually X + 1
 Based addressing
• Similar to indexed addressing except that a base register is used instead of an index register.
• An index register holds an offset relative to the address given in the instruction, but a base register
holds a base address where the address field represents a displacement from this base.
• Example: Load 3, where the base register holds the address value X.
- The effective address of the operand is actually X +3
 Stack addressing
• The operand is assumed to be on top of the stack.

 Example: For the instruction shown, what value is loaded into the accumulator for each addressing mode?

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 Eng. Ayman Metwali – 966592867601 – [Link]@[Link]

Final Question: Suppose you have the instruction Load 1200 . Given that memory and register R1 contain
the values below. What would be loaded into the accumulator if the addressing mode for the operand is?

a. Direct
b. Indexed
c. Immediate
d. Indirect

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 Eng. Ayman Metwali – 966592867601 – [Link]@[Link]

Final Question: In this part, suppose that:

- The main memory is word addressable (each memory location contains one word) and contains the decimal
values shown in the figure below;
- the computer uses an accumulator architecture and it can handle different types of addressing modes listed in the
table below (table to be copied and filled);
- the register “R1” is implied in the “register addressing” and “register indirect addressing” modes;

Decimal Memory
addresses contents
Table to be copied and filled
Assembly Content of the
Addressing Mode
100 400 Instruction accumulator
… Immediate
200 500 300 Load 200 Direct
… Indirect
300 50 Register
Load R1
… Register Indirect
500 100

What would be the content of the accumulator(in decimal) after the execution of:
a) the assembly instruction“Load 200” when the system uses: Immediate, Direct and Indirect addressing modes.
(6 Marks)
b) the assembly instruction “Load R1” when the system uses: Register addressing and Register Indirect addressing
modes. (4 Marks)
Hint: Answer this partB (B.a and B.b) by copying and filling the above table (entitled “Table to be copied and
Filled”) in your answer sheet.

Content of the
Assembly Instruction Addressing Mode
accumulator
Immediate (2 Marks) 200
Direct
500
Load 200 (2 Marks)
Indirect
100
(2 Marks)
Register
300
(2 Marks)
Load R1
Register indirect
50
(2 Marks)

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 Eng. Ayman Metwali – 966592867601 – [Link]@[Link]

Final Question: Consider the following assembly code written for MARIE:
Load 100
Add 200
Now suppose that MARIE can handle different types of addressing modes.
Given the memory and register R1 containing the values below, and assuming that R1 is implied in the indexed
addressing mode:

What is the value loaded into the AC after executing each of the two instructions?
Hint: Answer this question “a” by Copying and filling the following table in your answer sheet.

Addressing Mode Value Loaded in the AC Value stored in the AC

After LOAD instruction after ADD instruction
Immediate
Direct
Indirect
Indexed

Sol.

Addressing Mode Value Loaded in the AC Value stored in the AC

After LOAD instruction after ADD instruction
Immediate 100 300(100+200)
Direct 500 800(500+300)
Indirect 50 150(50+100)
Indexed 300 400(300+100)

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