2024 Asian Conference on Intelligent Technologies (ACOIT)

Karnataka, India. Sep 6-7, 2024

Implementation and Design of Reversible Logic

Based Carry Tree Adders
Arunkumar K Pavithra V [Link]
Department of ECE Department of ECE Department of ECE
Saveetha Engineering College Saveetha Engineering College Saveetha Engineering College
Chennai, India Chennai, India Chennai, India
2024 Asian Conference on Intelligent Technologies (ACOIT) | 979-8-3503-7495-7/24/$31.00 ©2024 IEEE | DOI: 10.1109/ACOIT62457.2024.10939859

arunkumar@[Link] pavithravm0404@[Link] prithyushaprithi@[Link]

Abstract— Parallel prefix adders excel in reducing delays in accomplish this, reversible circuit must have an identical
VLSI circuits. This work describes three reversible versions: amount of inputs as they have outputs, resulting in an
the Brent-Kung Adder, the tree-spanning Adder, and the optimal matching of the two states. Reversible logic is a
Kogge-Stone Adder. The designs in question have been computer model in which the system's outcome is distinct to
recreated and produced on a Xilinx 14.3 platform with Verilog its inputs. This notion is important in quantum computing,
High-Definition Layout software. In comparison with typical low-power design, and nanoscale since it essentially removes
carry-lookahead adders, the suggested reversible parallel dissipation of energy, a major difficulty in traditional
prefix adders provide large latency savings while maintaining computing. Conventional logic gates, including AND, OR,
energy consumption and area. Reversible logic has emerged as
and XOR, are irreversible because they lose data. For
a possible option to meet the rising demand for cost-effective
processing, especially in the areas of quantum computing,
example, an AND gate's outputs does not independently
inexpensively VLSI design, and nanotechnology. This work define the inputs to be processed. Reversible logic gates,
describes the design and implementation of bidirectional logic- such as the Toffoli, Fredkin, the Peres gates, prevent data
based carry tree adders (CTAs), which are significantly more from being lost throughout computing.
power efficient and faster than ordinary adders. The suggested These devices are essential parts of electronic devices
CTA architecture uses reversible gates like as the Toffoli, that are widely employed in arithmetic computations.
Fredkin, and Peres gates to ensure minimum information loss,
Conventional adder designs are electricity inefficient owing
possibly decreasing power consumption to zero. The carry
in part to the intrinsic loss of data in irrevocable logic gates.
tree's orderly arrangement reduces carry propagated time,
allowing for quicker calculations. A complete design approach
Integrating addition algorithms with reversible logic can
is demonstrated by building a 4-bit reversible CTA, which minimize power consumption while increasing efficiency,
includes circuit designs and gate combinations. making them appropriate for future computing systems,
particularly in quantum computers contexts.
Keywords—Parallel Prefix Adder, Faynman gate, reversible Reversible logic circuits have multiple benefits. First and
PPA, reversible KS adder, reversible Brent-Kung adder foremost, they improve the utilization of energy by
eliminating data corruption, resulting in less heat production
I. INTRODUCTION and less electricity use. The ability to reverse calculations
creates opportunities for mistake repair and innovative
From the very beginning chips made of semiconductors computational approaches. Beyond use in practice, reversible
had only one transistor. As technologies improved, extra logic advances our theoretical knowledge of computation
transistors were crammed onto these silicon devices, and information, and it serves as the basis for quantum
enabling the integration of many functions and systems. computing.
Initially, electronic circuits had a small number of parts such
as diodes, transistors, resistors, which and capacitors that are Energy efficiency: Reversible logic gates are intended to
charged allowing the fabrication of simple logic gates. This reduce energy consumption by retaining all data throughout
step is called small-scale integration (SSI). With additional processing. As transistor size reduce, usage of energy and
advancements, chips might support hundreds of logic gates, current leakages becomes more difficult. Because of its
ushering in the age of large-scale integration. Today's natural emphasis on energy saving, reversible logic may be
microprocessors much exceed these boundaries, with able to address these fuel-related difficulties in modern
millions of gates for reasoning and numerous billions of computer systems.
semiconductors.
Reduced gate count: Reversible logic gates require a
Reversible reasoning assumes a one-to-one relationship smaller number of gates than irreparable gates to provide the
between input and output values. Despite conventional logic, same capability. Reducing gate number in VLSI device
whose may erase knowledge, resulting in energy waste and design can reduce complexity and manufacturing issues
probable mistakes, reverse logic retains every piece of data. associated with smaller feature sizes. Using smaller gates
This notion is based on Landauer's principle, which states simplifies circuit designs, improving manufacturing ability,
that deleting information establishes energy. Bennett's work production, and speed.
also demonstrated a relationship among data deletion and
Signal integrity: Reversal logic circuits frequently
consumption of electricity, suggesting the possibility of
feature lower fan-out and faster signal transmission. in
resource-efficient computing using reversible logic. To
comparison to their irrevocable brethren. These qualities help

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boost the quality of signals by decreasing interface delays are x No feedback loops: The circuit's construction must
cross talk, and generator interference. As a consequence, keep output signals from impacting the internal
irreversible logic can help improve circuit performance and sources.
dependability.
Reversible gates are computing components that maintain
Quantum computing considerations: Reversible logic information correctly. Each one includes a comparable
circuits are very energy efficient because they eliminate amount of inputs and outcomes, and every particular input
information loss during calculations. This benefit becomes variety always results in a different output pair. Most
more significant as transistors decrease, resulting in importantly, this bilateral connection enables for forward as
increased power consumption and leak. Reversible logic, by well as reverse calculation.
eliminating wasted energy via loss of data, provides a
possible answer to current computing's energy issues. A. Feynman Gate
Reverse circuits often have lesser fan-out and quicker signal
The Feynman gate is a fundamental component in the
transmission than traditional logic gates. These qualities
field of programmable electronics. It's a basic yet vital
improve the integrity of signals by minimizing delays,
circuits with both inputs (X and Y) and two outcomes (A and
interference, and electrical noise. Therefore, reversible logic
B). The Feynman gate's functioning is easy to understand:
can increase circuit reliability and performance.
output A exactly reflects input X, whereas output B is the
Reversal logic is vital in quantum technology, where
outcome of a logical XOR operation involving inputs X and
information preservation is critical. Although classical
Y. This simple arrangement serves as a foundation for more
reversible logic does not directly solve quantum computer
complicated reversal circuits. When X is 0, B equals Y;
difficulties, the insights learned during its creation can help
when X is 1, B equals Y. Also, with Y=0, A follows X,
to progress future quantum computers.
hence the Feynman gate is used as a fan-out or duplication
Circuit design and synthesis: Scholars are continually gate. Its plank cost equals one.
researching effective techniques for designing and building
reversal circuits. This includes looking at new gate libraries
in general, reversal gates, and constructing pieces that can
conduct operations with no losing any data.
Optimization techniques: Several optimization methods
are being tested to minimize the number of the gates, trash
products, and planck and colleagues cost in permanent
circuits [11]. This includes approaches like as circuit-level
optimization, logic synthesizing, gate shifting, and Fig. 1. Feynman Gate
technological mapping.
Quantum reversible logic: The use of quantum B. Toffoli Gate
computers relies heavily on reversible logic [39]. The Toffoli gate, an essential part of reverse processing,
Researchers are exploring irreversible logic creation is a three-bit function. It has two command bits plus a single
approaches for nano devices. The objective is to lower the destination bit. The gate's main purpose is to reverse the
traditional cost while improving the preciseness of quantum intended bit while the control bit are in the '1' position. In
computations [11, 12]. every other case, the intended bit is unaffected. The Toffoli
gate is unique for its versatility. This implies that every
II. REVERSIBLE GATES traditional reversal circuit may be built exclusively with
Reversible logic circuits save power by eliminating lost Toffoli gates. This characteristic renders it a key building
information during calculations. This is especially helpful component for creating complicated reversible computer
when transistor sizes decrease, resulting in greater energy use systems. Toffoli Gate shown in Figure 2.
plus leakage. Reverse logic handles contemporary
computing's power problems by saving power. Unlike
standard reversible gates (such as AND, OR, and XOR),
which lose knowledge, bidirectional gates retain every bit of
data.
This happens by including additional input as well as
output lines, which ensure a one-to-one match of the values
entered Implementation of PPA and obtained. The further
input necessary for reversibility is referred to as constant Fig. 2. Toffoli gate
input. Although every output is required for reversible nature
they are not necessarily all used in the last circuit. Unused C. Peres Gate
outputs are known as trash output. Rubbish outputs are those
from a bidirectional circuit which are not used in the final The Peres Gates is a famous gate with a unique design.
calculation. The number of unused outputs varies depending The essential Pere gate is represented on Figure 3. It is a
on the type of reversible gate. There are two major highly noteworthy gate since it has a low atomic cost of 4
restrictions when building reversible circuits as follows: when compared to similar gates in terms of reversibility.

x There is no fan-out; each output can only be linked to The Peres gate is an important bidirectional gate
one input. recognized for its effectiveness. It possesses a lower photon

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cost than other reversible gates, with a value of four. The A. Pre-Computation Stage
Peres gate's effectiveness makes it an invaluable tool in the During the pre-computation step, algorithms (1) and (2)
layout of reversing circuits, since it has the ability to are used to calculate expands and produces based on inputs.
minimize total resource usage.
Pi = Ai ^ Bi (1)
Gi = Ai Bi (2)

B. Prefix Stage
In the prefix stage, group produce and propagation
impulses for all bits are calculated using prescribed
equations. The black cell makes a sequential combination of
these signals that are but the gray cell simply outputs the
Fig. 3. Peres gate
create signal. The basic carry operator, represented by the
symbol "o," combines the create and propagation messages,
D. HNG Gate as seen in the formula (3).Figure 6 shows black and grey
The HNG is a reversible gate with four inputs. and cell.
four outputs (4x4). It maps (I1, I2, I3, I4) to (A= I1, B= I2,
C= I1ْ I2ْ I3, D = (I1ْ I2). I3ْ I1 I2ْ I4), with the
values I1, I2, I3, I4 as inputs and A, B, C, and D as outputs. It
carries an exponential cost of six. Figure 4 shows the
reasoning circuit.
The HNG may function alone as a Reversible Full
Adder. To execute the process as an irreversible complete
adder, regard the 4th input of HNG simply an input that
stays the same (I4 = 0).

Fig. 6. Black and Grey Cell logic definition

(݃‫ܮ‬, ‫ܴ݃(݋)ܮ݌‬, ‫ ܮ݃( = )ܴ݌‬+ ‫ܮ݌‬. ܴ݃, ‫ܮ݌‬. ݃‫)ݎ‬ (3)

Equ (4) and (5) produce and disseminate signals based
Fig. 4. HNG gate on the black and grey cell logic description.
‫݅ܩ‬:݇ = ‫݅ܩ‬:݆ + ܲ݅:݆ . ‫݆ܩ‬í1:݇ (4)
III. IMPLEMENTATION OF PPA
ܲ݅:݇ = ܲ݅:݆ . ݆ܲí1:݇ (5)
A Parallel Prefix Adder (PPA) is a binary adder that
performs rapid additions in electronic circuits. The main In practice, the equations (4) and (5) may be stated
benefit of PPAs is that they are able to do binary sums in utilizing the letter "o" as defined by Brent and Kung.
arithmetic time relative to the amount of bits. This is far Equation (6) represents this symbol, which acts exactly like
quicker than the linear time needed by conventional adder a black cell. The "o" operator makes it easier to create prefix
designs, such as ripple-carry adders. PPA’s basically structures, such as (7).
consists of 3 stages. ‫݅ܩ‬:݇ : ܲ݅:݇ = (‫݅ܩ‬:݆ , ܲ݅:݆ )‫݆ܩ(݋‬í1:݇ , ݆ܲí1:݇ ) (6)

C. Final Computation
The ending calculation's the outcome total and perform
constitute the actual outcomes, as indicated by formulas (7)
and (8). The create and disseminate signals can be coupled
in a variety of ways to obtain the desired carry values.
Multiple prefixes topologies can be created by arranging the
signals accordingly.
ܵ݅ = ܲ݅ . ‫݅ܩ‬íí (7)
‫݊ܩ = ݐݑ݋ܥ‬:1 (8)

D. Reversible Parallel Prefix Adders(PPA)

The incorporation of reversal into PPA was accomplished
by the key usage of structural elements, specifically the PG
interfere with, Grey Cell, and Black Cell. In these sections,
reversible logic gates were used to implement the equations
Fig. 5. Parallel-Prefix structure

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for create and propagate rather than traditional gates. This F. Reversible Brent-Kung Adder
method enabled the whole structure to be accurately The reversible B-K adder is a modified version of the
simulated using reversible gates by guaranteeing that the classic B-K adder that incorporates reversible logic concepts
basic components were reversible. The bidirectional to improve efficiency and reduce the use of electricity during
propagation and produce block was constructed with just one computations. This adder architecture preserves the
Peres gate. Figure 7 shows the reversible construction of the hierarchical layout of the initial Brent-Kung adder, which
Grey, the movie, cell structure, which uses two Peres gates to employs a tree-based technique for carry creation and
acquire the generating signal. propagation, but assuring that the reasoning gates utilized are
reversible. The adder uses irreversible gates, such as Peres
gates, to execute addition while also preserving The
input/output knowledge, allowing for the retracing of
computing steps.

Fig. 7. Block diagram of reversible PPA

E. Reversible Kogge - Stone Adder

The reversible Kogge-Stone adder is a variation version
of the classic Kogge-Stone boost that uses bidirectional logic
concepts to increase energy usage and minimize heat output
while computing. This sort of adder uses reverse gates, such Fig. 9. 16-bit Reversible Brent Kung Adder
as Peres gates, to implement the create and disseminate
operations, permitting it to add while retaining knowledge G. Reversible Spanning tree adder
about its inputs and outputs. The structure preserves the
The reversible spanning tree adder is an instance of adder
multiple carry propagation feature of the typical Kogge-
that utilizes reversible logic concepts with a spanning tree
Stone adder while ensuring that no data is lost throughout the
design to provide rapid addition while consuming very little
calculation process. The adder uses reversible logic, which
power. This beast design takes advantage of reverse gates to
dramatically decreases the use of energy, making it ideal for
guarantee that nothing is lost throughout calculations,
applications requiring little power. Furthermore, the Kogge-
resulting in an increased economical use of energy compared
Stone design enables quick carry transmission, which is
to typical adders.
strengthened in the reversible form.
In a reversible spanning tree adder, carry generation and
propagation are organized in an arrangement resembling a
tree, similar to the structure of prefix adders. This
arrangement allows for parallel carry computations, thereby
improving the speed of addition. The employment of
reversible logic gates, such as Toffoli and Peres gates, allows
for the development of the generation and propagating tasks
while retaining the input-output linkages, ensuring that the
system may be turned without losing information.

Fig. 8. Reversible Kogge Stone Adder 16 -bit

The KS adder performs best in implementations of VLSI.

The adders cover a large area with minimum fan-out. The
Reversal Kogge Stone Adder is recognized as an analog
prefix adder that offers rapid logic addition. Reversible
Kogge Stone adders are preferred for broad adders due to
their lower latency compared to alternative designs. Each
horizontal step creates Promote and manufacture bits. The
final phase involves the generation of bits. Then, each of the
bits be merged with the original spread. The input used to
generate the total number of bits.
Fig. 10. 16-bit Reversible Spanning tree adder

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 IV. SIMULATION & SYNTHESIS RESULTS
The proposed design comprises practical code for
Reversal Sparse Kogge Stone adders, Reversible Spanning
Tree,16-bit Reversible Kogge-Stone, and Reversal Brent-
Kung adders, with corresponding Latency and Area values.

TABLE I. SUMMARAY REPORT OF ADDERS

Name of the Adder No. of No. of bonded Delay(ns)
LUT’s IOB’s
Brent kung Adder 32 50 3.630
Reversible Brent 35 50 3.571
Kung Adder
Kogge stone Adder 42 50 3.671
Reversible Kogge 77 50 2.592
Fig. 13. Stimulation result of Kogge Stone Adder
stone adder
Spanning Tree Adder 28 50 3.249
Reversible spanning 30 50 3.234
Tree adder V. CONCLUSION
This study proposes a simple solution for lowering the
electrical energy usage and latency of Simultaneous Prefix
Adders. Parallel Prefix Adders outperform serial adders in
terms of latency, however this comes at the cost of space.
The results show that carrying chain adders outperform
serialized adders at increasing bit widths. Because adders are
frequently important elements impacting process duration
and energy dispersion in various digital signal processing
and cryptographic implementations, this research focuses on
designing prefix adders that incorporate reversible gates for
logic, specifically using 16-bit Kogge-Stone, 16-bit Brent-
Kung, and 16-bit spanning tree adders.

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