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High-k Dielectrics in CMOS Technology

The document discusses the need for high-k dielectrics in semiconductor technology, listing various materials along with their dielectric constants and energy gaps. It covers the structure and operation of field-effect devices, including their modes of operation and the importance of substrate doping and gate materials. Additionally, it outlines different CMOS processes and variants, as well as the two-terminal MOS structure and its components.

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28 views15 pages

High-k Dielectrics in CMOS Technology

The document discusses the need for high-k dielectrics in semiconductor technology, listing various materials along with their dielectric constants and energy gaps. It covers the structure and operation of field-effect devices, including their modes of operation and the importance of substrate doping and gate materials. Additionally, it outlines different CMOS processes and variants, as well as the two-terminal MOS structure and its components.

Uploaded by

sujalrai199
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd

• Need to look for High-k dielectrics

– Larger thickness while maintaining the same


capacitance per unit area
Dielectric εr Eg (eV)
Si3N4 7 5.3
Ta2O5 22 4.4
HfO2 25 5.8
ZrO2 25 5.8
TiO2 80 3.5
SrTiO3 2000 3.2
SiO2 3.9 9
Aloke Dutta/EE/IIT Kanpur 1
• NA - Substrate Doping (1016-1018 cm–3)
• Gate - typically poly-Si (earlier Al was used)
– Very poor conductor
– Alloyed with W, Ti, Co, Ni, Ta, TaN, TiN to
increase conductivity - called silicides (very high
melting point)
– Also used for source/drain contacts (called self-
aligned silicide - salicide)
• Source/Drain very heavily doped to reduce
their ρ (high σ)
– Thus, produce less RS & RD
Aloke Dutta/EE/IIT Kanpur 2
• Field Effect (Voltage Controlled Device)
• Unipolar, i.e., a single type of carrier (holes
or electrons) contribute to current transport
• Bi-directional device: source and drain
terminals determined by their bias state
• Three modes of operation:
– Accumulation (Capacitor)
– Depletion
– Inversion: Weak, Moderate, and Strong
(Analog Application – Amplifier)
(Digital Application – Switch)
Aloke Dutta/EE/IIT Kanpur 3
Aloke Dutta/EE/IIT Kanpur 4
Aloke Dutta/EE/IIT Kanpur 5
Aloke Dutta/EE/IIT Kanpur 6
TECHNOLOGY
• CMOS Processes
– LOCOS (Local Oxidation of Silicon)
– STI (Shallow Trench Isolation)
– SOI (Silicon-on-Insulator)
• Variants
– n-well
– p-well
– Twin-tub

Aloke Dutta/EE/IIT Kanpur 7


LOCOS CMOS Process

Aloke Dutta/EE/IIT Kanpur 8


STI CMOS Process

Aloke Dutta/EE/IIT Kanpur 9


SOI CMOS Process

Aloke Dutta/EE/IIT Kanpur 10


FINFET

Aloke Dutta/EE/IIT Kanpur 11


VARIOUS PROCESS TECHNOLOGIES

GAA: GATE ALL AROUND


MBC: MULTI BRIDGE CHANNEL (SAMSUNG)

Aloke Dutta/EE/IIT Kanpur 12


THE TWO-TERMINAL
MOS STRUCTURE
(2T-MOS or MOSCAP)

Aloke Dutta/EE/IIT Kanpur 13


• Introduction:
– Three-layer device:
• Substrate (S): Typically Si (Semiconductor)
• Oxide (O): Typically SiO2, of late Si3N4, HfO2,
Ta2O5 (High-k Dielectrics)
• Metal (M): Typically Al, can also be heavily doped
poly-Si (termed as poly), Cu, Ta, Ti, W, etc.
– Two-terminal device:
• Gate (G) and Body (B)
– Three-dimensional device:
• Lateral (x), Vertical (y), and Depth or Width (z)

Aloke Dutta/EE/IIT Kanpur 14


G

Metal (Gate)
z
Oxide (Insulator)
x

Semiconductor
(p-type)
y

Back Ohmic Contact

Aloke Dutta/EE/IIT Kanpur 15

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