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Early Verification and Validation in

Model-Based Design
Amory Wakefield

© 2008 The MathWorks, Inc.

Technical Marketing
The MathWorks
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Introductions

I spend most of my time:

A. Creating specifications and requirements (systems and software)

B. Implementation based on specification and requirements created

by somebody else (generating, writing, deploying, debugging
code)

C. Both

D. None of the above

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Address the Entire Development Process

Requirements
Requirements

Design System V&V

Requirements Validation
Environment Robustness Testing
Modeling Standards Checking

Physical Components

Component V&V
Algorithms Design Verification
Model Testing
Coverage and Test Generation
Ge
e

H
Ge and
rat

ne

ne - Property Proving
ne

ra
rat

te
Ge

Code Verification
Digital Embedded Code Correctness
Electronics Software Processor-In-The Loop Testing
VHDL, Verilog C, C++

FPGA ASIC MCU DSP Integration Testing

Software Integration Testing
Integration Hardware-in-the-Loop Testing
Hardware Connectivity
Implement

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Methods for Verification and Validation

ƒ Traceability
ƒ Requirements to model and code
ƒ Model to code
ƒ Modeling and Coding Standards
ƒ Modeling standards checking
ƒ Coding standards checking
ƒ Testing
ƒ Model testing in simulation
ƒ Processor-in-the-loop
ƒ Proving
ƒ Proving design properties
ƒ Proving code correctness

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Increasing Confidence in Your Designs

Confidence

Traceability Modeling and Coding Model and Code Proving Design

Standards Checking Testing Properties and Code
Correctness

Verification Method

5
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Traceability System V&V

Comp. V&V
Integration
Functional Requirements

Design

Environment

Physical Components ƒTracing RequirementsÙModel

Simulink Verification and Validation
Algorithms

H
Ge and ƒTracing ModelÙSource Code
Ge
e
rat

ne -
ne

ra
Real-Time Workshop Embedded Coder
ne

te
rat
Ge

Digital Embedded
Electronics Software ƒTracing RequirementsÙSource Code
VHDL, Verilog C, C++ Simulink Verification and Validation
FPGA ASIC MCU DSP

Integration
Implement

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Tracing RequirementsÙModel System V&V

Comp. V&V
Simulink Verification and Validation Integration

ƒ Creating links between text documents and model objects

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Tracing RequirementsÙSource Code System V&V

Comp. V&V
Simulink Verification and Validation Integration

Real-Time Workshop Embedded Coder

ƒ Including requirements in the generated source code

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Requirements Traceability—Overview System V&V

Comp. V&V
Simulink Verification and Validation Integration

ƒ Bidirectional linking with

external documents
ƒ For Simulink and Stateflow
ƒ Extensibility API
ƒ Report generation
ƒ DOORS integration
ƒ Linking with read-only
requirement documents
ƒ Real-Time Workshop Telelogic DOORS
Microsoft Word
Embedded Coder integration Microsoft Excel
ƒ Embeds requirements as PDF
comments in source code HTML
Text
Supported document formats
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Modeling and Coding Standards System V&V

Comp. V&V
Coding Standards Integration

Modeling Standards

Design

Environment

Physical Components ƒ Modeling Standards Checking

Simulink Verification and Validation
Algorithms

H
Ge and
Ge
e
rat

ne -
ne

ra
ne

te
rat
Ge

Digital
Electronics
Embedded
Software
ƒ Coding Standards Checking
VHDL, Verilog C, C++
PolySpaceTM Client for C/C++

FPGA ASIC MCU DSP

Integration
Implement

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Simulink Model Advisor

Model Checking
ƒ Enforce modeling best
practices
ƒ Detect and troubleshoot
modeling and code generation
issues
ƒ Check models for (a subset of)
known version upgrade issues

ƒ Automated report is a useful

process audit document:
ƒ More detailed summary
ƒ Valid check states: Pass, Fail,
Warning, and Not Run

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Modeling Standards Checking

Simulink Verification and Validation

ƒ Static analysis of models for

ƒ Requirement consistency
ƒ Custom checks for company-
specific processes
ƒ Standards
ƒ MAAB Style Guidelines
ƒ DO-178B
ƒ IEC 61508
ƒ Custom – using extensibility API

ƒ Benefits
ƒ Prevent problems early in the design process
ƒ Automate time consuming review work

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MAAB Style Guide Checks

ƒ MathWorks Automotive Advisory Board (MAAB)

ƒ Consistency
ƒ Interoperability
ƒ Error prevention
ƒ Knowledge sharing

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IEC 61508 Modeling Standards Checks

This Absolute Value This Relational Operator block is

block is operating on not outputting a Boolean data type
an unsigned value which may lead to unpredictable
which could result in results in the generated code.
unreachable code.

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Coding Standards Checking System V&V

Comp. V&V
PolySpace Client for C/C++ Integration

ƒ Configure rules and run as part of the static check of the

C source code

ƒ MISRA-C:2004
ƒ Covers 122/142 rules
ƒ 102 fully supported
ƒ 20 partially supported

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Testing System V&V

Comp. V&V
Integration
Functional Requirements

Design
ƒModel Testing
Environment
ƒSystemTest
Physical Components
ƒSimulink Verification and Validation
ƒSimulink Design Verifier
Algorithms
Verify that design meets
H
Ge and
requirements
Ge
e
rat

ne -
ne

ra
ne

te
rat

ƒCode Testing
Ge

Digital
Electronics
Embedded
Software
ƒReal-Time Workshop
VHDL, Verilog C, C++
Embedded Coder
ƒEmbedded IDE Link products
FPGA ASIC MCU DSP ƒTarget Support Package products
Integration Verify that the behavior of
Implement
source code and object code
matches the model
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Demo

ƒ Model testing using test cases stored in Excel

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Improving Test Suite System V&V

Comp. V&V
Simulink Design Verifier Integration

ƒ Generating tests to reach coverage criteria

Test Generation

Test generation harness with the

copy of the original model Test inputs that ensure complete
coverage

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Code Testing with Generated Signals

Simulink
ƒ Software-in-the-loop
ƒ On the host
ƒ Processor-in-the-loop
ƒ On the target processor

ƒ Independent code testing

environment
ƒ Generated signals and model outputs
are saved as a .mat data file
ƒ Exported input signals drive code
tests
ƒ Exported model outputs become
expectation values for code testing

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Proving System V&V

Comp. V&V
Integration
Requirements
Requirements

Design

Environment

Physical Components ƒ Proving Design Properties

Simulink Design Verifier
Algorithms
Prove that design meets
H
Ge and the key functional
Ge
e
rat

ne -
ne

ra
ne

te
requirements
rat
Ge

Digital Embedded
Electronics Software ƒ Proving Code Correctness
VHDL, Verilog C, C++ PolySpace Server for C/C++
FPGA ASIC MCU DSP Prove that code meets
Integration
non-functional runtime
requirements
Implement

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Proving Properties – Workflows System V&V

Comp. V&V

Simulink Design Verifier Integration

1. Authoring ƒ Benefits
ƒ Highly Iterative ƒ Leads to precise definition of low
ƒ Leads to improvement in level functional requirements
design and in specifications ƒ Once established, properties
2. Execution and Reporting represent a model of design
behavior
ƒ Automated
ƒ Minimizes chance of implementing
ƒ Part of the regression
undesired behavior
testing harness

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Proving Code Correctness System V&V

Comp. V&V
Integration
Requirements
Requirements

Design
ƒ Verifying code integration
Environment
ƒ Certification requirements
Physical Components
ƒ Reliability concerns
Algorithms
e

Ge
rat

ne
ne

ne -
te
Ge and
rat

ra
Ge

Digital Embedded
Electronics Software

VHDL, Verilog C, C++

ƒ Proving Code Correctness
PolySpace Server for C/C++
FPGA ASIC MCU DSP

Integration
Implement

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Code Correctness Formal method:

Abstract Interpretation

Green Green
reliable reliable
P
r
o Red Green
v faulty reliable
e
n
Grey
dead
Green
Orange reliable
unproven

Results are proven for

all possible executions of the code!! 24
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Summary

ƒ Model-Based Design enables early verification and

validation

ƒ Early verification and validation methods improve and

optimize your existing development process

ƒ Early problem detection significantly reduces time spent

debugging – shorter time to resolution

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