Digital assignment 4

(c) a SR flip-flop and a T flip-flop

1. S-R flip-flop can be converted to T-type flip-flop. If
(d) two SR flip-flop
(a) S and R are connected to Q and Q respectively.. 10. The characteristic equation of the T-FF is given by
(b) S is connected to Q (a) Q  TQ  QT
(c) R is connected to Q
(d) Both S and R are shortened (b) Q  TQ  TQ
2. The main difference between JK and RS flip-flop is that
(a) JK flip does not need a clock pulse (c) Q  TQ
(b) JK flip-flop accepts both input as 1
(c) there is a feedback in JK flip- flop (d) Q  TQ
(d) JK flip-flop is acronym of junction cathode Common Data For Questions 10 and 11
multivibrator A counter is shown below:
3. T flip-flop is commonly used as
(a) a digital counter and frequency divider QC
QA QB QD
(b) a digital counter only JA JB JC JD
(c) a delay switch
(d) none of these O C O C O C O C
4. In figure, assume that initially Q = 1. With clock pulses
being given , the subsequent states of Q will be? KA O
KB O KC O KD O O
CLK OCLR O CLR O CLR O CLR

11. The counter shown is

(a) Mod-12 (b) Mod-9
(a) 1, 0, 1, 0, 1, 0, 1,.............. (c) Mod-14 (d) None
(b) 0, 1, 0, 1, 0, 1, 0,.............. 12. Frequency of output QD assuming 1 MHz I/P frequency
(c) 0, 0, 1, 0, 0, 1, 0,.............. (a) 633 kHz (b) 833 kHz
(d) 1, 1, 0, 1, 1, 0, 1,.............. (c) 733 kHz (d) None
5. In a sequential circuit, the outputs at any instant of time
depends. 13. The input signal V shown in below fig., is applied to the
i
(a) only on the inputs present at that instant of FF, when initially in 0 state Assume all timing constraints
time are satisfied. The output Q is
(b) on past outputs as well as present inputs
(c) only on the past inputs Vi T Q
(d) only on the present outputs
CLK
6. The S and R inputs of S-R flip-flop are called synchro -
nous inputs because
(a) When S = 1, Q =0 Q

(b) When S = 1, Q = 0
(c) the data on these inputs are transferred on the
output
(d) The data is transferred to output only when
clock signal is applied to it.
7. Suppose input to J-K flip-flop is J = 0, K = 1with applied
clock pulse of 20 ms and the propagation delay time of 2
nsec. Then the operation performed is
(a) flip-flop race around condition
(b) flip-flop toggle
(c) flip -flop normal operation
(d) Both (a) and (b)
8. How many flip-flops are required to build a binary
counter circuit to count from 0 to 2048?
14. Consider the circuit shown in below figure?
(a) 10 (b) 9
(c) 11 (d) 8
9. The master slave JK flip-flop is effectively a combination
of
(a) a T flip-flop and a D flip-flop
(b) an SR flip-flop and a D flip-flop The expression for the next state Q is
 (a) xQ (b) xQ (a) 010000 (b) 010101
(c) x  Q (d) x  Q (c) 010010 (d) 011001
19. The shift register shown in the given figure is initially
15. To convert any counter into count down, the gate that
loaded with the bit pattern 1010. Sub sequently the shift
can be used is
register is clocked, and with each clock pulse the
(a) XNOR (b) AND
pattern gets shifted by one bit position to be right. With
(c) XOR (d) OR
each shift the bit at the serial input is pushed to the left
16. A sequential circuit using D flip-flop and logic gates is
most position (msb). After how many clock pulses will
shown where X and Y are inputs and Z is the output .
the content of the shift register become 1010 again?
Then the circuit is

Clock
Serial 1 0 1 0
input

(a) RS flip-flop with X = R and Y = S (a) 3 (b) 11

(b) JK flip-flop with X = J and Y = K (c) 7 (d) 10
(c) RS flip-flop with X = Z and Y = R 20. To realize the given truth table from the circuit shown in
(d) JK flip-flop with X = K and Y = J the figure the input to J in terms of A and B would have
17. The circuit realization of the combination logic clock to be
shown in figure to obtain the following truth table will be
A B Q
0 0 Qn
0 1 1
1 0 Qn
1 1 0 Truth Table

(a) A (b) B
(c) AB (d) AB
21. Figure below shown D type Flip-flops connected as

shift register, then outputs Q , Q , Q , Q

D C B A are
given by
18. In a JK flip-flop we have J = Q and K = 1. Assuming
the flip-flop was initially cleared and then clocked for 6
pulses, the sequence at the 0 output will be
DA DB DC DD
O
QA O
QB O
QC O QD

CLK

(i) (ii) (iii)

0001 0011 1110
0010 0001 1111
0100 1000 0111
 0001 0100 0011 (d) one clock delay element
(a) i, ii and iii (b) i and ii only 28. Match the pair
(c) ii and iii only (d) None of these
22. An X-Y flip-flop, whose Characteristic Table is given
below is to be implemented using a J-K flip-flop Group I Group II
A shift register For code
A can be used 1 conversion
Qn +1
X Y A
To generate
0 0 1
B multiplexer
can be used
2
memory chip
select

0 1 Qn C
A decoder
can be used 3
For parallel to
serial
conversion

1 0 Qn
4 As a many to
1 1 0 one switch

For analog to
5
digital
This can be done by making conversion

(a) J  Y, K  X (b) J  X, K  Y

(c) J  Y, K  X (d) J  X, K  Y (a)  A   3,  B   4 ,  C   2

23. A 4 bit modulo-6 ripple counter uses JK flip-flop. If the
propagation delay of each FF is 50 ns, the maximum
(b)  A   5,  B    4 ,  C   1
clock frequency that can be used equals to [ Gate 1987]
(a) 20 MHz (b) 10 MHz (c)  A    4  ,  B    2  ,  C    3
(c) 5 MHz (d) 4 MHz
24. Advantage of synchronous sequence curcuit over (d)  A    3 ,  B    4  ,  C    5 
asychronous ones is: [EC - Gate 1990] 29. In a J-K flip-flop we have J = Q’ and K = 1 (Figure
(a) faster operation shown) Assuming that the flip-flop was initially cleared
(b) ease of avoiiding problems due to hazards and then clocked for 6 pulses , the sequence at the Q
(c) lower hardware requirment output will be [ Gate 1997]
(d) better noise immunity
(e) None of the above
25. An S-R FLIP-FLOP can converted into a JK FLIP-FLOP J Q
by connecting________ to Q and_________to Q
[ Gate 1991]
(a) S’, R’ (b) S, R’
K CK Q
(c) S’, R (d) S, R
26. For the initial state of 000, the function performed bu the
arrangement of the J-K fliop-flop in the figure
[Gate 1993] (a) 010000 (b) 011001
(c) 010010 (d) 010101
30. In Figure, A = 1 and B = 1, the input B is now replaced
by a sequence 101010...... the output x and y will be

(a) Shift Register (b) Mod-3 Counter

(c) Mod-6 Counter (d) Mod-2 Counter
(e) None of the above (a) fixed at 0 and 1, respectively
27. An R-S latch is [EC-Gate 1995] (b) x = 1010... , while y = 0101....
(a) Combinational circuit (c) x = 1010..... while y = 1010.....
(b) synchronous sequential circuit (d) fixed at 1 and 0 respectively
(c) one bit memory element
31. Figure shows a mod-K counter, here K is equal to
X Y
Digital
Block

J Q J Q
t0 t t t3 t 0 t1 t 2 t3 t 4
1 2

1 K Q 1 K Q

CLK

(a) 1 (b) 2
(c) 3 (d) 4
32. The following arrangement of master-slave flip-flop has
the initial state of P, Q as 0, 1 (respectively) . After
three clock cycles the output state P, Q is (respectively),

P 0 Q 1

D
J K
1

Clock

(a) 1, 0 (b) 1, 1
(c) 0, 0 (d) 0, 1
33 shown in the figure where X and Y are the input and Z is
the output. The circuit is [EC- Gate 2000]

36. Consider the partial implementation of a 2-bits cunter

using T flip-flops following the sequence 0-2-3-1-0, as
shown below.

(a) S-R Flip-Flop with inputs X = S and Y = R

(b) S-R Flip-Flop with inputs X = R and Y = S
T
1 Q2 T1 Q1
(c) J-K Flip-flop with inputs X = K and Y = J
(d) J-K Flip-Flop with inputs X = J and Y = K
34. In the figure, the J and K inputs of all the four Flip-Flops MSB LSB
are made high. The frequency of the signal at output Y
CLK
is [ Gate 2001]
To complete the circuit, the input X should be
(a) Q2’ (b) Q2 + Q1
(c) (Q1  Q2)’ (d) Q1  Q2
37. In SR latch made by cross-coupling two NAND gates if
both S and R inputs are to 0, then it will result in .
(a) Q = 0, Q’ = 1 (b) Q = 1, Q’ = 0
(a) 0.833 KHz (b) 0.77 KHz (c) Q = 1, Q’ = 1 (d) Indeterminate states
(c) 0.91 KHz (d) 1.0 KHz 38. A digital system is required to amplify a binary-encoded
35. The digital block in the figure is realized using two audio signal. The user should be able to control the gain
positive edge triggered D-flip flops. Assume that for of the amplifier from a minimum to a maximum in 100
t  t0. Q1  Q2  0. The circuit in the digital block is increments. The minimum number of bits required to
encode in straight binary is
given by.
(a) 8 (b) 7
(c) 6 (d) 5
39. Choose the correct one from among the alternatives A,
B, C, D after matching an item from Group 1 with the The flip-flop are positive edge triggered D FFs. Each
most appropriate item in Group 2. Q0Q1 . Let the
state is designated as a two bit string
initial state be 00. The state transition sequence is
Group 1 Group 2
[ Gate 2005]
1 Frequency
P Shift register division 00 => 11 => 01
(a)
Q Addressing in
Counter memory chips
2 00 => 11
(b)
R Serial to
Decoder 3 parallel data
conversion 00 => 10 => 01 => 11
(c)

00 => 11 => 01 => 10

(a) P  3, Q,  2, R  1 (d)
(b) P-2, Q  1, R  2 44. The given figure shows a ripple counter using positive
(c) P  2, Q  1, R  3 edge triggered flip-flops.
(d) P-  3, Q  1, R  2
40. A master-slave flipflop has the charactristic that If the present state of the counter is Q2Q1Q0  011,
(a) change in the input immediately reflected in the
output then its next state  Q2Q1Q0  will be [ Gate 2005]
(b) change in the output occurs when the state of
the slave is affected 1 1
(c) change in the output occurs when the state of
the master is affected 1
(d) both the master and the slave are affected at T0 Q0 T1 Q1 T2 Q2
the same time
41. In the modulo-6 ripple counter shown in the figure, the CLK Q0 Q1 Q2
output of the 2-input gate is used to clear the J-K
flip flops. (a) 111 (b) 101
(c) 100 (d) 010
1 45. The present output Qn of an edge triggered JK flip-flop
C J B J A J
is logic 0. If J = 1, then Qn 1
C K B K A K
(a) will be logic 0
(b) will be logic 1
2-input (c) cannote be determined
gate (d) will race around
46. Two D-flip-flops as, shown below, are to be connected
The 2- input gate is as a synchronous counter that goes throuh the follow
ing Q1 Q0 sequence
(a) an OR gate (b) a NOR gate
(c) a NAND gate (d) an AND gate 00  01  11  10  00...
42. How many pulses are needed to change the contents of
The input D0 and D1 respectively should be
a 8-bit up- counter from 10101100 to 00100111 (rightmost
bit is the LSB)? connected as
(a) 134 (b) 133
(c) 124 (d) 123 D0 Q0 D1 Q1
43. Consider the following circuit
LSB MSB
CK Q0 CK Q1
D0 Q0 D1 Q1

Q0 Q1 Clock

CLK (a) Q1Q0 and Q1Q0

 (b) Q0 and Q1 Q1 Q2
(c) Q0 Q0 and Q1Q0 J1 Q1 J2 Q2
Clock JK Flip Flop JK Flip Flop
(d) Q1 and Q0 1 K
K1 Q1 2 Q2
47. The following binary value were applied to the X and Y
inputs to the NAND latch shown in the figure in the
sequence indicated below.
X = 0, Y = 1; X = 0, Y = 0; X = 1, Y = 1. (a) 01, 10, 11, 00, 01,....
The corresponding stable P, Q outputs will be (b) 11, 10, 00, 11, 10,....
[ Gate 2007] (c) 00, 11, 01, 10, 00,....
(d) 01, 10, 00, 01, 10,....
50. The characteristic equation of a JK flip flop is:
(A) Qn 1  J.Q n  K.Qn

(a) P = 1, Q = 0 ; P = 1, Q = 0 ; P = 1, Q = 0
(B) Q n 1  J.Q n  K.Q n
or P = 0, Q = 1 (C) Qn 1  Qn ..J.K
(b) P = 1, Q = 0 ; P = 1, Q = 1 ; P = 1, Q = 0
or P = 0, Q = 1 (D) Qn 1  J  K  Q n
(c) P = 1, Q = 0 ; P = 0, Q = 1,
or P = 0, Q = 1 ; P = 0, Q = 1 51. A reduced state table has 18 rows . The minimum
(d) P = 1, Q = 0 ; P = 1, Q = 1 ; P = 1, Q = 1 number of Flip flops needed to implement the
48. Refer to the NAND and NOR latches shown in the figure sequential machine is :
(A) 18 (B) 9

. The inputs P1 , P2  for both the latches are first (C) 5 (D) 4
made (0, 1) and then, after a few seconds, made (1, 1). 52. What are the value of Q1 and Q2 after 4 clock cycles
The corresponding stable outputs Q1 , Q2   are if innitial value are 00 in the sequntial circuit shown
below :

P1 O P1
O Q1 O O Q1

O Q2 O Q2
P2 O P2 O

(A) 11 (B) 10
(a) NAND: first (0, 1) then (0, 1) NOR: first (1,0) (C) 01 (D) 00
then (0, 0) 53. A 4 bit modulo-6 ripple cunter uses JK flip-flop if the
(b) NAND: first (1,0) then (1,0) NOR : first ( 1,0) propagation delay of each FF is 70ns the maximum
then (1, 0 ) clock frequency that can be used is equal to:
(c) NAND: first (1, 0) then (1, 1) NOR : first ( 0, 1) (A) 3 . MHz (B) 3 . 6MHz
then (0, 1) (C) 4 . 2MHz (D) 4 . 9MHz

(d) NAND : first(1, 0 ) then (1, 0) NOR : first (1, 0) 54. In figure assume that initially Q = 1, With clockpulses being
then (0, 0) given, the subsequencent status of Q will be
49. 
What are the counting states Q1 , Q2  for the
counter shown in the figure below

(A) 1,0,1,0,1,0,1,....
(B) 0,0,1,0,01,0,.....
(C) 0,1,0,1,0,10,....
 (D) 1,1,0,1,0,1,0,....
55. Consider the circuit shown below .In a certain steady,Y
is at logical ‘1’. What are possible values of A.B.C.?
[Dec 2012 paper 2]

(A) A=0, B=0, C=1 (B) A=0, B=C=1

(C) A=1,B=C=0 (D) A=B=1,C=1
56. In the following question match each of the items A , B
and C on the left with an approximation item on the
right

Codes :
a b c
(A) 1 2 3
(B) 1 3 5
(C) 5 4 2
(D) 3 4 1
57. In the sequential circuit showm below if the initial
value of the output Q1Q0 is 00, what are the next
values of Q 1Q 0 ?

(A) 11,10,01,00 (B) 10,11,01,00

(C) 10,00,01,11 (D) 11,10,00,01,