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Single-Phase Single-Stage Isolated ZCS Current-Fed Full-Bridge Converter

for High Power AC/DC Applications

Article in IEEE Transactions on Power Electronics · September 2017

DOI: 10.1109/TPEL.2016.2623771

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6800 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 32, NO. 9, SEPTEMBER 2017

Single-Phase Single-Stage Isolated ZCS Current-Fed

Full-Bridge Converter for High-Power
AC/DC Applications
Chushan Li, Yu Zhang, Member, IEEE, Zhifang Cao, and Dewei XU, Member, IEEE

Abstract—In this paper, a single-phase single-stage isolated zero single PSU to reduce the total cost of system. In high power
current switched (ZCS) current-fed full-bridge ac/dc converter PSU, IGBT is preferred compared to MOSFET due to its lower
is proposed for IGBT-based high-power power factor correction conduction loss on higher current rating. Also, the following
(PFC) applications. By adding an additional commutation path
and few resonant components, ZCS operation is realized for all two requirements should be complied by the converters:
IGBTs. The conduction loss is also lowered by the additional path. 1) power factor correction (PFC) and harmonics elimina-
Furthermore, the control strategy for the proposed converter is tion: Standards such as IEC 1000-3-2 strictly demand the
compatible with that developed for traditional PFC converter. In quality of the input ac current to satisfy the grid code,
this paper, the topology derivation and circuit operational analysis especially for these rectifiers with higher power rating;
are given. The control strategy is introduced. A 3-kw prototype is
developed and tested to verify the circuit functionality. Finally, the 2) galvanic isolation: In order to guarantee the customers’
efficiency performance is investigated and comparison is made to safety, isolation is mandatory in these applications. High-
show the advantages of the topology. frequency transformer is preferred to achieve higher
Index Terms—AC–DC power conversion, dc power systems,
power density.
PFC, single stage, zero current switched (ZCS). Generally speaking, commercialized single-phase products
usually employ a single switch topology based (flyback, for-
I. INTRODUCTION ward, etc.) single-stage configuration for low power rating appli-
C/DC converters, also known as rectifiers, are the crucial cations [5] and a two-stage system configuration for high power
A power electronic facilities that build the interface between
the ac grid and massive dc equipments. Following the emerging
rating applications [6]. Single switch single-stage solutions are
not acceptable by high-power ac/dc applications mainly because
of high-power dc applications such as the modern data center or of its lower efficiency and high-voltage stress. Two-stage solu-
commercial building dc distribution system, high power ac–dc tion usually consists of a front-end boost PFC stage followed
converters are required. Summarized by [3], the present modular by an isolated dc–dc stage. Bulky dc link capacitors are also
designs of power supply unit (PSU) for data center are rated on required between the two stages. The main drawback of the
10, 15, or 20 kW. Typical solution of one such module consists of two-stage solution is that the bulk decoupling capacitor often
three 5 kW single-phase rectifiers connected together [4]. Seven uses high failure rate electrolytic capacitors, which significantly
PSUs are parallel connected in the rack system to form a redun- increase the volume and cost, and limit the reliability of the
dant 100-kW supply. The selection of 5-kW power rating for one whole system.
single-phase converter is mainly because of the MOSFET maxi- Single-stage bridge-type ac–dc converters with isolation can
mum current capability. On the other hand, commonly used soft- be used in high-power single-phase PFC applications instead
switching dc–dc converter for PSUs such as LLC converter has of the two-stage solution. Single-stage converters with dc-link
its optimized power rating, which is also around 5 kW. However, capacitor are developed to eliminate the boost stage and de-
with increasing power rating of data center, more PSUs have to crease the volume of the dc-link capacitance. The circuit in
be parallel installed, which increase the system complexity and [7]–[8] is the combination of diode rectifier and voltage source
the cost. There is a clear tendency to raise the power rating of full-bridge converter, where the boost function is realized by
the full-bridge circuit switching. The problem is that, since the
Manuscript received December 3, 2015; revised April 11, 2016, June 17, duty cycle cannot be fixed due to PFC operation, the voltage
2016, and September 29, 2016; accepted October 21, 2016. Date of publication on the dc-link capacitor will be varying continuously and may
November 1, 2016; date of current version April 24, 2017. Recommended for
publication by Associate Editor J. Biela.
exceed the switches’ voltage rating under the light load con-
C. Li, Z. Cao, and D. XU are with the Department of Electrical and dition. Several improvements are found in [9]–[11] where the
Computer Engineering, Ryerson University, ON M5B 2K3, Canada (e-mail: input current is controlled to be discontinuous or asymmetric
[email protected]; [email protected]; [email protected]).
Z. Yu is with the School of Electrical and Electronic Engineering,
pulse width modulation (PWM) is implemented. However, per-
Huazhong University of Science & Technology, Wuhan 430074, China (e-mail: formance is scarified such that the input current total harmonics
[email protected]). distortion (THD) is lower. Instead of using PWM control, res-
Color versions of one or more of the figures in this paper are available online
at http://ieeexplore.ieee.org.
onant full bridge circuit is proposed in [12] and [13] to better
Digital Object Identifier 10.1109/TPEL.2016.2623771 regulate the dc bus voltage and realize soft switching. However,
0885-8993 © 2016 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.
See http://www.ieee.org/publications standards/publications/rights/index.html for more information.
LI et al.: SINGLE-PHASE SINGLE-STAGE ISOLATED ZCS CURRENT-FED FULL-BRIDGE CONVERTER FOR HIGH-POWER AC/DC APPLICATIONS 6801

a large frequency variation is required since the input voltage

is changing from zero to its maximum. The current is distorted
especially when it is crossing zero. Also, filter design becomes
complex because of this frequency variation.
Single-stage converters with no dc-link capacitor potentially
have higher power density since the capacitor in the dc link
is almost eliminated. Current-fed bridge converter is preferred
since it just likes the boost PFC circuit. As shown in [14], the
current-fed full bridge circuit is applied with a clamping cir-
cuit added. This circuit is necessary because that during the Fig. 1. Current-fed single-stage ac–dc converter based on similar ZCS dc–dc
topology.
operation, when the input inductor and the leakage inductor
of the transformer are connected together during the switch-
ing transient, high voltage spike will take place on switches.
Topologies with more complex clamping circuit can be found
in [15] and [16]. The use of passive snubbers is demonstrated
in [17]. However, the practicability of these solutions is low
because too many additional components are required. Another
solution is to use the active switches instead of diode rectifier in
the secondary side to create soft-switching condition [18], but
this makes the cost higher than the diode-based design. Other
solutions such as voltage-fed buck-type circuit [19], resonant-
type circuit [20] and [21], and dual active bridge (DAB) type Fig. 2. Proposed single-stage isolated ZCS current-fed full-bridge ac–dc con-
verter.
circuit [22] and [23] can also implemented to avoid the voltage
spike problem. But the input current performance still cannot
be as good as compared with the current source input circuit.
diodes Do1 −Do4 and high frequency transformer T1 form the
This is because of the nonlinear transfer-function between the
basic full bridge circuit. A capacitor Cr inserted between the
PWM output to input current. Also fast changing input voltage
mid-points of two bridges. By adding another small resonant
makes the control design very complex. Another important fact
inductor Lr and four series-connected diodes D1 −D4 , ZCS
should be pointed out that most of the aforementioned ac–dc
operation can be realized. As the forced commutation is avoided,
converters with soft-switching capability are implementing the
voltage spike will not take place during the switching transient.
zero-voltage-switched (ZVS) operation. However, the duration
However, this circuit has the following two drawbacks:
of IGBT turning OFF is longer than MOSFET due to its tail
1) higher conduction loss due to the four series-connected
current effect. ZVS operation requires large parallel capacitor
diodes;
for IGBT to reduce the turn-OFF loss. On the contrary, ZCS
2) higher diode voltage rating and reverse recovery loss due
operation eliminates IGBT turn-OFF loss without parallel ca-
to the resonant operation.
pacitors. As a result, the high-power ac–dc application prefers
To solve above-mentioned problems, an additional commu-
ZCS operation of IGBT.
tation path is added parallel with the full bridge circuit. The
In this paper, a novel single-phase single-stage ac/dc topology
proposed topology is shown in Fig. 2. In this circuit, the res-
is proposed. The topology is aiming to high-power PFC appli-
onant inductor is spitted to Lr 1 and Lr 2 . Thus, a portion of
cations, which use IGBTs and enable ZCS operation. By adding
them can be realized by trace inductance. ZCS turning ON and
an additional commutation path to current-fed ac-dc converter,
turning OFF can still realize for all the IGBTs. The new circuit
ZCS is realized for all IGBTs to avoid additional absorb circuit.
is similar with the traditional two-stage solution, where the in-
Meanwhile, the conduction loss is also lowered through the ad-
termediate dc-link capacitor is eliminated. S1 (D1 ) is the boost
ditional commutation path. Furthermore, the control strategy
main switch, which conducts during the boost “ON” time. All
for the proposed converter is compatible with that for the tradi-
the other devices S2 (D2 ) − S5 (D5 ) and Do1 −Do4 composes
tional PFC converter. In this paper, the topology derivation and
the full-bridge circuit that operates during the boost “OFF”
circuit operational analysis are given. The soft-switching design
time. Half of the IGBTs conduct during the “OFF” time to out-
process is derived. The components selection and control strat-
put a square wave voltage. High-frequency transformer T1 is
egy is introduced. Experiment is carried out to verify the circuit
used to achieve galvanic isolation. Lk represents its leakage
functionality. Finally, the results are evaluated by comparing the
inductance.
efficiency. The estimation of the losses shows the benefit of the
In the following section, the circuit operational principle and
circuit.
analysis are given to show the operating principle of soft switch-
ing. The criterion of soft-switching is also derived.
II. PROPOSED CIRCUIT ANALYSIS
A. Topology Explanation B. Circuit Operational Analysis
In this paper, inspired by a ZCS dc–dc topology shown in [24], One switching period is divided into two symmetric subpe-
a ZCS ac–dc converter is given in Fig. 1. IGBTs S1 −S4 , output riods corresponding to positive and negative cycle of T1 . One
6802 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 32, NO. 9, SEPTEMBER 2017

Fig. 3. Operational process of proposed converter. (a) Interval 0 [t0 − t1 ], (b) Interval 1 [t1 − t2 ], (c) Interval 2 [t2 − t3 ], (d) Interval 3 [t3 − t4 ], (e) Interval
4 [t4 − t5 ], (f) Interval 5 [t5 − t6 ].

subperiod is further divided into five intervals. The positive

subperiod is taken as example to demonstrate the operation.
The corresponding equivalent circuits are given in Fig. 3(a)–(f),
the key waveforms are shown in Fig. 4, where vC r , vS 1 , vD 1 ,
vS 2 , and vD 2 represent the voltage across Cr , S1 , D1 , S2 , and
D2 , respectively, and iin , ik , iL 1 , and iL 2 represent the current
go through Lin , Lk , L1 , and L2 . The positive directions are
marked out in Fig. 2. It is assumed that the output dc voltage
vdc and input ac voltage vin remains almost constant during
one switching period.
Interval 0 [t0 –t1 ]: The equivalent circuit of this interval is
shown in Fig. 3(a). During this interval, S2 and S5 are in ON
state; S1 , S4 , and S3 are in OFF state. The capacitor voltage vC r
is in steady state, which can be given by
n1
vC r = vdc (1)
n2

where vdc is the output dc voltage. The voltages on S1 , S3 ,

and S4 are equal to vC r . This interval can be considered as the
“OFF” state of a boost converter.
Interval 1 [t1 –t2 ]: The equivalent circuit of this interval is
displayed in Fig. 3(b). At the time t1 , S1 is turned ON. Cr begins
to resonant with both Lr 1 + Lr 2 and Lk . The current rising rate
of S1 is limited by Lr 1 and Lr 2 , which shows that it is ZCS Fig. 4. Operational waveforms for proposed converter.
LI et al.: SINGLE-PHASE SINGLE-STAGE ISOLATED ZCS CURRENT-FED FULL-BRIDGE CONVERTER FOR HIGH-POWER AC/DC APPLICATIONS 6803

turned ON. The value of Cr is selected to ensure that the energy follow the bellowing resonance equations:
in Cr is large enough compared to Lr 1 , Lr 2 , and Lk , so vC r vin + vC r
will keep almost constant during this interval. The commuta- iLin = ILin0 cos [ωr (t − t3 )] + sin [ωr (t − t3 )]
Zr
tion time that allows current changing from Lr2 to Lr1 can be (5)
calculated as
vC r = −vin + (vin + VC r 0 ) cos [ωr (t − t3 )]
(Lr 1 + Lr 2 )iLin
tc1 ≈ . (2) − Zr ILin0 sin [ωr (t − t3 )] (6)
vC r
Where ωr and Zr are given by
It is decided by the input current iLin and vC r . After cur-
1
rent in Lr 2 decreases to zero, D2 and D5 experience the re- ωr = 
verse recovery process. The reverse voltage on both diodes is (Lr 2 + Lin )Cr
half of vC r , which means that higher diode voltage rating is 
Lr 2 + Lin
avoided for D2 and D5 . After the reverse recovery, the voltages Zr = . (7)
Cr
on D2 and D5 change to half of vC r . The voltage on S3 and S4
will decrease because of the partial discharge of their parasitic ILin0 is the initial values of iLin , VC r 0 is almost equal to vdc ·
output capacitor. Accordingly, the voltage on D3 and D4 will n1 /n2 . The duration of interval 3 and 4 can be calculated by
increase. using (6) where vC r is equal to −vdc · n1 /n2 . This resonance
At the same time, Cr continues to resonant with Lk . The process will not affect the waveform of iLin under normal load
current in Lk decreases to zero at the time t2 . As vC r almost condition since the energy in Lin is much larger than that in
keeps constant, and the changing rate is limited by Lk , Do1 and Cr . Thus, the current has a small ripple in one switching cycle.
Do4 are ZCS turned OFF. Usually, the inductance of Lr 1 + Lr 2 However, this effect becomes more significant when iLin is
are set to be rather small, thus tc1 is shorter than t2 − t1 . The crossing zero or under light load condition. As a result, the input
duration of interval 1 is defined by the resonant time and is current THD performance will be affected slightly as well.
approximately given by Interval 5 [t5 –t6 ]: The equivalent circuit of this interval is
shown in Fig. 3(f). After vC r falls below −vdc n1 /n2 , Do2 , and
π Do3 are turned ON again. Cr Begins to resonant with Lk . The
t2 − t 1 ≈ Lk Cr . (3)
2 maximum voltage overshoot will be

Interval 2 [t2 –t3 ]: In this interval, S2 and S5 can be turned Δv = ILinm ax
Lk
. (8)
OFF at any time since the current has decreased to zero already. Cr
Thus they are in ZCS turned OFF. As shown in Fig. 3(c), only The maximum IGBT voltage on the primary side will be
S1 and D1 are in ON state during this time. This interval is 
equal to the “ON” state of boost PFC circuit. Compared to n1 Lk
Vswitch = vdc + ILinm ax . (9)
the circuit shown in Fig. 1, where always two IGBTs and two n2 Cr
diodes are in the current path, only one IGBT and one diode is According to the analysis, all the IGBTs are clamped to Cr
in the current path in this interval, thus the conduction loss is during the operation. It can be inferred from (9) that keeping the
lower. inductance of Lk as small as possible can limit the over voltage
Interval 3 [t3 –t4 ]: At the time t3 , S3 and S4 are turned ON of vC r and limit the voltages on all the IGBTs. This will also
simultaneously. Cr begins to resonant with Lr 1 + Lr 2 again. make the volume of Cr smaller.
The current increasing rate on S3 and S4 is limited by Lr 1 and One positive subperiod is from interval 0 to interval 4. The
Lr 2 . It implies that they are ZCS turned ON. The current in negative subperiod begins with the interval 5, where S3 and
Lr 1 falls gradually to zero and is reverse blocked by D1 . The S4 become active instead of S2 and S5 . But the commutation
diode parasitic capacitor and resonant inductors resonant causes process will be similar to the positive subperiod and we will not
over voltage on D1 . Therefore, a higher voltage-rating device go into details here.
is required. Similar with interval 1, the duration of this interval
can be calculated as C. Soft-Switching Design Criterion
(Lr 1 + Lr 2 )iLin According to the former analysis, there are three commutation
tc2 = t4 − t3 ≈ . (4) intervals in one subperiod, which are interval 1, interval 3, and
vC r
interval 4. Minimum commutation time should be guaranteed
The equivalent circuit of this interval is displayed in Fig. 3(d). to ensure the soft-switching performance.
Interval 4 [t4 –t5 ]: In this interval, current in Lr 1 decreases During the interval 1 and 3, an overlap gate signal is gen-
to zero. S1 can be turned OFF in this interval with ZCS. Cr erated for S1 and Sx (x = 2 − 5) to ensure the current is fully
continues to be discharged by vin through Lin and Lr 2 . vC r commutated between Lr 1 and Lr 2 . According to (2) and (4), the
goes to negative finally. The equivalent circuit is shown in worst case takes place when input current iLin reach its maxi-
Fig. 3(e). It can be found that, during this interval, voltages mum value. Assuming that PFC function is realized, this case
on all the OFF-state IGBTs are clamped by Cr . vC r and iLin takes place when ac voltage is on its peak. The lower limit of
6804 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 32, NO. 9, SEPTEMBER 2017

Fig. 5. Control diagram implemented to proposed circuit.

this overlap time is given by

n2 (Lr 1 + Lr 2 )iLinm ax
td1 > . (10)
n1 vdc
During the interval 4, the S1 turning OFF S1 should be no
later than vC r changes its polarity. Otherwise the current will
go through S1 again and ZCS condition is lost. Thus, the over-
lap time has its upper limit. The worst case still takes place
when input current iLin reaches its maximum value, which is
given by
Cr n1 vdc Fig. 6. Gating pattern demonstration.
td1 < . (11)
n2 iLinm ax
Here it is assumed that the energy in Lin is much larger than
in Cr . Thus, Cr is continuously discharged by a constant current given as an example to show the design procedure. It should be
source Lin . Equations (10) and (11) can always have its solution pointed out that the 3 kW power rating is only for an easier pro-
if (12) is satisfied. This infers that the energy in Cr should totype. The power rating is not optimized for the IGBT-based
always be larger than the energy in Lr 1 and Lr 2 . As long as vdc circuit, which will make the efficiency lower than a conventional
is fixed all the time, the soft switching can be guaranteed if the MOSFET-based circuit. The target of the proposed topology is
maximum input current is limited much higher than 3 kW. Because of this target, the switching
 2 frequency is kept to be 10 kHz. This low frequency will some-
2 n1 vdc
(Lr 1 + Lr 2 )iLinm ax < Cr . (12) how limit the performance of efficiency as well as the THD of
n2 input current.
III. CONTROL STRATEGY EXPLANATION
A. Transformer Design
The control strategy of the proposed PFC converter is fully
The leakage inductance of the transformer T1 will affect the
compatible with a traditional continuous current mode (CCM)
over voltage on all IGBTs and then decide the volume of Cr . As
PFC control. Only an additional gating signal distribution block
a result, the transformer should be designed first and the leakage
is added to generate the gating signals for all the IGBTs. It
inductance is then tested.
only needs digital logic gates and flip-flop gates. The complete
The steady-state relationship between the input ac voltage
control block is given in Fig. 5. The traditional voltage-current
and output dc voltage is derived in (13), which is also similar
double loop control is adopted. The only modification is that a
with a classic boost converter
minimum duty cycle is required to generate the overlap time.
Based on the control diagram, the resultant gating pattern is vac (t)
vdc = . (13)
demonstrated in Fig. 6. The frequency of Gs1 is the same as N [1 − d(t)]
the converter switching frequency. Frequencies of other IGBTs The turn ratio N of T1 is then decided to guarantee the ac
are all divided by two as the using of J-K flip-flop gate. td1 peak voltage is lower than vdc ·N thus, the converter can always
represents the overlap time. operate under boost mode. Typically, for a 208 Vrm s ac voltage
input and 400 V dc voltage output, the turn ratio could be set
IV. DESIGN AND SELECTION OF SYSTEM COMPONENTS
to N = n1 : n2 = 7 : 8. The primary side steady-state voltage
The major part of the proposed converter is a boost-type will be clamped to 350 V when the secondary side dc voltage
PFC converter. As a result, the design process for most of the is 400 V.
system components follows the common design process for tra- The number of turns for transformer can be calculated based
ditional PFC converter. A 3 kW, 10 kHz switching prototype is on the traditional magnetic design. Equation (13) is derived
LI et al.: SINGLE-PHASE SINGLE-STAGE ISOLATED ZCS CURRENT-FED FULL-BRIDGE CONVERTER FOR HIGH-POWER AC/DC APPLICATIONS 6805

TABLE I TABLE II
SPECIFICATION OF PROTOTYPE SELECTION OF COMPONENTS AND PARAMETERS USED FOR LOSS CALCULATION

Real value Per unit value Components Component type and its parameters for loss calculation

System input and output IGBT S 1 −S 5 IKW30N60T (650 V, 30 A; v c e 0 = 0.8 V, r c = 0.02 Ω;

C o s s = 108 pF)
Output power P o u t 3 kW 1.0 p.u. Si Diode D 1 DSEP 60-12 A (1200 V, 60 A; v D 0 = 1.25 V,
Input rms ac voltage V i n 208 V a c 1.0 p.u. r D = 0.016 Ω; Q r r ( I p e a k ) = 1250 nC)
Input rms ac current I a c 14.4 A 1.0 p.u. Diode D 2 −D 5 , Output VS-40EPF (600 V, 60 A; v D 0 = 0.75 V, r D = 0.015 Ω;
Base impedance Zb a s e 14.42 Ω 1.0 p.u. rectifier Diode D o 1 −D o 4 Q r r ( I p e a k ) = 1000 nC)
Output dc voltage V d c 400 Vd c Input rectifier Diode PB4006 (600 V, 40 A; v D 0 = 0.9 V)
Switching frequency f s w 10 kHz (S1 switching D i n 1 −D i n 4
frequency: 20 kHz) Transformer T 1 Two EE85B Ferrite core transformer connected in
seriesN p r i = 29, N s e c = 33, AWG #16 Litz wire∗2
Filter and transformer parameters (A e = 8.57 cm2 , V e = 162 cm3 , B m a x = 0.18T,
P v = 40 mW/ cm3 , R t r a n p r i a c = 100 mΩ,
Input inductor L i n 650 μH (Δ I ࣈ 7.7 A) 0.017 p.u. R t r a n s e c a c = 96 mΩ)
Output capacitor C o 3300 μF 17.6 p.u. Inductor L i n Two stacked Kool Mμ toroid core 0077908A7 from
Grid filter capacitor C f i l t e r 3 μF 0.016 p.u. Magnetics Inc.N = 105, AWG #16 Litz wire∗2 (μ = 26,
Turn ratio N = n 1 : n 2 58:66 A e = 2 ∗ 2.21 cm2 , V e = 2 ∗ 43.4 cm3 , B m a x = 0.42T,
Leakage inductor L k 6 μH 0.00016 p.u. K = 120, α = 2.09, β = 1.46, R i n d a c = 100 mΩ)

Resonant component parameters

Commutation inductor L r 1 , 0.5 μH + 2 μH 0.000065 p.u.

Lr 2
Clamping capacitor C r 220 nF 0.0012 p.u.

based on the maximum allowable flux density Bm ax , core cross-

section area Ae , and output dc voltage vdc
vdc · Ts /2 vdc · Ts /2
n2 = , n1 = N (14)
2Bm ax Ae 2Bm ax Ae
where Ts is the switching period.

B. Input Inductor Design

Design of passive components for ac–dc converter can be
referred to [25]. Under continuous current mode, the relationship
between the input inductance Lin and maximum input current
ripple IΔ m ax is given by Fig. 7. Photograph of the 3-kW prototype.

vdc N Ts
Lin = . (15)
4IΔ m ax
D. 3-kW Prototype Specification
C. Resonant Components Design In this paper, the experiment is carried out based on a 3-kw
After Lk is measured, the clamping capacitor Cr could be prototype. The specification of the prototype is given in Table I.
selected. Referring to (9), the volume of Cr is given by The detailed selection for all switches and parameters for mag-
netic components are shown in Table II. 1200-V rating diode
Lk iLinm ax 2 is selected for D1 as analyzed before. It should be pointed out
Cr = (16)
(vlim it − N · vdc )2 that because of the materials availability, the transformer is real-
ized by two EE85B core transformers connected in series. Each
where iLinm ax is the maximum inductor current including the transformer will share half of the primary and secondary wind-
current ripple, vlim it is the allowance voltage applied to all ings. The core of the inductor is made by two Kool Mμ toroid
switches. For a typical 600 V IGBT application, this voltage is cores stacked together. In order to facilitate the loss calculation,
set to 550 V, where the over voltage is limited to 150 V. all parameters are tested and listed in Table II. The details of all
The volume of Lr 1 and Lr 2 should comply with the limitation parameters are given in Appendix.
given in (12). This limitation is easy to be satisfied. Tradeoff for
the value of Lr is made between lower the di/dt when diode
is turned OFF or shorter the commutation time. Compromise is V. EXPERIMENTAL RESULTS DEMONSTRATION
made based on experimental loss test. For the 3-kw prototype, The photograph of the 3-kW prototype is shown in Fig. 7. The
the Lr 1 and Lr 2 are set to be 2.5 μH in total. The overlap time dimensions of the heatsink and the board, as well as the position
td1 used for commutation is set to be 1 μs. of main components are marked. The experimental results are
6806 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 32, NO. 9, SEPTEMBER 2017

Fig. 8. Waveforms of IGBT S 1 (a) large time-scale view, (b) ZCS turned ON, (c) ZCS turned OFF.

Fig. 9. Waveforms of IGBT S 2 (a) large time-scale view, (b) ZCS turned ON.

illustrated in Figs. 8–14. The waveforms are captured under Fig. 10 demonstrates the voltage and current waveforms for
rated load condition. Figs. 8–11 are taken when the input ac D1 and D2 , where vg 1 , D1 voltage vD 1 , D2 voltage vD 2 , iL r 1 ,
voltage is at its peak. and iL r 2 are given. As shown in Fig. 10(a) and (c), a slight
Fig. 8 shows the voltage and current waveforms for IGBT S1 difference with the theoretical waveform shown in Fig. 4 is the
where its gating signal vg 1 , collector–emitter voltage vce1 and resonance when diodes are OFF. This is because that their junc-
Lr 1 current iL r 1 are given. According to the large time-scale tion parasitic capacitor is charged when Cr resonant with Lk .
waveforms given in Fig. 8(a), resonance takes place on vce1 , The peak voltage of the resonance is low, thus can be neglected
which is caused by the resonating between Cr and Lk . Well- during analysis.–Fig. 10(c) and (d) shows the reverse recovery
designed Cr limits the over voltage to around 500 V under rated process for the two diodes, respectively. As previously analyzed,
load condition. It can be inferred from Fig. 8(b) and (c) that ZCS D1 has a higher resonant voltage during the reverse recovery.
turning ON and OFF are both realized for S1 . Either 1200-V diode or small RC snubber circuit is required.
Fig. 9 shows the voltage and current waveforms for IGBT S2 Both solutions will slightly affect the efficiency. In the devel-
where its gating signal vg 2 , collector–emitter voltage vce2 , and oped 3-kw prototype, 1200-V diode is used. While the diodes
Lr 2 current iL r 2 are given. According to the large time-scale D2 −D5 only need normal 600-V diode.
waveforms given in Fig. 9(a), vce2 rises when iL r 2 go through The waveforms of transformer T1 , capacitor Cr and output
IGBT group S3 −S4 . Thus, it is obviously turned OFF in ZCS. diode Do1 is given in Fig. 11. Gating signal vg 1 , transformer
Fig. 9(b) proves that it is ZCS turned ON as well. current iL k , transformer secondary winding voltage vsec ,
LI et al.: SINGLE-PHASE SINGLE-STAGE ISOLATED ZCS CURRENT-FED FULL-BRIDGE CONVERTER FOR HIGH-POWER AC/DC APPLICATIONS 6807

Fig. 10. Waveforms of diode D 1 and D 2 (a) large time-scale view for D 1 , (b) D 1 reverse recovery, (c) large time-scale view for D 2 , (d) D 2 reverse recovery.

Fig. 11. Waveforms of transformer T 1 , capacitor C r , and output diode D o 1 (a) C r , (b) T 1 and D o .

capacitor voltage vC r , and output diode voltage vD o1 are shown mainly caused by resonance between Cr and Lin . The power
respectively. According to voltage waveform of Cr , resonant factor performance of the converter is given in Fig. 15. It can be
voltage is limited to 500 V. According to iL k , Do1 is turned OFF found that the power factor can be maintained to be higher than
under no reverse recovery. Switching loss is eliminated. 98% within nearly entire load range.
The PFC performance is demonstrated in Fig. 12. Accord-
ing to the waveforms shown in Fig. 12(a), although the input VI. EFFICIENCY PERFORMANCE AND LOSS DISTRIBUTION
voltage vac is distorted because of a nonideal autotransformer ANALYSIS
input, the input current iac maintains a good sinusoidal wave.
A. Efficiency Performance Evaluation
The dc voltage vdc is regulated to 400 V. The voltage after the
diode rectifier vrec and input inductor current iLin is shown in The efficiency of the 3-kW prototype is tested. Based on the
Fig. 12(b). The fast Fourier transform (FFT) analysis for iac is components selection given in Table II, efficiency estimation is
given in Fig. 12(c). The THD is 5.2% according to the FFT anal- also made to compare with the test results and show the loss
ysis. Main contents of harmonics are mainly on low frequency distribution. The loss model is given in Appendix, where the
odd orders. parameters are extracted from the datasheet and demonstrated
The total demand distortion (TDD) performance of the con- in Table II.
verter is given to further verify how much harmonics are gen- The efficiency curve related to output power is shown in
erated if varying the output power and the input ac voltage. Fig. 16. From full load to half load, the tested efficiency is
The results are given in Figs. 13 and 14, respectively. It can around 93% to 94%. It can be found that there is no significant
be found that, despite of voltage and load changing, the TDD difference between the tested and estimated efficiency. Consid-
performance does not change too much. As mentioned in the ering some niche losses such as sampling resistor, small resonant
theoretical analysis, the slightly higher input current TDD is inductor, and resonant capacitor loss are not taken into account,
6808 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 32, NO. 9, SEPTEMBER 2017

Fig. 12. Input and output analysis (a) ac input voltage, ac input current, and dc voltage, (b) FFT analysis for input current.

the estimation results do have a good coincidence with the real

case. The estimated loss for converter in Fig. 1 is also given. It
can be found that almost 1% efficiency decreasing is expected
compared to the proposed converter.
The estimated loss distribution is shown in Fig. 17. The def-
initions of all part of losses are given in Appendix. From the
results, it can be found that almost 38% of the total loss can be
attributed to magnetic loss induced by transformer and induc-
tor. As soft switching is realized for all IGBTs, only 9.44% is
switching loss including the reverse recovery loss of diodes and
the parasitic capacitor loss of IGBTs. This part of loss can be
even lower if replace D1 with SiC diode.
Fig. 13. TDD performance under different output power rating (V a c = By further investigating the loss distribution pie chart, an
208 V). assumption can be made that the efficiency performance will
be higher even with increasing switching frequency. The
main reason is: due to the magnetic material limitation, losses
on both inductor and transformer are too high compared to
the commercialized design. The design of the transformer is
limited by the maximum flux density, which makes a very
large copper loss and very small iron loss. By increasing
the switching frequency, fewer winding turns are expected.
A balanced copper and iron loss will make the transformer
efficient. On the other hand, the inductor also has a large copper
loss. If increasing the switching frequency to make the inductor
smaller, lower copper loss is expected.

B. Comparison Between Topologies

A comprehensive comparison is made between the proposed
Fig. 14. TDD performance different input ac voltage (P o u t = 3000 W). circuit, industrial standards and commercialized solution [3],
LI et al.: SINGLE-PHASE SINGLE-STAGE ISOLATED ZCS CURRENT-FED FULL-BRIDGE CONVERTER FOR HIGH-POWER AC/DC APPLICATIONS 6809

[26]–[27] and several recent-published topologies given in the

review section.
The 80 Plus Titanium specification [26] is the highest in-
dustry standard that is widely accepted for the computer PSUs.
By comparison, two-stage standard solution still shows better
performance. As stated in the design part, these are mainly be-
cause the 3-kw power rating is more favorable by MOSFET
than IGBT. With the increasing of the power rating, it becomes
difficult to find 650-V MOSFET with large current capacity. On
the contrary, the IGBTs of this current rating are popular. Also
from the cost point of view, if the power rating of one ac–dc
circuit without parallel is going to be large such as 15 kW, the
industry should prefer to use IGBT instead of MOSFET since Fig. 15. Power factor performance under different output power rating (V a c =
the price of IGBT will become cheaper. When applying IGBTs 208 V).
to the soft-switching dc–dc stage of the two-stage standard solu-
tions with high power (>10 kW) [28]–[30], it can be found that
the efficiency typically is around 94%–96.5% when the load is
changing from 20% to 100% whatever LLC or PS-FB topology
is used. On the other hand, the efficiency of the PFC stage us-
ing MOSFET is around 98% [27]. However, if higher power is
required, products can only either use several MOSFET-based
circuits paralleled together or use IGBT-based single-phase PFC
stage where more loss will be produced because of more switch-
ing loss. As a result, by comparing the IGBT-based two-stage
solution with the proposed circuit, it can be found that, the effi-
ciency performance of the proposed circuit will be higher than
the two-stage solution even if the tested proposed circuit is a
3-kW prototype. When redesigning the prototype for higher Fig. 16. Efficiency versus output power.
power rating (>10 kW) applications, fewer portions of conduc-
tion loss on magnetic components can be realized. The proposed
solution will show higher performance and catch up with the
highest industrial standards.
The proposed converter is also compared with several recent-
published topologies given in the review section. According to
the results, either the proposed topology has much higher effi-
ciency or lower THD compared to the solutions [9], [15] which
also use low switching frequency. On the other hand, it can be in-
ferred from these solutions [9], [15] that it is difficult to achieve
high performance under low switching frequency. Compared
with other topologies using much higher switching frequency,
the proposed solution still has comparable performance than
single-stage topologies [10], [20].
Another comparison is made on several aspects including the
requirement of passive components, number of active compo-
nents, forms of additional soft-switching components, conduc-
tion loss (represent by how many switches in the current path), Fig. 17. Estimated loss distribution under 3-kW rated power condition.
and switching loss (represent by whether the switches are under
soft-switching and types of hard-switching devices). The results
of the comparison are given in Table III. the current path during the boost “ON” time. This makes the
According to the results, the proposed circuit has realized a proposed circuit have comparable conduction loss performance
good balance between the number of components, switching with the two-stage solution [6] or basic single-stage ac–dc con-
loss, and the conduction loss. First, intermediate dc-link ca- verter [14]–[16]. The proposed topology has reverse recovery
pacitor is eliminated. Second, although more active switches loss during the switching transient. According to the former
are required for the proposed circuit, but only a small LC cir- analysis, the switching loss on D2 −D5 can be small since the
cuit is required to realize soft switching. Furthermore, the con- reverse block voltage is half of vC r . Normal voltage-rating diode
duction loss of the converter is lower by using the additional is sufficient. Only for diode D1 , in order to ensure safe opera-
commutation path. Only three diodes and one IGBT exist in tion, a higher rating diode, or small RC snubber may be required.
6810 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 32, NO. 9, SEPTEMBER 2017

TABLE III
PERFORMANCE COMPARISON TABLE

Topology Two-stage ac–dc converters [3], Current-fed single-stage full bridge Converter shown in Fig. 1 Proposed converter
[26]–[27] ac–dc converters [14]–[16]

Requirement of passive 1) Input ac inductor; 1) Input ac Inductor; 1) Input ac Inductor; 1) Input ac Inductor;
components 2) Intermediate dc-link capacitor; 2) Output dc capacitor; 2) Output dc capacitor; 2) Output dc capacitor;
3) Output dc capacitor;
Number of active components 1) Two stages: diode rectifier + 5 1) diode rectifier + 4 switches + 4 1) diode rectifier + 4 switches + 1) diode rectifier + 5 switches +
switch + 5 diodes diodes 8 diodes 9 diodes
Additional components for 1) soft-switching cells for secondary 1) Active clamping circuit to snubber 1) small LC resonant circuit 1) small LC resonant circuit
soft-switching dc–dc stage the L k energy
Conduction loss (switches in the 1) Front stage: 3 1) “Boost on”: 4 1) “Boost on”: 6 1) “Boost on”: 4
path) 2) Secondary stage: 4 2) “Boost off”: 6 2) “Boost off”: 8 2) “Boost off”: 8
Switching loss 1) Front stage: hard switching 1) Soft-switching is difficult to 1) ZCS for IGBTs; 1) ZCS for IGBTs;
2) Secondary stage: ZVS realize; 2) Large diode recovery loss due 2) Low diode recovery loss due to
soft-switching 2) Few applying ZVS to all 1200 V diodes 600 V diodes (except D 1 )
for MOSFET

Unlike the topology shown in Fig. 1, D1 −D4 should all change 2) Diode conduction loss PD x con (x = 1..5), PDinx (x =
to 1200-V diode to guarantee safe operation. In conclusion, the 1..4), PD ox (x = 1..4): The ON-state Diode is also
proposed ac–dc converter is a good candidate circuit for high- modeled as a voltage source vD connected in series with
power IGBT-based application. a resistor rD

PD con = vD x · Iavg + rD x · Irm s 2 . (18)

VII. CONCLUSION
In this paper, a single-phase single-stage ZCS current-fed full- 3) Diode switching loss PD x sw (x = 1..5): The energy loss
bridge ac/dc converter is proposed aiming to IGBT-based high- of one switching period is calculated by multiplying the
power lower cost PFC applications. The benefit of this topol- reverse recovery charge Qr r with reverse block voltage
ogy include: no dc-link capacitor is required; soft switching is vDoff . Assumption is made that Qr r is almost propor-
realized with few components added; the conduction loss is tional with the diode forward current If according to the
comparable with traditional solutions; reverse recovery loss datasheet. If is almost equal to the instant value of iLin
is pretty low since most of the diodes are soft switching or 
turned OFF under half of the dc voltage; the control strategy is PD sw = Qr r (If ) · vDoff · fsw
compatible with that used for traditional PFC converter.
2
A 3-kw prototype is built in the paper to verify the pro- = Qr r (ILin p eak ) · vDoff · fsw . (19)
posed circuit. The results show that the converter can realize π
soft switching for all IGBTs, and the THD is 5.2% at the rated 4) Transformer Loss PTran : The transformer loss includes
operation point. The efficiency is estimated to be around 93% two parts, the core loss and the winding loss. The core loss
to 94%. The circuit has shown its capability of high-power ap- per unit volume PFe tran can be found from the material
plications because of the using of IGBT and ZCS operation. loss chart according to Bm ax in (14). The core loss is given
by multiplying the core volume Ve tran with PFe tran . The
APPENDIX dc resistances of both winding are tested using a dc current
LOSS MODEL FOR COMPONENTS IN PROPOSED source. From [31], how much percentage of ac resistance
AC–DC CIRCUIT increasing under 10-kHz operation is derived. Based on
the ac winding resistance Rtran pri ac and Rtran sec ac , the
A loss model for main components of the proposed ac–dc
winding loss is derived
circuit is given in this appendix. The average power loss is
calculated by integrating the instant energy loss in one line PTran = PTran + PTran
fe cu
period. The precise average current and rms current are extracted
2
from the simulation. = Ve tran PFe tran + Rtran pri ac Ipri rm s
1) IGBT loss PS x (x = 1..5): Only the conduction loss and 2
+ Rtran sec ac Isec rm s . (20)
parasitic output capacitance loss exist. The on-state IGBT
is modeled as a voltage source vce0 connected in series
5) Inductor Loss PInd : The calculation of inductor loss is
with a resistor rc . The OFF-state IGBT is modeled as a similar with the transformer loss. Considering the chang-
output capacitance Coss
ing voltage-second applied to the inductor because of
1 the ac input voltage variation, the instant value of loss
PS sw = Coss vce 2 fsw per unit volume PFe ind is calculate by Improved Gen-
2
eral Steinmetz Equation (iGSE) [32]. The average loss in
PS con = Iavg · vce0 + Irm s 2 · rc . (17) one line period is the integration of instance loss in every
LI et al.: SINGLE-PHASE SINGLE-STAGE ISOLATED ZCS CURRENT-FED FULL-BRIDGE CONVERTER FOR HIGH-POWER AC/DC APPLICATIONS 6811

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6812 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 32, NO. 9, SEPTEMBER 2017

Chushan Li received the B.E.E. degree and Ph.D. Zhifang Cao received the B.A.Sc. degree in elec-
degree in electrical engineering from the Depart- trical engineering from Ryerson University, Toronto,
ment of Electrical Engineering, Zhejiang University, Canada, in 2016.
Hangzhou, China, in 2008 and 2014, respectively. Then she joined Accuenergy Canada Inc, North
From April to September in 2008, he was an in- York, Canada, a company in power metering. Her re-
ternship student with the Power Application Design search interests include the electrical metering, power
Center in National Semiconductor Co. Ltd, Hong electronics, and motor drives.
Kong. From December 2010 to October 2011, he was
a Visiting Scholar with the Freedom Center, North
Carolina State University, Raleigh, NC, USA. From
December 2013 to June 2014, he was a Research As-
sistant in Hong Kong Polytechnic University, Hong Kong. He is currently a
Postdoctoral Fellow in the Department of Electrical and Computer Engineer-
ing, Ryerson University, Toronto, Canada. His research interest includes high
power density power converter design and ac–dc power conversion. Dewei (David) Xu (S’99–M’01) received the B.Sc.,
M.A.Sc., and Ph.D. degrees in electrical engineering
from Tsinghua University, Beijing, China, in 1996,
1998, and 2001, respectively.
Yu Zhang (M’11) was born in Jiangsu Province,
Since 2001, he has been working with Ryerson
China. He received the B.E., M.E., and Ph.D. degrees
University, Toronto, ON, Canada, where he is cur-
in electrical engineering from the Huazhong Uni-
rently a Full Professor. His research interests include
versity of Science and Technology (HUST), Wuhan,
renewable energy systems, high-power converters,
China, in 1992, 1995, and 2005, respectively.
electric motor drives, and advanced digital control
From 1995 to 2002, he was an Engineer with
for power electronics.
power supply applications in Wuhan Telecommuni-
cation Company, China. He is currently an Associate
Professor of power electronics in the School of Elec-
trical and Electronic Engineering, HUST. He was a
Visiting Professor at Ryerson University. His research
interests include power electronics modeling and control, parallel UPSs, and re-
newable energy generation.
Dr. Zhang has developed several power systems, such as modular UPSs, and
achieved five scientific and technology awards and two Chinese Patent Awards.
He is currently a member of the UPS standard committee of China.

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