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Design of High Gain and High Bandwidth Operational Transconductance

Amplifier (OTA)

Article in International Journal of Electronics · July 2021

DOI: 10.1080/00207217.2021.1941291

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INTERNATIONAL JOURNAL OF ELECTRONICS
https://doi.org/10.1080/00207217.2021.1941291

Design of high gain and high bandwidth operational

transconductance amplifier (OTA)
Shikha Soni �a, Vandana Niranjana,b and Ashwni Kumara,b
a
Electronics & Communication Department, IGDTUW Kashmere Gate, New Delhi, India; bDepartment of
Electronics & Communication Engineering, IGDTUW Kashmere Gate, New Delhi, India

ABSTRACT ARTICLE HISTORY

A novel operational transconductance amplifier (OTA) having high Received 10 August 2020
gain and high bandwidth for high-speed analog communication Accepted 22 March 2021
techniques and precision filtering is designed in this paper. The KEYWORDS
designed OTA uses β-multiplier-based current biasing scheme with Beta multiplier (BM); folded
folded cascode amplifier scheme in order to improve the small cascode amplifier (FC); slew
signal models and the DC gain of circuit. The OTA design was rate; unity gain bandwidth;
carried out using TSMC 65 nm CMOS technology using Cadence common mode rejection
Virtuoso tool with 1 V supply voltage and 10 pf capacitive load. The ratio (CMRR)�;
output DC gain was found to be approximately 75.3 dB. In addition,
the unity gain frequency for the designed OTA was found to be
around 200 MHz. Superior common mode rejection ratio, power
supply rejection ratio and slew rates along with compact chip area
and low power are other salient features of the designed OTA. The
designed OTA can be employed in order to design high perfor-
mance analog circuits like data converters, phase-locked loops, etc.

1. Introduction
Operational amplifier (Op-amp) is one of the elementary structural blocks in the domain
of analog and mixed signal designs. These circuits are primarily designed with the
intention of availing very low input offset, quite higher output impedance in order
achiever superior isolation. Higher order output voltage gain, current and impedances
are the characteristic design parameters intended for the desired application. The opera-
tional amplifier has a variety of applications while designing switched capacitor array
circuitries, phase-locked loops (PLL), data converters, current biasing circuits and low-
dropout regulator (LDO), etc. (Briseno Vidrios et al., 2018; Maity & Patra, 2017; Marx et al.,
2018; Sarma et al., 2018; Sutula et al., 2016). Moreover, the escalating demand in today’s
smart technological world with the intention of designing energy-efficient systems
fetches the requirements for designing particularly low-power, high-speed and area-
efficient circuitries (Siddhartha et al., 2010; Yavari & Moosazadeh, 2014,; Abdelfattah
et al., 2015). The supply voltage reduction also results in the decrease in power consump-
tion. Although reduction in supply voltage is not a superior technique since it results in

CONTACT Shikha Soni [email protected] Electronics & Communication Department, IGDTUW Kashmere
Gate, New Delhi, India�
© 2021 Informa UK Limited, trading as Taylor & Francis Group
2 S. SONI ET AL.

degradation of the dynamic range of the designed circuitries and hence they experience
the issues related to limiting slew rate and limited bandwidth.
In order to design high-precision applications, the superior unity-gain bandwidth
(UGBW), high gain, great capacitive loads driving capabilities and higher order slew
rates intended for low-voltage designs are desirables (Maity & Patra, 2015).
Furthermore, these operational amplifiers predominantly experience from problems, for
instance, the short-channel effects responsible for performance degradations (Torfifard &
Bin Aain, 2013; Cao & Wisland, 2010; Ferri & Stornelli, 2007). For this reason, the new low-
power and high-speed design techniques are area of interest for researchers in domain of
analog circuit design. Various research methodologies involving floating gate, multi-
voltage designs and subthreshold device operations have been of great area of research
due to their salient features such as requirement of low power and low operational
voltage. But the subthreshold devices are subjected to pay the cost for speed while
going for low-power designs. Hence with the intention of counterbalancing this trade-
off, the folded cascode schemes, adaptive biasing techniques, were further employed in
analog designs (Stornelli et al., 2017; Ghamsari & Pirmoradian, 2015; Akbari et al., 2018;
Ozaki, 2014).
Furthermore, the current reference circuits are amongst one of the most significant
building blocks in analog circuit designs. These circuits are accountable in order to
determine and evaluate the biasing conditions with the intention of designing a variety
of building blocks. Various works are proposed in order to generate the reference current in
De Vita & Iannaccone, 2007; Yoo & Park, 2007. However, self biased current schemes or β-
multiplier schemes are more preferable owing to their relative ease of system on chip (SoC)
implementations (Chouhan & Halonen, 2016; Osipov & Paul, 2017). Additionally, the
cascode (series combination of common source and common gate topology) amplifier is
extensively used in order to achieve high transconductance and superior gain for designed
operational amplifier. Moreover, the folded cascode scheme is an enhanced version of
normal cascode topology enabling low-power application with superior gain bandwidth.
This paper presents a novel design of operation transconductance amplifier (OTA)
making extensive usage of β-multiplier current biasing technique and folded cascode
amplifier scheme. The rest of the paper is planned as follows. Section 2 in brief
presents the related work in the domain of adaptive current biasing and operational
amplifier designs. Section 3 presents the implementation of novel current biasing
circuit β-multiplier design and folded cascode amplifier for OTA design. Section 4
presents the simulation results and performance parameters analysis performed on
the circuit designed in Section 3. Sections 5 presents the conclusion of the paper.

2. Related work
Various biasing techniques and gain or amplifier stages are used in order to achieve the
optimum and superior result for the designed OTA. The various techniques used result in
improved DC gain, superior slew rate, efficient power supply rejection ratios (PSRR) and
common mode rejection rations (CMRR). These further enable to design amplifiers
intended for low-power, high-speed and area-efficient SoC applications in today’s smart
world. A few of these schemes are presented here in following subsections in order to
make inroads for research in subsequent domain in current times.
 INTERNATIONAL JOURNAL OF ELECTRONICS 3

2.1. Class AB OTA with current adder

Cascode current biasing topology was utilised in order to design current adder circuit as
shown in Figure 1 (Kaur & Pandey, 2014). The current mirror used here was implemented
using N-channel MOSFET. The circuit was designed in order such that all the devices were
working in saturation mode of operation while matching the respective device pairs as
mirror devices were matched with respect to the diode device. The input current gets
copied into respective devices followed by the cascode stage. The device sizes are
matched as shown in Equations (1) and (2). Furthermore, using Kirchhoff’s current law
(KCL) the output current is given by Equation (3).

ðW=LÞ2 ðW=LÞ4
¼ (1)
ðW=LÞ1 ðW=LÞ3

ðW=LÞ5 ðW=LÞ7
¼ (2)
ðW=LÞ6 ðW=LÞ8

I0 ¼ AIin1 þ AIin2 (3)

This circuit was implemented using TSMC 180 nm CMOS process technology with supply
voltage of 1.8 V. This circuit was found to be operating on current range of up to 80 μA. In
this circuit, the output current was found to be varying from 10 μA to 90 μA with respect
to the given input current with fixed current source of 10 μA. The early effect or the
mismatch of channel wavelength may result in current error in this circuit.

Figure 1. Class AB OTA with current adder.

4 S. SONI ET AL.

Figure 2. Super class recycling folded cascode (RFC) OTA.

2.2. Super class recycling folded cascode OTA

An energy-efficient super class-AB based recycling folded cascode (RFC) OTA was pro-
posed in Garde et al., 2018 as shown in Figure 2 in order to overcome the issues related to
degrading current efficiency (CE) resulted in Lopez-Martin et al., 2005. Also, the constant
current source was replaced here by an adaptive bias circuit in order to bias the differ-
ential input pair. This helps in order to set the low static currents simultaneously not
limiting the dynamic currents. The small-signal transconductance, gain bandwidth pro-
duct (GBW) and slew rates are given by Equations (4)–(6), respectively. The extensive use
of an adaptive bias circuit for the given input differential pair enables the improvement in
dynamic current along with the augmented GBW product. Furthermore, in order to
improvise the performance of the circuit the local common mode feedback (LCMFB)
can further be employed at the load of the given input differential pair. This implementa-
tion was carried out using 500 nm CMOS process technology. This circuit was found to be
superior in terms of both GBW productand slew rate with few other overheads. These
overheads can be overcome by improving the current reference circuit further.

Gm ¼ gm1A ðK þ 1Þ (4)

Gm
GBW ¼ (5)
2πCL

2 � K � IB
SR ¼ (6)
CL

where gm1A is transconductance gain of device M1A , CL is the load capacitance and IB is the
bias current.
 INTERNATIONAL JOURNAL OF ELECTRONICS 5

Figure 3. Class AB winner-take-all (WTA) OTA.

2.3. Class AB winner-take-all OTA

The class AB winner-take-all (WTA) OTA was implemented as shown in Figure 3. Here, the
traditional common mode sensing circuit is generally reinstated by novel WTA circuitry.
Here, the inputs contend with in order to set the output, which results in the highest
amongst these types of inputs. Furthermore, this circuit enables the improvisation in
additional current. The generated dynamic current can additionally be improved by
extensive use of LCMFB scheme with the matched resistors R1 and R2. These resistors
further results in superior GBW product too. Furthermore, these resistors can be replaced
by MOS devices operating in linear or triode mode of operation which are more area
efficient and enable the circuit to avail resistance adjustments. The circuit was implemen-
ted using MOSIS 500 nm CMOS technology with N-channel MOSFET and P-channel
MOSFET threshold voltage as approximately 0.67 V and −0.96 V, respectively. The circuit
was found to have around 80-pF capacitive load with slew rate of 92 V/μs with static
power consumption of 120 μW.

2.4. Class AB amplifier with N-type flip voltage follower (FVF)

Another novel class AB amplifier was implemented as shown in Figure 4. In order to
augment the dynamic currents ahead of quiescent current range, adaptive biasing
schemes were evolved. In this circuit, the dynamic biasing needs some additional circuitry
in order to improvise the nonlinearities-related sensitivities, process variations (corner
analysis), and power and area requirements. Moreover, the generated dynamic currents
are further imitated within the circuit in order to get into the load which results in extra
6 S. SONI ET AL.

Figure 4. Class AB amplifier with N-type flip voltage follower (FVF).

power dissipation. This is generally measured in terms of CE which is more precisely

defined as the ratio of the maximum load current to the given input supply current. The
devices employed in voltage follower path are reprocessed in order to drive the capaci-
tances C1 and C2. For large positive values of input differential voltage, improved positive
slew rate is achieved. In the same way, the improvisation in negative slew rate is achieved
by maintaining sufficiently large value of negative input differential voltage. The DC
voltage gain and GBW product can be obtained as in Equations (7)–(9), respectively.
�
Av ¼ 2 � gm8;9 þ α � gm3;6 � Rout (7)
�� �� �
Rout ¼ ro8;9 ��ro3;6 ��ro4;5 (8)
�
2 � gm8;9 þ α � gm3;6
GBW ¼ (9)
2 � π � CL

3. Proposed work
3.1. β-Multiplier current biasing circuit
The β-multiplier current biasing circuit is one of the easiest and straightforward solutions
in order to supply the bias current. The general circuit for β-multiplier current biasing is as
 INTERNATIONAL JOURNAL OF ELECTRONICS 7

Figure 5. β-Multiplier current biasing circuit.

shown in Figure 5. Here, there are two P-channel MOSFET devices, namely Mp1 and Mp2,
two N-channel MOSFET devices, namely Mn1 and Mn2, one resistor R and one reference
current source Iref. By extensively using Kirchhoff’s voltage law (KVL) in the lower loop we
obtain Equation (10).

Vgsn1 Vgsn2 ¼ Iref � R (10)

where Vgsn1 and Vgsn2 are gate voltages of N-channel MOSFET device which are given as in
Equation (11) and (12). Vthn is threshold voltage of N-channel MOSFET device, μn is
mobility of electrons, Cox is the capacitance of the gate oxide, and W and L are the
width and length of the device.
sffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi
2 � Iref
Vgsn1 ¼ Vthn þ (11)
μn � Cox � ðW=LÞn1

sffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi
2 � Iref
Vgsn2 ¼ Vthn þ (12)
μn � Cox � ðW=LÞn2

Equation (10) can further be solved in order to obtain Iref as shown in Equation (13).
wHere, M is multiplication factor which is given as in Equation (14). The transconductance
constant gm is given by Equation (15). Furthermore, since Iref is dependent on resistor
R and sizes of N-channel MOSFET devices. Hence, the temperature coefficient (TC) for Iref is
given as in Equation (16).
8 S. SONI ET AL.

rffiffiffiffi!2
2 1
Iref ¼ � 1 (13)
R2 � μn � Cox � ðW=LÞn1 M

ðW=LÞn2
M¼ (14)
ðW=LÞn1

qffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi 1
gm ¼ 2 � M � μn � Cox � ðW=LÞn1 � Iref ¼ (15)
R

� �
1 @Iref 1 @R 1 @μn
TCjIref ¼ � ¼ 2� � þ � (16)
Iref @T R @T μn @T

As it is clear from Equation (16), the TC is having dependence over resistance. Hence, an
advanced novel circuit is proposed for the β-multiplier current biasing circuit in order to
obtain the temperature compensation voltage which improvises TC value of the designed
reference current for both the stages respectively as shown in Figures 6 and 7. This circuit
is quite useful for lower technology nodes in order to work upon short-channel CMOS
technology processes which result in exceptionally small output impedances. Here a basic
amplifier circuit is inserted in the basic reference current circuit. Stability of the circuit

Figure 6. Proposed β-multiplier current biasing circuit Stage 1.

 INTERNATIONAL JOURNAL OF ELECTRONICS 9

Figure 7. Proposed β-multiplier current biasing circuit Stage 2.

similar to feedback topologies results in the compensation in order to enable the unique
high impedance mode in the reference circuit.

3.2. Folded cascode operational transconductance amplifier (FC-OTA)

The folded cascode amplifier architecture as shown in Figure 8 is a negotiation or trade-off
between the telescopic cascode amplifier and two-stage amplifier. This circuit allows
designers to make use of low supply voltage, with high output voltage swing in conjunc-
tion with the equalisation of input and output common mode levels. Furthermore, this
circuit has operating speed lesser than the telescopic cascode amplifier and its gain is
poorer than for the two stage amplifier. Hence this circuit has characteristic in between
both of these amplifiers. Hence, improvisations in both bandwidth and gain are needed in
order to make these architectures further efficient. However, the cascode structures are
helpful in order to improvise the DC gain of the designed amplifier exclusive of mortifying
its frequency response.
Furthermore, in general the folded-cascode amplifier design consists of an input
differential pair together with two detached individual current arms in order to avail
the differential output. Hence, the output current is produced as the cascode architectural
action of the mirrored input currents. This technique in turn gets rid of the noise
constraints which are primarily generated by the current mirrors. In addition, this enables
a simplified and direct signal flow resulting in the superior operating speeds. Moreover,
the MOSFET devices present in parallel in the various arms are utilised in order to pump in
or out the more current such as the tail current of differential amplifiers. When nodal
voltage when Vp becomes more than Vm, correspondingly action is taken on MOSFET
devices by turning on or off them. This results in the pulling up/down the drain of the
subsequent devices. This further makes the changes the current levels and hence adds to
the output voltage. The maximum current sourced out of the designed OTA or sink in the
OTA can be set by corresponding device parameters. The small signal AC currents are
 10
S. SONI ET AL.

Figure 8. Folded cascode operational transconductance amplifier (FC-OTA).

 INTERNATIONAL JOURNAL OF ELECTRONICS 11

primarily given by Equations (17)–(19). In addition to this, the output voltage and voltage
gain are given by Equation (20) and (21), respectively.
id1 ¼ id2 ¼ gmn � vgs1 ¼ gmn � vgs2 (17)

vp vm ¼ vgs1 vgs2 (18)

gmn �
id1 ¼ � vp vm (19)
2
� �
Rop � Ron
Vout ¼ id � (20)
Rop þ Ron
� �
Vout Rop � Ron
Av ¼ � ¼ gmn � (21)
vp vm Rop þ Ron

The GBW product for the designed folded cascode OTA is given by Equation (22). The
added amplifier results in the drain regulation of circuit. Furthermore, the added source
follower circuits enable the signal amplification with respect to supply or ground at the
inputs of the differential amplifiers. In addition, the frequency-depended gain enhance-
ment and the 3-db cut-off frequency on the output of the designed circuit is given by
Equations (23) and (24), respectively. Let’s the current flowing through the coupling
capacitor (Cc) is much greater than the other subsequent currents, then the output of
the OTA need to get charged. Hence, it is observed that the frequency response obtained
in the designed circuit is going to result in the narrower bandwidth of the added
amplifiers. On condition that the bandwidths are higher than the tradition circuits, the
proposed work is found to be quite useful. Furthermore, the slew rate (the maximum rate
of change of output with respect to time) can be calculated as given by Equation (25) and
substituting the output voltage from Equation (20).
gmn
GBW ¼ (22)
2 � π � Cc

Adc
Aðf Þ ¼ (23)
1 þ i ffc

1
fc ¼ � � (24)
R �R
2�π� Cc RopopþRonon � Aðf Þ

dVout Iout
SR ¼ ¼ (25)
dt CL

4. Results and analysis

The presented work has been implemented using Cadence Virtuoso Tools with TSMC
65 nm CMOS process technology. The simulation was done using Cadence Spectre tool.
12 S. SONI ET AL.

Table 1. Device parameters of operational transconduc-

tance amplifier (OTA).
Device name W/L ratio (aspect ratio)
M0, M2,M3,M4, M5, M6, 3 µ/120 n
M7,M8, M9, M10,, M11, M13 3 µ/120 n
, M14,, M15,M16,M20, M22 3 µ/120 n
M1, M13,, M14,M15, M16, M17, M19, 6 µ/120 n
M21, M12 1.5 µ/120 n

Table 2. Device parameters of generation

biasing circuit.
Device name W/L ratio (aspect ratio)
M0,M1, M2, 6 µ/120 n
M3,M4, M5, 6 µ/120 n
M6, M7,M8 3 µ/120 n

Table 3. Device parameters of differential

amplifier unit.
Device name W/L ratio (aspect ratio)
M0,M1, M4, M5, 3 µ/120 n
M6, M7,M8 3 µ/120 n
M2, M3 6 µ/120 n

Figure 9. AC analysis setup for the proposed β-multiplier biased folded cascode OTA.
 INTERNATIONAL JOURNAL OF ELECTRONICS 13

Tables 1–3 present device parameters for the proposed OTA, current generation biasing
circuit and differential amplifier unit, respectively. Figure 9 shows the AC analysis setup for
the proposed β-multiplier biased folded cascode OTA. Its AC gain response, phase
response is shown in Figure 10. This plot is useful in order to determine the frequency
response of the amplifier, the values of DC gain, the gain margin values and the phase
margin values. Hence, the open loop DC gain of the designed β-multiplier biased folded
cascode OTA is found to be approximately 75.3 dB. Furthermore, the unity gain frequency
for the designed OTA is found to be around 200 MHz. The phase margin achieved at the
unity gain frequency is found to be 138 degrees.
The variation CMRR with respect to the operating frequency is shown in Figure 11.
Maximum value of CMRR obtained is found to be approximately 41 dB. Figures 12 and 13
show the PSRR- and PSRR+, respectively. The maximum values for PSRR- and PSRR+ are
found to be 38 dB and 74 dB, respectively. The zoom-in view for output voltage slewing in
order to measure the slew rate is shown in Figure 14. The operating supply voltage is 1 V
and capacitive load of 10 pf. From simulation results it is obvious that the proposed
design outperforms the other OTA design circuits.
The corner analysis of OTA gain for the proposed circuit was carried out and is shown in
Figures 15–17. In order to make sure and evaluate the desired performance of the
proposed OTA circuit in all the practical and realistic state of affairs for consequent
applications, the proposed circuit should be capable to function in the extreme cold
conditions such as −25°C, normal environmental or room temperature conditions of 25°C
along with the hot and enormously hot conditions at 70°C and 110°C. From the results

Figure 10. AC gain and phase response for the proposed OTA.
14 S. SONI ET AL.

Figure 11. Variation of CMRR for the proposed OTA.

Figure 12. Variation of PSRR– for the proposed OTA.

 INTERNATIONAL JOURNAL OF ELECTRONICS 15

Figure 13. Variation of PSRR+ for the proposed OTA.

presented, it is quite obvious that as the temperature increases, the OTA gain of the
proposed circuit gets lower marginally (within 10%). In addition, the proposed OTA was
found to be the best operating conditions with 1 V of input supply voltage. With the
particular variations in input supply voltage, as presented for 0.9 V and 0.8 V, the OTA gain
for the proposed design was found to be varying accordingly. Furthermore, the perfor-
mance of the designed OTA circuit turns out to be the best at TT process corner (PMOS-
Typical, NMOS-Typical) and therefore found to be mortifying to some extent in terms of
OTA gain as we move towards SS, SF and FF (PMOS-Fast, NMOS-Fast) process corners.
From the PVT analysis-based simulations conducted for the proposed OTA circuit, it can
be easily verified that the OTA gain is reasonably robust or having trivial variations
corresponded to all the discussed variations of process corners, input supply voltages
and temperature.
Furthermore, layout work for the proposed OTA was carried out using TSMC 65 nm
CMOS process technology using Virtuoso Layout Editor in Cadence Custom IC Design
Tools as shown in Figure 18. The chip area is 396μm2 . Moreover, the parasitic resistances
were brought down with minimising the metal length used during various connections,
using higher order and low-resistance metals and using proper shielding among voltage
carrying lines. The final layout was simulated in order to evaluate the performance and
compared with schematic circuit simulation results as shown in Table 4.
In addition an outline of the characteristic measurement simulation results achieved
for the proposed circuit is compared with existing circuits and presented in Table 5. It is
16 S. SONI ET AL.

Figure 14. Average and nominal slew rates for the proposed OTA.

Figure 15. PVT process corner analysis of gain for the proposed OTA.

obvious from comparison that the proposed OTA provides higher gain, superior band-
width and higher slew rate. Other parameters like both types of PSRR and CMRR are also
improved primarily owing to the superior gain of the proposed OTA.
 INTERNATIONAL JOURNAL OF ELECTRONICS 17

Figure 16. PVT supply voltage analysis of gain for the proposed OTA.

Figure 17. PVT temperature analysis of gain for the proposed OTA.

5. Conclusion
A high gain and high bandwidth OTA based on β-multiplier current biasing and improved
folded cascode architecture for high-speed analog communication techniques and pre-
cision filtering has been designed making extensive use of the TSMC 65 nm CMOS process
technology in Cadence Virtuoso tools. The use of β-multiplier-based current biasing
scheme results in the enhanced small signal and TC performances of the biasing network
for designed OTA. Furthermore, the folded cascode architecture results in enhanced DC
gain, bandwidth and CMRR and slew rate as well as compact area and low-power
dissipation for the designed OTA. Hence, the designed OTA can be used in high gain
and high bandwidth analog circuit designs.
18 S. SONI ET AL.

Figure 18. Layout for the proposed OTA.

Table 5. Comparison of schematic vs layout simulation results.

Performance parameters Schematic simulation Layout simulation
DC gain (dB) 75.3 61.8
Unity gain bandwidth (MHz) 200 190.25
CMRR (dB) 41 35.75
PSRR+ (dB) 38 32.3
PSRR– (dB) 74 62.75
Slew rate (V/us) 620 560

Table 5. Comparison of the proposed OTA circuit with existing OTA circuits.
Performance OTA (Abdelfattah OTA (Cabebe OTA (Veldandi & OTA (Woo & Proposed
parameters et al., 2015) et al., 2013) Ahamed, 2018) Yang, 2020) OTA
Supply voltage (V) 0.5 0.5 0.5 0.25 1
Technology 65 nm CMOS 65 nm CMOS 65 nm CMOS 65 nm CMOS 65 nm
CMOS
Capacitive load 3 3 2 15 10
(pF)
DC gain (dB) 46 41.5 43.5 74.3 75.3
Unity gain 38 2.1 4.1 0.0105 200
bandwidth
(MHz)
CMRR (dB) 35 NA NA 62.5 41
PSRR+ (dB) NA NA NA 38 38
PSRR– (dB) NA NA NA NA 74
Slew rate (V/us) 43 NA 2.06 0.002 620
Power 182 150 3.27 0.026 129
consumption
(μW)
 INTERNATIONAL JOURNAL OF ELECTRONICS 19

Disclosure statement
�
No potential conflict of interest was reported by the author(s).

ORCID

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