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fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/TIE.2017.2782239, IEEE
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High Step-Up DC-DC Converter with Active

Switched-Inductor and Passive Switched-
Capacitor Networks
Marcos Antonio Salvador, Telles Brunelli Lazzarin, Member, IEEE, and
Roberto Francisco Coelho, Member, IEEE

 In this context, isolated dc-dc converters can be identified

Abstract— High gain voltage conversion is a feature as natural topologies to provide high voltage gain by the
required for several applications, especially for power adjustment of the transformer turn ratio [3], [4]. However, in
processing of low voltage renewable sources in grid- these converters the transformer leakage inductance can
connected systems. In this scope, the presented paper
proposes a novel transformerless high gain step-up dc-dc
produce voltage spikes across the switches, requiring the
converter based on an active switched-inductor (ASL) and employment of energy regenerating techniques to clamp the
a passive switched-capacitor (PSC or SU2C) networks. voltage and recycle the energy [5], [6], which increase the cost
The main advantages of the proposed converter are the and the complexity and reduce the converter efficiency.
high voltage gain (>10), the reduced voltage stresses Conversely, the utilization of non-isolated high step-up dc-
across the switches and the reduced number of dc converters has been extensively addressed in several
components when compared to topologies that provide
the same voltage gain using similar principles. The
applications involving low-power renewable energy sources,
detailed analysis of the proposed converter and a because of their simplicity, size, cost and good efficiency
comparison considering other topologies previously when compared to isolated topologies [3], [4], [7].
published in the literature are also presented in this High step-up non-isolated dc-dc converters are frequently
manuscript. In order to verify the proposed converter classified as coupled inductor and non-coupled inductor types.
performance, a prototype has been built for a power of In coupled inductor type converters, the high voltage gain can
200 W, input and output voltages of 20 and 260 V,
respectively, and switching frequency of 50 kHz.
be achieved by the adjustment of the coupled inductor turns
Experimental results validate the effectiveness of the ratio. In this case the leakage inductance may cause voltage
theoretical analysis proving the satisfactory converter spikes across the switches, like in isolated converters [8], [9].
performance, which peak efficiency is around 95.5%. Therefore, the employment of techniques to clamp or recycle
[9]-[12] the energy in order to improve the efficiency is
Index Terms— Active switched-inductor, gain cell, high
necessary, but the complexity of the topology is increased.
step-up dc-dc converters, transformerless.
Non-coupled inductor type converters are based on the use
I. INTRODUCTION of a Boost converter in association with cascaded converters
[13]-[15] or voltage multipliers (gain cells) [16], [17], as
I N order to achieve high output voltage levels from low
voltage sources, high voltage gain dc-dc converters are
employed. Theoretically, the conventional dc-dc Boost
switched-inductor and/or switched-capacitor cells [18]. This
type of converter is able to provide high voltage gain, but its
efficiency can be deteriorated due to the large number of
converter appears as a suitable candidate to these applications. components, mainly when several voltage multiplier stages are
Nevertheless, when its operating duty cycle approaches to the employed [19].
unity, its voltage gain and its efficiency are drastically reduced Based on this idea, the symmetrical hybrid switched-
due to the increase on the conduction losses. In addition, high inductor converter (SH-SLC) proposed by [20] employs an
gain implies high output voltages and requires the use of high active switched-inductor network (ASL) [21] and a passive
voltage switches, whose electrical parameters further increases switched-inductor (PSL) [18]. During the switch-on period the
the conduction and switching losses [1], [2]. converter charges four inductors in parallel (there are six
power devices on the current flow path in this time interval)
Manuscript received August 13, 2017; revised September 19, 2027;
accepted November 20, 2017. This work was supported by CAPES, and discharges them in series during the switch-off period
CNPq, Federal University of Santa Catarina, and Power Electronics (there are three power devices on the current flow path in this
Institute. time interval). Despite the large component count, especially
The authors are with the Power Electronics Institute (INEP),
Department of Electrical and Electronics Engineering, Federal diodes (seven of them), the converter provides a high step-up
University of Santa Catarina, Florianopolis, Brazil (e-mail: gain and enough efficiency (nearly 92%) at the rated power.
[Link]@[Link]; telles@[Link]; roberto@[Link]).

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In this paper a novel non-coupled high step-up dc-dc

converter is presented, combining a passive switched-
capacitor (PSC) network, also named by step-up 2 cell (SU2C)
[18], with an active switched-inductor network (ASL) [21],
which results in the active switched-inductor step-up 2 cell
(ASL-SU2C) converter.
Although both converters, SH-SLC [20] and ASL-SU2C,
present the same static gain, the ASL-SU2C has some ad-
vantages: 1) it uses lower count of switches devices (five
diodes less); 2) there are just two power switches on the cur-
rent flow path during the both topological states; 3) the
voltage stresses on the active switches are lower and; 4) the Fig. 2. Proposed ASL-SU2C converter.
structure can achieve a better efficiency, as it will be
confirmed by experimental results.

II. ASL-SU2C TOPOLOGICAL DERIVATION

The active switched inductor (ASL) network, depicted in
Fig. 1 (a), is composed of two switches (S1 and S2) and two
inductors (L1 and L2). These inductors are charged in parallel
connection when the switches are turned on and discharged in
series connection when the switches are turned off [21].
The switched capacitor SU2C, shown in Fig. 1 (b), is an
option to increase the voltage gain of step-up converters,
without increasing the voltage stresses on the switches. This
cell consists of two diodes (D1 and D2) and capacitors (C1 and
C2), that are charged in parallel when the diodes are conducing
and discharged in series when they are blocked [18].
Combining the ASL network with the SU2C cell and a low
frequency output LC filter, the proposed converter presented
in Fig. 2 can be derived, in which the diodes operate
complementary to the switches.
L1 C1

S1 S2 D2 D1

L2 C2
(a) (b)
Fig. 1. (a) ASL network [21], (b) SU2C cell [18].

III. ASL-SU2C PROPOSED CONVERTER OPERATION

PRINCIPLE AND THEORETICAL ANALYSIS
The topological stages related to the ASL-SU2C converter
with ideal components are illustrated in Fig. 3, while Fig. 4
shows some typical waveforms obtained during its operation
Fig. 3. Topological stages: (a) Switches on, (b) Switches off, and (c)
in continuous conduction mode (CCM) and in discontinuous
Switches off in DCM operation.
conduction mode (DCM). In the next subsection the operation
principle and the theoretical analysis are detailed. source Vin, the capacitors C1 and C2 are discharged in
series, whereas the diodes D1 and D2 are blocked. The
A. CCM Operation load is fed by source and by the energy previously stored
The ASL-SU2C has two operating stages at CCM in the capacitors C1 and C2. The voltage across the
operation, defined as stage 1 and 2, respectively described by inductors are expressed as
the topological stages presented in Fig. 3 (a) and (b). VL1  VL2  Vin , (1)
 Stage 1 (t0 < t < t1): in this first stage the switches S1 and
and
S2 are simultaneously turned on. During this time interval
VLo  Vin  2VC  Vo . (2)
the inductors L1 and L2 are charged in parallel from the

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 Stage 2 (t1 < t < t2): with the simultaneous blocking of the v g1,g 2 v g1,g 2
switches, the diodes (D1 and D2) are turned on. The 1 1

inductors L1 and L2 are series connected with the voltage 0 0

source Vin and provide energy to charge the capacitors C1 t t
i L1, L 2 i L1, L 2
and C2, connected in parallel, and to the output load. The
voltage across the inductors can be expressed as t t
V  VC i Lo i Lo
VL1  VL2  in , (3)
2 i in t i in t
and
VLo  VC  Vo . (4) t t
By using the volt-second balance principle on the inductors, v S1, S 2 3Vin +Vo
v S1, S 2 3Vin +Vo
4 4 Vin
(5) can be obtained from (1) and (3), and (6) from (2) and (4).
v D1, D 2 3Vin +Vo t v D1, D 2 3Vin +Vo t
 V V  Vo -Vin
VL1  VL2  Vin D   in C  1  D   0
2 2
(5) 2
 2  t t
t0 t1 t2 t0 t1 t 2 t3
V Lo  Vin  2VC  Vo  D  VC  Vo  1  D   0 (6) DTs (1- D )Ts DTs D xT s
(a) Ts (b) Ts
Solving (6), an expression for the voltage (VC) across the
Fig. 4. Typical waveforms. (a) CCM, (b) DCM.
capacitors C1 and C2, can be derived:
V V D Combining (9) and (11), the quantity Dx, concerning the
VC  o in . (7)
1 D time interval in which the inductors currents decrease to zero,
Replacing (7) in (5), the ideal converter voltage gain in is expressed as
CCM is obtained: 2Vin D
Dx  . (14)
V 1  3D VC  Vin
M CCM  o  . (8)
Vin 1  D Now, associating (10), (12) and (14) VC can be obtained:
1
B. DCM Operation VC  Vin  Vo  . (15)
The ideal static gain in DCM operation can be obtained by 2
including the third operation stage, depicted in Fig. 3 (c), in Substituting (15) into (14), Dx can be rewritten as
the analysis. 4Vin D
Dx  . (16)
 Stage 1 (t0 < t < t1): this operation stage is illustrated in Vo  Vin
the Fig. 3 (a). The voltages across the inductors are The average current through the diodes D1 and D2 is equal
described by (1) and (2), while their maximum current to the output current Io, wherein their peak currents IDp are
values (ILp or ILop) are calculated by adding their ripples expressed by (18), thus:
to their respective minimum values (IL(min) or ILo(min)): D V
V D I o  I Dp x  o , (17)
I Lp  I L1 p  I L 2 p  in  I L (min) , (9) 2 Ro
fS L and
and I Lp  I Lop
2V D I Dp  I D1 p  I D 2 p  . (18)
I Lop  in  I Lo (min) . (10) 2
f S Lo Combining (9), (10), (17) and (18), (19) can be derived.
 Stage 2 (t1 < t < t2): this stage is depicted in Fig. 3 (b). Vo 2Vin 2 D 2
The voltage across the inductors is described by (3) and Io   . (19)
Ro f S Leq (Vo  Vin )
(4) and the currents through them by (11) and (12).
(V  Vc ) Dx Solving (19), the ideal voltage gain in DCM is obtained.
I L (min)  I L1(min)  I L 2(min)  in  I Lp (11)
2 fS L
Vo 1 1 8D 2
(V  Vo ) Dx M DCM    1 . (20)
I Lo (min)  c  I Lop (12) Vin 2 2 K
f S Lo
Similarly to [1], the dimensionless parameter K and the
 Stage 3 (t2 < t < t3): during this time interval the current equivalent inductance Leq are defined as:
across the diodes becomes null while the switches S1 and f S Leq
S2 are still turned off, since all power semiconductors are K , (21)
blocked. The current that flows through L1 and L2 is Ro
constant, as shown in Figs. 3 (c) and 4 (b). In addition, and
the current through Lo is described by 2 Lo L
Leq  . (22)
I Lo(min)   I L(min) . (13) 2 L  Lo

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C. External Characteristic of the Converter

The proposed converter can operate in the boundary
conduction mode (BCM), in which the voltage gain in CCM
and in DCM is the same. Hence, equaling (8) and (20), the
critical value of K is determined:
D(1  D)2
Kcrit  . (23)
2(1  3D)
The plot of Kcrit versus D illustrated in Fig. 5 evidences that
for K>Kcrit the converter operates in CCM, otherwise, in
DCM. In addition, from (19) it is possible to obtain the critical
load resistance, written in (24), and to define a dimensionless
parameter γ, according to (25), which is used to represent the
parameterized converter output current.
2(1  3D) f S Leq
Rcrit  (24) Fig. 5. Boundary conditions for the converter operation.
D(1  D)2
I o Leq f S
 (25)
Vin
Substituting (25) in (19), the critical value of γ is found, as
in (26). Furthermore, isolating the duty cycle D in (8) and
replacing the result in (26), the critical value of γ is expressed
as a function of the static gain, in accordance with (27), and
depicted in Fig. 6, in which the dashed line shows the
boundary of CCM and DCM operation.
2D2
 crit  (26)
M 1
2( M  1)
 crit  (27)
( M  3) 2

D. Influence of Parasitic Parameters in the Voltage Gain

In order to verify the impact of the parasitic parameters in
the converter gain, some of these parameters were included,
resulting in non-ideal converter model. In this analysis it is Fig. 6. External characteristic of the proposed converter.
considered the inductors windings resistances (rLo and
TABLE I
rL1=rL2=rL), the power switches on resistances (rS1=rS2=rS), the PARASITIC PARAMETERS OF THE COMPONENTS
diodes forward voltages (VF1=VF2=VF), their respective on VF rD rL rS rC rLo
resistances (rD1=rD2=rD) and the capacitors series equivalent
1.7 V 83 mΩ 46 mΩ 15 mΩ 10 mΩ 412 mΩ
resistances (rC1=rC2=rC). The numerical values
assumed/measured for these quantities are presented in
Table I, while the converter model including parasitic
parameters is show in Fig. 7.
After the parasitic parameters are included, a new equation
to describe the converter static gain can be derived, in
accordance with (28). A graphical comparison among (8), (28)
and some experimental points obtained from a prototype
described in section V are plotted in Fig. 8. It is noted that the
experimental results are properly represented by the models,
mainly when the converter parasitic parameters are regarded.
Upon to Fig. 8, one can verify that the converter static gain
approaches to 16 for duty cycles close to 0,8, evidencing the Fig. 7. Proposed ASL-SU2C Converter with parasitic parameters.
high step-up characteristic of the proposed converter. In 1  3D 2VF
addition, the miniature view in the Fig. 8 shows the static gain 
1 D Vin
curves to full duty cycle range, demonstrating the relationship M 'CCM  (28)
rL 2(1  D ) 2 rS 8D rD  rC D 2 rLo
between ideal behavior and real limitations of the converter. 1   
Ro (1  D ) 2 Ro (1  D ) 2 Ro (1  D ) Ro

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inductor iLo during the time interval DTs. Therefore:

Po D(1  D)
C  C1  C2  . (36)
Vin f S (1  3D)VC
The average voltage VC across the capacitors was already
presented in (7). Nevertheless, substituting (8) in (7) it may be
rewritten as a function of the input voltage:
V (1  D)
VC  VC1  VC 2  in . (37)
1 D
As it is evidenced in Fig. 3 (a), the current in the capacitors
C1 and C2 is equal to the output inductor current during the
first topological state. In the second topological state each
capacitor assumes half of the difference between the currents
in the input and output inductors. Consequently, the root-
mean-square (rms) value related to the current in these
Fig. 8. Static gain curves related to the ASL-SU2C. capacitors is expressed as:
E. Voltage and Current Stresses on the Components Po (1  D) D
I C ,rms  . (38)
Considering the converter operating in CCM, a complete Vin (1  3D) 1  D
analysis may be accomplished to obtain the key equations that The average voltage VCo across the output capacitor is the
describe the voltage and the current stresses across the own converter output voltage. Considering that all AC
components. components of iLo flows through Co, their voltage ripple and
Firstly, the voltage across the output inductor can be the capacitance can be obtained by (39), whereas its rms
described by (29), by replacing (15) in (2). Thus, the current can be calculated from (40).
inductance Lo and hence the current ripple ΔILo can be easily Vin D
obtained: Co  (39)
4 Lo VCo f S 2
di
vLo  2Vin  Lo Lo , (29) iLo 2
dt I Co ,rms  (40)
2V D 12
Lo  in . (30)
I Lo f S To select the diodes D1 and D2, the reverse voltage
Once the average current in the output capacitor Co is null (VD1=VD2 = VD) applied when they are blocked (stage 1) and
in steady-state, the output inductor average current ILo can be their average current values (ID1,ave = ID2,ave = ID,ave) can be
considered equal to the load average current Io, thus: expressed respectively by (41) and (42), since the current
across the diodes is equally divided, as shown in Fig. 3 (b).
1 D
I Lo  I o  I in , (31) 2Vin
1  3D VD  (41)
1 D
P (1  D )
I Lo  o . (32) P (1  D)
Vin (1  3D) I D ,ave  o (42)
Vin (1  3D)
A similar procedure can be employed to determine the
inductances L=L1=L2, but using (1) to describe the voltages The voltage stresses (VS1=VS2 =VS) across the power
applied to them during the interval DTs. Therefore: switches when they are blocked (stage 2) and their rms current
V D values (IS1,rms = IS2,rms= IS,rms) are respectively expressed by (43)
L  L1  L2  in . (33) and (44), wherein VS is derived by the difference between Vin
I L f S
and the input inductor voltage. Additionally, the rms current
From Figure 3 (a) and (b) it is possible to define an equation values can be calculated considering that the current flows
to calculate the input current, as in (34). Thus, the mean values through the switches only during the first topological stage.
of the currents in the input inductors can be obtained by During this time interval this current corresponds to the sum
isolating IL, as in (35), and substituting (32) in the previously of the input and output inductors currents.
found result. V
VS  in (43)
Iin  (2I L  I Lo ) D  I L (1  D) (34) 1 D
Po (1  D) 2 Po D
I L  I L1  I L 2  (35) I S ,rms  (44)
Vin (1  3D ) Vin (1  3D )
The voltage ripple on the capacitors C=C1=C2 as well as
their respective capacitances, can be defined considering that F. Design Considerations
the current through them is equal to the current of the output Some important considerations regarding the passive

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components (inductors and capacitors) used to increase the

gain of the proposed converter and the non-idealities referring
the two active switches are discussed as follows:
 Taking into account possible parametric differences
between the two inductors, the switches may be
subjected to a peak voltage higher than the ideal values.
However, the converter proposed by [20], based on the
employment of an ASL network, also presents the same
phenomenon, requiring the clamping technique detailed
by the authors in [22].
 Since both input inductors of the proposed topology are
designed with the same inductance value and are
subjected to the same operation conditions, they could be
integrated into one magnetic core to improve the
converter power density [20]. Nevertheless, coupling
imperfections (as leakage and non-unitary turns ratio)
Fig. 9. Voltage gain comparison.
may result in effects similar to the that caused by
parametric differences between the two inductors.
 Regarding to the capacitors used in the proposed
converter, it can be observed that their average voltage
are equal, i.e., VC=VC1=VC2=Vin+Vo/2, whereas the
average voltage on Co is higher (VCo =Vo). Since these
capacitors are placed in parallel, different voltage levels
can cause high peaks of current. In the proposed
converter this phenomenon is smoothed because there is
always an inductor in the current path, which allows the
usage of non-high capacitance values. Moreover, it
should be highlighted that large parametric differences
between the capacitors C1 and C2 may also result in peak
currents across the diodes D1 and D2, since when the
switches are turned off, these capacitors are connected in
parallel. This is an intrinsic characteristic of switched
capacitors circuits and can be smoothed by increasing the Fig. 10. Normalized switches voltage stress in the compared converters
capacitors values in order to reduce their voltage ripple. Boost [25], converter I [21] and SL-Boost [18]. The static gain
However, considering the little tolerance (5%) of the film and the normalized equations that describe the voltage stresses
capacitors used in the proposed converter, non-high across the semiconductors for these converters are
capacitance differences are expected and the peak current summarized in Table II and graphically represented in Fig. 9
across the diodes will not be so high to cause relevant and Fig. 10, respectively. Furthermore, the number of
problems. components applied in each of the compared converters also is
 Concerning the active switches, there are two main shown in Table II. As shows Fig. 9 and Table II, the compared
challenges to be considered. Firstly, according to [22], a converters are ordered from the higher to the lower voltage
resonant effect may appear due to the loop containing gain, and grouped in pairs, due to static gain equivalence. The
Vin, L1, L2 and the parasitic capacitances CS1 and CS2, converters [23], [25] and [18] can respectively provide the
when the switches are turned off. In second, resonances same static gain of converter III [21], [24] and converter I
may also occur due to synchronism imperfections on the
[21], only using one active switch and thus a single circuit
driving signals, since it results in differences between the
driver.
currents through the inductors L1 and L2. These both
When the number of components is considered, the HBC
drawbacks associated to the ASL network can result high
voltage stresses on the converter switches. Nevertheless, [23] is an interesting topology, especially because of its
clamping techniques, as it is proposed by [22], may be equivalence with the Converter III [21] in terms of static gain
employed to minimize this problem. and voltage stress on the semiconductors. When compared
with the proposed converter, the HBC [23] has an advantage
IV. COMPARISON ANALYSIS related to the number of active switches and inductors,
This section compares the proposed topology with non- however the proposed converter uses fewer diodes and
isolated and non-coupled structures that also provide high capacitors and can provide higher voltage gain for duty cycles
voltage gains, as such as the SH-SLC [20], Converter III [21], higher than 0.5, according to Figure 9. The proposed converter
hybrid boost converter (HBC) [23], Converter [24], SC- also presents the lower voltage stress on the active switches to
any voltage gain higher than five, like is shown in Figure 10.

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TABLE II
COMPARISON OF THE PROPOSED TOPOLOGY WITH NON-COUPLED MAGNETICS STRUCTURES
Diodes Diodes in P-SL Diodes Diodes Constant
Gain Switches Switches Diodes Capacitors Inductors
Converters output Cell (vDa,b /Vin) SC Cell VL Cell input
(MCCM) (vs /Vin) count count count count
(vDo /Vin) and (vDc /Vin) (vD /Vin) (vD /Vin) current
1  3D
Proposed M 2M
ASL-SU2C 1 D – – – 2 2 3 3 No
1  3D 1  3D

1  3D
M 1 M 1
SH-SLC [20] 1 D M1 and 1 – – 2 7 1 4 No
2 4

3 D M 1 M 1
Converter III [21] M1 – – 2 3 3 2 No
1 D 2 2
3 D M 1 M 1
HBC [23] – – – 1 4 4 1 No
1 D 2 2
2 M 1 M 1
Converter [24] – – – 2 3 3 2 Yes
1 D 2 2
2 M M M
SC-Boost [25] – – 1 3 3 1 Yes
1 D 2 2 2
1 D M 1
Converter I [21] M1 – – – 2 1 1 2 No
1 D 2
1 D M 1
SL-Boost [18] M M and 1 – – 1 4 1 2 Yes
1 D 2

The recently published converter [24] has input current Moreover, Table II and Fig. 10 reveal that the proposed
characteristic and requires the same number of components of converter presents the highest voltage gain and the lowest
the proposed ASL-SU2C, however the static gain provided by voltage stresses on the active switches for any duty cycle
[24] is lower for any duty cycle higher than 0.333, and their higher than 0.5. This fact allows the use of switches with
active switches are subjected to higher voltage stresses for any reduced on resistances, decreasing the conduction losses.
static gain higher than five. Despite the comparison analysis has only included similar
The converters [21] and [18] provide the lower static gain structures to the proposed converter, there are other recent
among the compared converters, and their active switches are topologies based on coupled inductors and interleaving
subjected to the higher voltage stresses, especially [18], as per technique [27], [28] that can achieve high step up gain and
Fig. 10. In accordance with [26], the converter [21] may be also present input current sharing. Such converters (and other
extended to a bidirectional topology. In this case, the output based on the same principles) have their voltage gain adjusted
diode must be replaced by an active switch, resulting in a by the turns ratio and can provide low input current ripple.
simple bidirectional structure. However, they have more complex structures and analysis
Additionally, only the proposed converter presents an design, with a high components count.
inductor in the place of the output diode. Even representing an
increase of cost and size, the output inductor adds a current V. DESIGN EXAMPLE AND VERIFICATION RESULTS
source characteristic to converter output. In order to verify the experimental performance of the
It is important to emphasize that some output diodes are proposed converter, the prototype shown in Fig. 11 was built
subjected to expressive levels of blocking voltage. The considering the specifications listed in Table III. Since a
normalized voltage stresses on the diodes (VD/Vin) are voltage source of 20 V is applied in converter input, its ability
presented in Table II, considering the topological derivation of of providing a high voltage gain (M=13) is verified by
each converter. Moreover, in the proposed converter, HBC defining an output voltage of 260 V, which implies in an
[23], Converter [24] and SC-Boost [25], the voltage stresses operating duty cycle of 0.75, according to (8). Thus, using
are equally divided by the diodes that compose the structure, (37), (41) and (43), the following results are obtained:
and, depending on the applied gain cell, each compared VC1,ave  VC 2,ave  140 V,
converter may require additional diodes.
A special comparison analysis can be evaluated between the VD1,max  VD 2,max  160 V, (45)
ASL-SU2C and SH-SLC [20] since both topologies are VS1,max  VS 2,max  80 V.
featured by the same static gain function, reaching the higher Similarly, the substitution of the specifications (Table III) in
values among the compared converters, according to Table II (38), (42) and (44) allows obtaining:
and Fig. 9. Although the proposed converter presents two
IC1,rms  IC 2,rms  1.332 A,
additional film capacitors (non-high capacitance), its total
number of components is reduced when compared to the SH- I D1,ave  I D 2,ave  0.769 A, (46)
SLC [20] (one inductor and five diodes less). I S1,rms  I S 2,rms  5.329 A.

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This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/TIE.2017.2782239, IEEE
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Equations to define the input and output inductances are

presented in (30) and (33), as well as the capacitances of C1 vg1 (30 V/div)
and C2 can be calculated through (36). One more time,
replacing the specifications of Table III in the mentioned
equations their numerical values are found:
vS1
L1  L2  223 H,
(40 V/div)

vg 2
Lo  2.34 mH, (47)
(30 V/div)

C1  C2  1 F.
TABLE III vS 2 (40 V/div)
SPECIFICATIONS AND COMPONENTS OF THE CONVERTER (10 ms/div)
Input voltage (Vin) 20 V
Output voltage (Vo) 260 V
Rated power (Po) 200 W
Fig. 12. Experimental gate-source signals (vg1 and vg2) and drain-
Switching frequency (fs) 50 kHz
source voltages (vS1 and vS2).
Input inductors current ripple 25%
Output inductor current ripple 33%
Output capacitor voltage ripple 8%
Commercial circuit drivers DRO100S25A
Vin(10 V/div)
S1 and S2 IRFB4321PbF
D1 and D2 SDT10S60
223 µH - Thorton IP12R
L1 and L2 iin (10 A/div)
(core NEE 30/15/14)
2.34 mH - Thorton IP12R
Lo
(core NEE 28/10/11)
C1, C2 and Co 1 µF (film)
Vo(100 V/div)

C1 , C 2 Io (1 A/div)
(10 ms/div)

L2

Lo Fig. 13. Experimental input and output voltages and currents.

Co
D1 , D 2
S1 , S 2

L1

Fig. 11. Prototype lab bench photograph (100 mm x 100 mm x 50 mm).

Based on the previously presented design example, the
proper selection of the converter components was
accomplished (Table III) and practical experimentation
realized. Some of the obtained experimental waveforms are Fig. 14. Experimental capacitors voltages (vC1 and vC2) and diodes
displayed in Figs. 12-15, considering the open loop voltages (vD1 and vD2) waveforms.
verification near to the nominal power (Po = 200 W) with
fixed input voltage (20 V). Fig. 12 shows the switching signals Vin(20 V/div)
and also highlights the low voltage (80 V) across the switches,
as it was predicted by (43). Vo (100 V/div)
The measured input and output voltages and currents are
shown in Fig. 13, evidencing the high voltage gain.
Furthermore, it may observe that the input current shape is
similar to the theoretical waveform shown in the Fig. 4 (a). iL1 (3 A/div) DiL1@ 1.4 A
The average voltage in the capacitors C1 and C2 is in
agreement with (37), as shown in Fig. 14. Moreover, it is iL 2 (3 A/div) DiL2 @ 1.4 A
noted that the voltages vD1 and vD2 across the diodes were (10 ms/div)

properly predicted by (41).

Figure 15 depicts the input and the output voltages, besides
the current across the input inductors L1 and L2. The measured Fig. 15. Experimental input and output voltage (Vin and Vo) and current
in the input inductors (iL1 and iL2).

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This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/TIE.2017.2782239, IEEE
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values (5.42 A) to the average inductors currents are in

accordance with the theoretical values shown in (47).
Moreover, the measured current ripple related the input
inductors (1.4 A) is established close to the theoretical value
(1.36 A).
Figure 16 shows the experimental efficiency curves,
measured by a Yokogawa power analyzer (WT1800), with an
output voltage of 260 V, over a large range of output power.
An experimental peak efficiency of 96.84% is achieved when
the output power is 150 W and the input voltage is 40 V. In
addition, a peak efficiency of 95.34% is achieved when the
output power is 125 W and input voltage is 20 V. As it is
observed in Fig. 16 and previously highlighted by [20], the Fig. 16. Experimental efficiency curves as function of the output power.
efficiency is increased for high input voltages because the
input current decreases, and thus the conduction losses on TABLE IV
EFFICIENCY ESTIMATED AND LOSS DISTRIBUTIONS
power switches and inductors are also reduced. (Vin = 20 V, Vo = 260 V, Po = 200 W and fs = 50 kHz)
The estimated efficiency and loss distributions considering rparasitic Vmax VF Iave Irms PLoss PLoss
Type
the nominal specifications and selected components are (mΩ) (V) (V) (A) (A) (W) ratio (%)
summarized in Table IV and depicted in Fig. 17. This S1 and S2 15 80 - - 5.329 5.692 48.443
estimation has considered that the power losses on the active D1 and D2 83 160 1.7 0.769 1.538 3 25.616
L1 and L2 46 - - 5.384 5.398 2.744 23.352
switches are composed by conduction and switching losses.
LO 412 - - 0.769 0.773 0.268 2.286
Concerning the diodes and capacitors, only the conduction C1 and C2 10 - - - 1.332
losses were considered, while for the inductors, both core and 0.035 0.303
CO 10 - - - 0.074
copper losses were took into account.
According to the estimated values, the switches losses
present the most significant impact on the converter
efficiency, followed by the diodes and input inductors. It is
important to highlight that the measured converter efficiency
at the rated power is about of 94.27%, while its theoretical
value is 94.45%.

VI. CONCLUSION
This paper has presented a novel non-isolated high voltage
gain dc-dc converter, named by ASL-SU2C. Experimental
Fig. 17. Proportion of Loss; Total Loss ≈ 11.75 W; Efficiency ≈ 94.45%.
results shown that this converter can reach a gain of thirteen
with a duty cycle of 0.75, using a reduced number of
semiconductors in a simple structure, which provides current inductor (ASL) and the step-up 2 cell (SU2C), that are,
flow just in two switches during the switch-on topological respectively, the division of the current through the input
stage and in two diodes during the switch-off topological components and the reduction of the voltage across the
stage. switches.
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0278-0046 (c) 2017 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission. See [Link] for more information.
This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/TIE.2017.2782239, IEEE
Transactions on Industrial Electronics

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