Question Bank with Reference

DEPT:
Electronics & Communication Engineering

SEMESTER: 5th

SUBEJCT
PCCECE503
CODE:
SUBEJCT
VLSI Design
NAME:

Section
Text Book Name, Exercise
Module No. No. (if Chapter No
Author, Publisher Nos.
any)
VLSI Design & EDA Tools –
Angshuman Sarkar,
Module 1 Swapnadip De and Chandan
Kumar Sarkar, Scitech
Publications
VLSI Design & EDA Tools –
Angshuman Sarkar,
Module 2 Swapnadip De and Chandan 10 1,2,3
Kumar Sarkar, Scitech
Publications
VLSI Design & EDA Tools –
Angshuman Sarkar,
Module 3 Swapnadip De and Chandan 5,6,7,8
Kumar Sarkar, Scitech
Publications
VLSI Design & EDA Tools –
Angshuman Sarkar,
Swapnadip De and Chandan 3,15
Kumar Sarkar, Scitech (Angshuman
Publications
Sarkar ),
VLSI Physical Design : From
Module 4 Graph partitioning to timing 3,15(Angshuman Andrew B.
Closure - Andrew B. Kahng , Sarkar ) Kahng
Jens Lienig , Igor L. Markov (Chapter
, Jin Hu Andrew B. Kahng , 2,3,4
Jens Lienig , Igor L. Markov Exercise )
, Jin Hu. – Spinger
Mod 1 Syllabus:
Device Physics & IC Fabrication Steps

MOS device physics and modeling; Wafer processing; oxidation;

epitaxy; Diffusion & Ion implantation; Photolithography; Etching;
Basic n-well process; p-well process; twin tub process; Layout and
stick diagram.

Questions
Define sheet resistance.
Draw the Stick diagram of the below equation and circuit:

Why are mask layouts important in IC fabrication?

Discuss about carrier lifetime and carrier diffusion length.
 Module 2

CO2 : Analog VLSI Circuits

Syllabus : Single stage amplifiers; Differential amplifiers; Active loads; Current mirrors; Current and
voltage references; Switched capacitor circuits.

Textbook : VLSI Design & EDA Tools – Angshuman Sarkar, Swapnadip De and Chandan Kumar Sarkar,
Scitech Publications
Take kn=220μA/V2 ; λ=0.03V-1 , Vth=0.45V
Q4) Using the cascade circuit below, find the output resistance from small signal model in terms of
various device parameters. Neglect body bias effect.
Q7)

Find the small signal output impedance of the above circuit.

Take kn=220μA/V2 ; λ=0.03V-1 , Vth=0.45V; kp=60μA/V2 ; λ=0.03V-1 , Vth=-0.45V
Take kn=220μA/V2 ; λ=0.03V-1 , Vth=0.45V
 Module 3

5.74 VLSI Desigu and EDA

Tools
EXERCISES
1)
Derive the thresholdvoltage for a CMOS inverter.
2)
What are the advantage of CMOS inverter over depletion load inverter.
3)
Why criticalvoltages of an inverter are defined for VTC when slope=-1
4) How we can increase nojse margin of an inverter?
5)
EStimate the dynamic power consumption of a CMOS inverter?
6) How dymamic power Consumption can be reduced for a CMOS inverter?
7)
Locate five distinct regions for CMOS inverter and specify the operating modes of
the MOSFET on those regions of the
VTC.
8) What is ratioed logic? Why it is called ratioed logic?
9) What are the disadvantages of CMOS inverter?
10) Estimate t and t of a CMOS
inverter using R-C model.
11) How rise and fall times are
calculated?
12) Describe two methods of
approximate delay calculations.

REFERENCES
[1] Sung-MO Kang, Yusuf
New York, 1996 Leblebici, CMOS digital integrated circuits, McGrew Hill,
[2] LJ. Herbst, Integrated
circuit Engineering, Oxford University press,
(3) Martin, K. Digital New York
2000 Integrated circuit design, Oxford University press, New
York,
[4] Dougals A. Pucknell,
Kamran Eshraghian, Basic VLSIdesign,
[5) J.M. Rabaey, Digital Prentice Hall, 1984
1996. Integrated Circuits, Prentice-Hall, Upper Saddle
River, N).
 Static Combinational Digital Logic Design 6.69

EXERCISE
1. Design the 4:1 multiplexer circuit using TG
switches.
2. Design a 4:1 multiplexer using three 2:1 TG multiplexers.
3 Consider the 2-input XOR function.
a) Design an XOR gate using a 4:1 multiplexer.
b) Modify the circuit in a) to produce a 2-input XNOR
4 Design a CMOS logic gate for the function f= a.b+a.c+b.d
5. Design a NAND3 gate using an 8:1 multiplexer
6. Design a NOR3 gate using an 8:1 multiplexer as a basis.
7. Four nMOSs are used as pass transistor. The input voltage is set to Vin=VDp=5V
and it is given that V.n= 0.75V. Suppose that the signals are initially at (1,1,0,0)
and are then switched to (0,1,1,1). Find the value of Vout.
Design a tri-state circuit that is in a high-impedance state when the control signal
T=1, and acts as a non-inverting buffer when T=0.

9. Afull adder accepts inputs a,b and c and calculates the sum bit
S=a b c

Use the multiplexer based gates to design a circuit with this output
10. Implement the following expression in a full static CMOS logic fashio.a using no
more than 10transistors:

Y=(A.B)+(A.C.E)+(D.E)+(D.C.B)
11. What is the logicfunction implemented by the CMOS transistor network given in
figure below?
 6.70 VLSI Design and EDA Tools

12) Implement the logic function f=xy+xz using CMOS logic with as few transistor as
possible.
 Dynamic and Advanced Cmos Logic Circuits 7.57

Now we will see how the quantity f

Let us consider the time
provides increase in speed.
derivative as
df, dx dx
dt dt dt
note that

dx dx
dt dt
thus
dx
=2
dt dt

As x increases X decreases.

Notice that the rate of change of fx is approximately twice than that of a single variable.
Translated into logic terms, this means the switching speed is almost twice as fast as
can be obtained from a single rail circuit.

The disadvantages of dual rail logic are 1) increase incomplexity and wiring overhead.
However, speed adavanatge makes them worthy.

EXERCISES
1) What are the advantages of dynamic logic over static logic?
2) What are the disadvantages of dynamic logic?
3) What is precharge-evaluate logic?
Implement a 2 input NOR gate using precharge evaluate logic.
Why dynamic logic cannot be cascaded directly?
probiem of dynamic logic?
6) How dominologic solves the cascading
7.58 VLSI Design and EDA Tools
race?
race? How NORAlogic is not affected by
7) What is signal
preventcharge sharing?
8) What is charge sharing? How to
using MODL.
9) Implement Manchester carry chain
10) Implement a NANDgate
using DCVSL.

REFERENCES
CMOS VLSI Design: A Systems
[1] N. Weste and K. Eshragian, Principles of
Perspective, Appison-Wesley, 1993.
Circuits," IEEE Journal of Solid
2] V. Friedman and S. Liu, "Dynamic Logic CMOS
State Circuits, vol. SC-19, no. 2, pp. 263-266, April 1984.
CMOS Technique
[3] N. Goncalvez and H. De Man, "NORA: A Racefree Dynamic
Circuits, vol. SC-18,
for Pipelined Logic Structures," IEEE Journal of Solid State
no. 3, pp.261-266, June 1983.
[4] L. Heller et al., "Cascade Voltage Switch Logic: A Differential CMOS Logic
Family,"Proc. IEEE ISSCC Conference,pp. 16-17, February 1984.
[5) J.M Rabaey, Digital Inegrated circuits, Prerntice Hall, NJ,1996
[6] Ken Martin, Digital Integrated circuits, Prentice hall, NJ, 1996
[7] John. P. Uyemura, CMOS logic circuit desi,n, KLuyer academic press, MA,1999
[8] Randall L. Geiger, Phillip E. Allen, and Noel R. Strader. VLSI Design Techniques
for Analog and DigitalCircuits. McGraw-Hill, Inc., 1990.
[9] Sung-MOKang, Yusuf Leblebici, CMOS digital integrated circuits, McGrew Hill
New York, 1996

[10] LJ. Herbst, Integrated circuit Engineering Oxford University press, New York
 Sequential LogicCircuits 8.37

EXERCISES
1) Draw the circuit diagram of D-type FF using
transmission gate.
2) Differentiate between combinational and sequential circuits.
3) What is the advantage of JK FlipFlop over SR Flipflop?
4) Draw andexplain working of SRlatch using positive logic and negative logic
5) Describe the circuit operation of Master Slave JK Flip Flop.
6) What is bistability principle? What is metastable state?
Draw a clocked CMOS D altch.

8) Why edgetriggered flipflops are prefferd?

 Module 4

Chapter 3 - Angshuman
Sarkar
EXERCISES

1. What do you mean by CMOS PLA?

2. Give thc structurc of a CPLD.
3. What is meant by PAL?
4. What is an FPGA? Give its advantages.
5, What is ASIC?
6. What are different types ofFPGA programming modes?
7. What is Slice, CLB, LUT?
8. What is design hierarchy?
9. Name the domains in Y-chart.
10. What arc the two different kinds of design mcthodologics
provided in a typical dosign flow?
11. What are the features of standard-ccllbascd ASICs?
12. Compare FPGA and CPLD.
13. What arc the advantagcs of cell-bascd dcsign methodology?
14. Whal ure the things the designer delines in the CBlC design?
15. Compare SRAM-based and anti-fused based programming.
16. Whal is the domain and abstraction of a digital design
description?
17. Compare hierarchy, regularity, modularity, and locality in terms
of software and hardwarc.
18. What is an anti-fusc?
19. What arc thc different mcthods of programning for PALs?
20. What are the different levels of design abstraction at physical
design?
21. Mention the challenge in SOC design.
22. What does regularity mean in VLSI?
23. Explain modularity and locality in VLSI.
24. What do you mcan by ASIC?
25. Which 1C's are not considered as ASIC?
26. What are the important features of PLDs?
27. What are the advantages of Cell based ASICs?
28. Mention the advantage of hierarchical design.
29. DilTerentiate between structured design and full-custom design.
30. What is the difference between FPGA and CPLD?
31. Describe the FPGA architccturc.
32. Give a brief description of design flow for an ASIC.
33. Mention the differcnt typcs of gatc array ASICs with thcir
important features.
34. Draw a picture of a PLA programmed to implement fl (x1, x2,
x3)- m (1, 2, 4, 7). The PLA should have the inputs x1, x2, x3,
the product terms Pl, P2, P3, P4, and the outputs fl and f2.
35) Draw a piclure of aPAL. programmed to implement fl (x 1, x2,
x3) = m(1, 2, 4, 7) and fl(xl, x2, x3) =E, m(3, 5, 6, 7). The PLA
should have the inputs x1, x2, x3, the product terms P1, P2, P3, P4,
and the outputs fl and f2,.
Chapter - 2,3,4 Exercise of Andrew B.
Kahng 's Book
Chapter - 2,3,4 Exercise of Andrew B.
Kahng 's Book
 Chapter 15 - Angshuman Sarkar, Book

Pysical Desigu Automation 15.73

SHORT QUESTIONS WITH ANSWERS

1) What is the
disadvantage
Answer: High Order of
of K-L
algorithms?
not applicable to complexity
hyper graphs. O(n), possibility of entrapment to local mininma,

2) Is k-L
algorithm deterministic?
Answer: Yes
3) Is simulated
annealing deterministic?
Answer: No

4) What is the importance of the term "simulated" in simulated annealing

algorithm?
Answer: The algorithm is simulating the different steps occurs during the annealng
process used to temper metals which is a natural pheromenon.
5) What is simulate evolution technique?
Answer: Simulated Evolution is in a class of iterative probabilistic methods for
combinatorial optimization that exploits an analogy between biological evolution and
combinatorial optimization.
6) What is the difference between simulated annealing and simulated evolution
technique?
Answer: The key difference between these two kinds of algorithms is that the
simulated evolution uses the history of previous trial partitionings. Therefore, it is
more efficient than simulated annealing. However, it takes more space to store the
history of the previouspartitioning than the simulated annealing.
7) In aperformance driven partitioning algorithm,what is reduced
or optimized
Answer: In high performance chips, the on-ep delay hàs been greatly reduced The
design of a high performance system reques Pranoning algorithms to reduce the
delay in critical paths. The
cutsize asweil as to minimize the partitioning algorithms,
 EDA Tools
15.74 VLSI Design and
which deal with high performance circuits, are called as timing (performance) driven
process of partitioning for such circuits is called
partitioning algorithms and the
(performance) driven partitioning. ining
delay?
8) How partitioning affects
Answer: Delav within a partition is much less than delay between partitions. If a
critical path is cut many times by the partition, the delay in the path may be too large to
systems.
meet the goals of the highperformance
block and fixed block?
9) What is the difference between flexible
Answer: Blocks with fixed area but unknown dimensions are known as flexible blocks,
fixed blocks.
but blockswith fixed area and fixed dimensions are known as
10) What is the difference between floorplanning and placement for an ASc
design?
Answer: Floorplanning is equal to finding dimension of flexible blocks, then assignine
locations to those biocks. Placement is the problem for assigning locations to the fixed
blocks. Floorplanning is a much more difficult problem as compared to the placement
problem.
11) What is chip planning?
Answer: Both floorplanning and placement problems either ignore the interconnect or
consider it as a secondary objective. Chip planning is an attempt to integrate
floorplarning and interconnect planning. The basic idea is to comprehend impact of
interconnect as early as possible.
12) What is pin assignment?
Answer: The purpose of pin assignment is to define the signal that each pin wll
receive. Pin assignment may be done during floorplanning, placement or after
placement is fixed. If the blocks are flexible then good assignment of nets to pins Can
improve the placement. If the blocks are fixed, it may be possible to exchange a few
pins. This is because some pins are functionally equivalent and some are equipotential.
 15.75
Physical Desigu Automation

Functionally equivalent pins

Equi- potential pins

13) What Physical timing losure ?

Physical timing closure is the process by which an FPGA or a VLSI design with a
physical representation is modified to meet its timing requirements. Most of the
modifications are handled by EDA tools based on directives given by a designer.
Physical timing closure became more important with submicron technologies, as more
and more steps of the design fiow had to be made timing-aware. With present deep
submicrometre technologies it is unthinkable to perform any of the design steps of
placement, clock-tree synthesis and routing without timing constraints. When a
physical representation of the circuit is available, the modifications required to achieve
timing closure are carried out by using more accurate estimations of the delavs.
14) What is sliceable and rectangular floorplan?
Answer: a floorpian that can be bi-partitioned into two sliceable floorplan with
horizontal or vertical cutline is recursively detined as a sliceable floorplan. ÀSliceabla
floorplan can easily be represented by binary tree resulting in eficient algorithm
design.
 15.76 VLSI Designand EDA Tools

arethe most general class of floorplans. The only restriction is

Rectangular floorplans must be rectangular.
that allmodules and boundaries of floorplan
into two phases?
15) Why the routing process is divided
Answer: A VLSI chip may contain several million transistors. As a result, tens of
This makes the routing
thousands of net have to be routed to complete the layout. been divided into 3
problem has
problem computationally hard. Hence the routing each net :
phases. In the first phase, called the global routing, a loose route for
generated. It assigns a list of routing regions to each net without specifying the
geometrical lavout of wires. The second phase, called the detailed routing, finds th
actual geometric layout of each net within the assigned routing regions. Unlike glohal
routing, which considers the entire chip layout, a detailed routing considers just one
region at atime. Detailed routing includes channel routing and switchbox routing.
16) What is a hierarchically defined floorplan?
Answer: when afloorplan tree can be constructed, the design is called a hierarchically
defined floorplan.
17) What is the difference betweena channel and a switchbox?
Answer: A channel is a rectangular routing area that is bounded on two sides by
modules; a switchbox region is a rectangular area that is bounded on all four sides.
18) Name twoglobal routing algorithm.
Answer: ine -probe algorithm and maze routing algorithms
19) Name two global routing models.
Answer: grid based models and checkerboard based models
20) What is H tree?

Answer: Complex digital IC system ieqçires clock generation and clock stabilization.
Once a stable set of clocking signals has been generated, it must be
subchips on the chip. Out of several geometries, the most useful clockdistributed to
structure is H tree used for high density VLSI. It is named after thedistribution
shape of
distribution tree structure letter 'H.
 15.77
Physical Design Automation
21) State main
theme of K-L
Answer:
which Kernighan and Lin
algorithm for partitioning.
vertices starts with a Proposed a graph bisectioning algorithm for a graphof
between random initial partition and then uses pairwise. swapping
22) partitions, until no improvement is possible.
How the initial
partition
Answer: The initial partitions,
is obtained for K-L algorithm?
The input to a
constructive algorithms is the formed
partitions and the new netlist.
circuit components and the [Link].
by using a constructive The output is aset of
initial partitions which can be Constructive algorithms are typically used to form some

23) improved by using other algorithms.

What are factors on which the
quality of a placement depends?
Answer:
[Link] area.
[Link] of routing, and
[Link] performance.
24) What is net metrics?

Answer: The net metrics deal with the assumption that all the nets can be routed
without interfering with other nets or with the componernts. Usiially the length of a net
is important as theinterconnection delays depend on the length of the wire. The net
metrics oniy quantify the amount of wiring and do not account for the actual location
of these [Link] examples of this kind of objective functions are the total length of all
nets and the length of the longest net.
25) What is a congestion metrics?
Answer: The congestion metric is uaed to avoid the buildup of many nets in a
particular area leading to congestion. Example of congestion metric is the number of
nets that intersect with a routing channel.
are classified?
26) How placement algorithms
Answer:
Constructive or iterative
Depending upon initial input:
 EDA Tools
15.78 VLSIDesign and
probabilistic or deterministic
Depending uponoutput:
based, simulation based
Depending upon prvess partitioning
full-custom, semi-custom and gate avee
27) Compare between routing problem in
ASIC?

Answer:

Full custom: general globalrouting problem.

Standard cell: In the standard cell design style, after placement, cell location and
feedthrough position is fixed. However, the channel heights are not fixed. They can be
changed bv varving the distance between adjacent cell rows to accommodate wires
assigned bv a global router As a result, standard cell global routers attempt to
minimize the total channel height.
Gate array: In gate array design style, the size and location of allcells and the routing
channels and their capacitiesare fixed by the architecture. This is the key difference
between gate array and other design styles. Unlike the full custom design stvle and
standard cell design style the primary objective of the global routing in gate arrays is to
guarantee routability. The secondary objective may be to minimize the total wire
length or to minimize the maximum wire length.

EXERCISES
1) What are the different levels of partitioning possible in a system?
2) Differentiate between floorplan and placement.
3) State the goals of floorplanning
4 How placement algorithms are classified?
5) What are the constraints used in
floorplanning?
6) Describe how simulated annealing method helps to solve placement
problem
7 What is the different placement techniques
commonly used?
8) What is global routing?
 Automation 15.79
9) Physical Design
What is local
10)
Give a routing?
brief
11)
automation. description of different processes used for physical design
Formulate and state partition
12)
What are the problem.
13) constraints used in partitioning'
Illustrate K-L algorithm for
14)
What is portioning using asuitable example.
sliceable and rectangular floorplan?

REFERENCES
1] Algorithms for VLSI Physical Desion Automation By Naveed A. Sherwan,
Kluwer Academic Publishers
[2] M. Sarrafzadeh and C.K. Wong, An introduction to VLSI physical design,
Mcgrew-Hill,NY, 1996
[3] S. M Sait and H. Youssef, VLSI Physical Design Automation: Theory and Practice,
World Scientific, Singapore, 1999.
(4] R. H. J. M. Otten, Automatic floorplan design, in Proc. ACM/IEEE Design
Automation Conf., pp. 261-267, June 1982.
Automation, John Wiley & Sons,
[5] S. Gerez, Algorithms for VLSI Design
Chichester, England, 1998.
Hall, 2006
[6] W. Wolf,Modern VLSI deisgn, Prentice
Wang, Yao-Wen Chang and Kwang-Ting (Tim) Cheng Electronic
[7] Laung-Terng and Test, Morgan Kaufmann,2009
Design Automation: Synthesis, Verification,
Conway, L. Introduction To VLSI Systems. Addison-Wesley.
[8] Mead C. And
Reading, MA, 1980.
Physical Design Essentials An ASIC Design Implementation
Khosrow Golshan,
[9] Perspective,springer,2007
Question Bank - Part 1
Subject Code:PCCECE 503

C.O. Type C.O. Total In-Percentage

CO1 14 17.28
CO2 35 43.21
CO3 10 12.35
CO4 11 13.58
CO5 9 11.11
CO6 2 02.47

C.O. Type Marks:2 Marks:5 Marks:10

CO1 14 0 0
CO2 18 10 7
CO3 0 8 2
CO4 1 8 2
CO5 0 5 4
CO6 0 1 1

Please note: A Few Questions have

been deleted (eg. 121, 215 ...) from
the Question Bank as those were
out of scope of this semester's
learning.

4
 Modul
[Link]. Question Marks CO BL
e
91 Explain resitive load MOS inverter circuit. 5 1 CO2 BL2
92 Design clocked J-K F-F using CMOS. 5 3 CO2 BL2
93 Design Full Adder using Transmission Gates 10 3 CO4 BL4
What is Dynamic logic circuit? What are the
94 advantages and disadvantages of dynamic logic 5 3 CO2 BL2
circuit?
What are the steps involved in VLSI design flow?
95 5 3 CO2 BL2
Explain.
96 Implement Z= A (D+E) + BC using static CMOS. 5 3 CO5 BL5
Write short notes on
98 i) PLD 5 1 CO2 BL2
ii) ASIC
99 Design two-input NAND gate using static CMOS. 5 3 CO2 BL2
100 Design 2:1 MUX using CMOS Pass Transistor logic. 5 3 CO3 BL3
Justify: NMOS can pass logic ‘0’ perfectly but cannot
101 5 3 CO4 BL4
pass logic ‘1’ perfectly.
Prove that for a symmetric CMOS device, the size of
102 5 3 CO5 BL5
PMOS is 2.5 times higher than of NMOS.
Calculate the total power dissipation of CMOS
103 5 3 CO2 BL2
inverter.
104 What is PAL? 2 3 CO2 BL2
110 Design NOR based Clocked S-R F-F using CMOS. 5 3 CO2 BL2
Design negative edge triggered D Flip-flop using
111 10 3 CO2 BL2
Transmission gate and CMOS.
Explain Resistive load, NMOS load and CMOS inverter
113 10 1 CO2 BL2
circuits.
116 Design 6 transistor EX-OR circuit. 5 3 CO4 BL4
117 Draw and explain NORA logic. 5 3 CO2 BL2
Derive the threshold voltage Vth for Resistive Load
120 Inverter. Mention the advantages and disadvantages of 10 1 CO5 BL5
Resistive Load Inverter.

Write down the basic current equation of MOSFET in

124 2 1 CO1 BL1
saturation.
How the threshold of CMOS inverter is dependent on
125 5 1 CO6 BL6
W/L ratio of both the transistors.
126 What is transmission Gate? 2 3 CO2 BL2
127 Design Full Adder circuit using static CMOS. 10 3 CO2 BL2
132 What are the drawbacks of Static design? 2 3 CO2 BL2
How the power consumption is related with capacitive
133 2 3 CO2 BL2
load?
4
 Why transmission gate is better than normal CMOS
134 2 3 CO2 BL2
design.
135 Design NAND gate using transmission gate. 2 3 CO4 BL4
136 Design NOR gate using pseudo NMOS logic. 2 3 CO2 BL2
137 What are the drawbacks of Pseudo NMOS logic? 2 3 CO2 BL2
Why transmission gate is known as bidirectional
138 5 3 CO2 BL2
switch?Explain.
184 Define Short-channel MOSFET. 2 1 CO1 BL1
185 State the importance of the Fermi-Dirac function. 2 1 CO1 BL1
Define compound semiconductors with proper
186 2 1 CO1 BL1
examples.
187 Define ‘FOX’ and ‘LOCOS’ in a MOSFET. 2 1 CO1 BL1
188 Describe surface potential in a MOSFET. 2 1 CO2 BL2
189 Explain dry oxidation mechanism. 2 1 CO2 BL2
190 Discuss the formation of 'Inversion layer' in a MOSFET. 2 1 CO2 BL2
191 Describe the importance of CMOS scaling. 2 1 CO2 BL2
192 Interpret 'dry oxidation' and 'wet oxidation'. 5 1 CO3 BL3
Demonstrate high-K dielectrics. Give three examples of
193 5 1 CO3 BL3
high-K materials.
Differentiate accumulation and depletion mode in a
194 5 1 CO4 BL4
MOSFET.
Illustrate weak inversion and strong inversion mode in
195 5 1 CO4 BL4
a MOSFET.
Justify the importance of different 'oxidation'
196 methodologies based on their applications in the 5 1 CO5 BL5
growth of VLSI devices.
Describe Accumulation, Depletion, and Inversion (both
197 weak inversion and strong inversion) modes in a 10 1 CO2 BL2
MOSFET. Explain with appropriate band diagrams.
Interpret what are the ‘parameters’ responsible for the
198 tuning of ‘Threshold voltage’ in a MOSFET. Implement 10 1 CO3 BL3
the equation of threshold voltage in a MOSFET.
Differentiate how the depletion charges and inversion
charges are formed in a MOSFET. Mention how the
199 10 1 CO4 BL4
depletion regions are created at the p-n junctions of a
MOSFET (with appropriate example).
Select different important parameters which can tune
200 ‘Flat-band voltage’ in a MOSFET. Draw charge 10 1 CO5 BL5
distribution profile of the same.
201 Draw the drain characteristic of MOSFET. 2 2 CO1 BL1
202 Draw the transfer characteristic of MOSFET. 2 2 CO1 BL1
203 What is channel length modulation effect in MOSFET ? 2 2 CO1 BL1
204 What is substrate bias effect ? 2 2 CO1 BL1
How many types of MOS single stage amplifiers are
205 2 2 CO1 BL1
there ? Name them.
206 What is meant by process variation ? 2 2 CO1 BL1
207 What is meant by differential signalling ? 2 2 CO1 BL1
Why do we need source follower in an amplifier circuit
208 2 2 CO2 BL2
?

4
209 What are the applications of common gate amplifiers ? 2 2 CO2 BL2
210 What is Miller effect ? 2 2 CO2 BL2
211 What is small signal modelling ? 2 2 CO2 BL2
212 What is circuit transconductance or Gm ? 2 2 CO2 BL2
What are the differences between amplifiers made in
213 2 2 CO2 BL2
discrete level and integrated circuit level ?
Draw the small signal model of a CS amplifier with
214 2 2 CO2 BL2
deep triode load.

Find the output resistance of the basic current mirror

216 5 2 CO3 BL3
circuit.

From the small signal equivalent circuit find the output

218 5 2 CO3 BL3
resistance of a diode connected load.
How is substrate bias effect modelled in the small
219 5 2 CO4 BL4
signal equivalent circuit of MOSFET ?

Find the drain current of a MOSFET whose Vth = 1V;

223 5 2 CO5 BL5
Vds = 3V; Vgs = 5V; W/L = 30.5; kn = 220 µA/V2
Find the expression for input resistance of a common
224 5 2 CO5 BL5
gate amplifier from small signal model.
List down and explain the steps of digital VLSI design
225 10 2 CO2 BL2
flow.

Design a circuit that finds the sum of first N natural

230 10 2 CO6 BL6
numbers using the VLSI design flow.
231 Design R-S Flipflop using static CMOS. 5 1 CO3 BL3
233 Draw CMOS NAND gate. 2 1 CO1 BL1
234 Draw CMOS NOR gate. 2 1 CO1 BL1

4
Question Bank - Part 2
Subject Code:PCCECE 503

C.O. Type C.O. Total In-Percentage

CO1 46 25.14
CO2 45 24.59
CO3 47 25.68
CO4 45 24.59

C.O. Type Marks:2 Marks:5 Marks:10

CO1 21 15 10
CO2 10 24 11
CO3 21 16 10
CO4 20 15 10

Please note: A Few Questions from

this Question Bank have been
deleted (eg.) as those were out of
scope for this semester's syllabus

13
 Modul
[Link]. Question Marks CO BL
e
1 What are design rules ? 2 4 CO4 BL1
With a diagram write the design rule for minimum width
2 2 4 CO4 BL1
of a diffusion line.
With a diagram write the design rule for minimum width
3 2 4 CO4 BL1
of a polysilicon line.
With a diagram write the design rule for minimum
4 2 4 CO4 BL1
spacing between two diffusion lines.
With a diagram write the design rule for minimum
5 2 4 CO4 BL1
spacing between two polysilicon lines.
With a diagram write the design rule for minimum
6 2 4 CO4 BL1
spacing between a diffusion line and a polysilicon line.
In the layout of a MOS transistor, why does the
7 polysilicon line protrude from the diffusion region by a 2 4 CO4 BL2
certain extent?
Draw the layout of a depletion type MOS transistor
8 2 4 CO4 BL3
obeying design rules.
Draw the layout of a diffusion contact obeying design
9 2 4 CO4 BL3
rules.
Draw the layout of a polysilicon contact obeying design
10 2 4 CO4 BL3
rules.
Draw the layout of a metal contact obeying design
11 2 4 CO4 BL3
rules.
Draw the layout of a butting contact obeying design
12 2 4 CO4 BL3
rules.
Why multiple contacts are given in large area
13 2 4 CO4 BL4
MOSFETs ?
With a diagram write the design rule for minimum
14 2 4 CO4 BL1
spacing between two metal lines.
What is fringing capacitance and when does it become
15 2 4 CO4 BL1
important?
16 What is process, voltage and temperature variation? 2 4 CO4 BL2
What is skew corner in VLSI? Give an example where
17 2 4 CO4 BL4
skew corner's effect is most dominant.
18 What is slow corner and fast corner in VLSI? 2 4 CO4 BL2
Why layout of a memory cell needs to be very
19 2 4 CO4 BL4
compact?
What is IC packaging? Mention name of an IC
20 2 4 CO4 BL1
package.
21 Draw the layout of a CMOS inverter. 5 4 CO4 BL3

24 Draw the layout of a CMOS two input NOR gate. 5 4 CO4 BL3

13
 Draw the layout of a two input depletion load NAND
26 5 4 CO4 BL3
gate.
27 Draw the layout of a depletion load inverter. 5 4 CO4 BL3
What is a folded MOSFET and fingered MOSFET?
28 5 4 CO4 BL1
Explain with diagrams.
29 Draw the layout of a two input depletion load NOR gate. 5 4 CO4 BL3
30 Draw the layout of a CMOS two input NAND gate. 5 4 CO4 BL3
What is a dummy transistor? What are the advantages
31 5 4 CO4 BL2
and disadvantages of a dummy transistor?
Draw the layout of two parallel MOS devices with each
32 5 4 CO4 BL3
being a folded MOSFET.
Draw the layout of two parallel MOS devices each
33 5 4 CO4 BL3
having 4 fingers.
Explain the concept of sheet resistance with figure and
34 5 4 CO4 BL4
equations. What is a diffusion resistor?
Draw the C-V curve of a MOS capacitor and explain
35 5 4 CO4 BL1
the nature of the curve.
Draw the 2-dimensional common centroid layout of a
36 differential pair each composed of two equally sized 10 4 CO4 BL3
transistors in parallel.
What is ESD? Explain with a neat diagram an ESD
37 10 4 CO4 BL1
protection circuit.
Draw the matched layout of two capacitors whose ratio
38 10 4 CO4 BL3
is 8.

39 What is noise in VLSI circuits ? What is 10 4 CO4 BL1

electromigration ?

Draw the layout of a common source amplifier with a current

44 source load.
10 4 CO4 BL3
Draw the layout of a common drain amplifier with a
45 10 4 CO4 BL3
diode connected transistor as the source resistance.
Draw the low frequency small signal equivalent circuit
46 2 3 CO3 BL1
of MOSFET.
Draw the high frequency small signal equivalent circuit
47 2 3 CO3 BL1
of MOSFET.
What is the input and output impedance of a common
48 2 3 CO3 BL4
source amplifier?
What is the input and output impedance of a common
49 2 3 CO3 BL4
drain amplifier?

13
 What is the input and output impedance of a common
50 2 3 CO3 BL4
gate amplifier?

52 What is the concept of half circuit? 2 3 CO3 BL2

What is the output resistance of a diode connected

54 2 3 CO3 BL4
load?
55 What is the output resistance of a current source load? 2 3 CO3 BL4
56 What is the output resistance of a deep triode load? 2 3 CO3 BL4
57 What are the disadvantages of basic current mirror? 2 3 CO3 BL1

Find the voltage sensitivity of a resistive voltage divider

61 2 3 CO3 BL3
circuit.
Find the voltage sensitivity of a diode connected MOS
62 2 3 CO3 BL3
based voltage divider circuit.

64 What is charge injection? 2 3 CO3 BL1

65 What is clock feedthrough? 2 3 CO3 BL1

From the small signal equivalent circuit, find the

67 voltage gain of a common gate amplifier. Consider 5 3 CO3 BL4
body bias effect.
What are the main factors to be considered in amplifier
68 5 3 CO3 BL4
design? Comment on the tradeoffs between them.

72 What is body bias effect? Explain it with formulas. 5 3 CO3 BL1

Find an expression for the small signal gain and output
73 resistance of a common gate amplifier with diode 5 3 CO3 BL3
connected load from the small signal equivalent circuit.

13
 Find an expression for the small signal gain and output resistance
76 of a common gate amplifier with triode load from the small signal 5 3 CO3 BL3
equivalent circuit.
Find an expression for the temperature sensitivity of
77 5 3 CO3 BL4
the current of a threshold reference circuit.

List some ways by which you can eliminate charge

79 5 3 CO3 BL1
injection.
List some ways by which you can eliminate clock
80 5 3 CO3 BL1
feedthrough
Explain quantitatively how a MOS switch transfers logic
81 10 3 CO3 BL4
"0" to a holding capacitor.
Explain quantitatively how a MOS switch transfers logic
82 10 3 CO3 BL4
"1" to a holding capacitor.
Find an expression for the small signal gain of the
following circuit.

83 10 3 CO3 BL3

Find an expression for the small signal gain of the

following circuit.

84 10 3 CO3 BL3

13
 Find an expression for the small signal gain of the
following circuit. Assume R1=R2, M3 and M4 are
identical and so is M1 and M2 and all transistors are in
saturation.

85 10 3 CO3 BL3

13
 Find an expression for VREF of the following circuit.

87 10 3 CO3 BL2

Find an expression for VREF of the following circuit.

88 10 3 CO3 BL2

13
 Find the voltage sensitivity of the current of the
following circuit.

89 10 3 CO3 BL3

Find an expression for the gain of a common source

90 10 3 CO3 BL3
amplifier considering device capacitances.
91 Explain resitive load MOS inverter circuit. 5 1 CO2 BL2
92 Design clocked J-K F-F using CMOS. 5 3 CO2 BL3
93 Design Full Adder using Transmission Gates 10 3 CO2 BL3
What is Dynamic logic circuit? What are the
94 advantages and disadvantages of dynamic logic 5 3 CO2 BL3
circuit?
What are the steps involved in VLSI design flow?
95 5 3 CO2 BL3
Explain.
96 Implement Z= A (D+E) + BC using static CMOS. 5 3 CO2 BL3
Explain the DC transfer characteristics of CMOS
97 10 1 CO2 BL3
inverter and explain.
Write short notes on
98 i) PLD 5 1 CO2 BL3
ii) ASIC
99 Design two-input NAND gate using static CMOS. 5 3 CO2 BL3
100 Design 2:1 MUX using CMOS Pass Transistor logic. 5 3 CO2 BL3
Justify: NMOS can pass logic ‘0’ perfectly but cannot
101 5 3 CO2 BL3
pass logic ‘1’ perfectly.
Prove that for a symmetric CMOS device, the size of
102 5 3 CO2 BL3
PMOS is 2.5 times higher than of NMOS.
Calculate the total power dissipation of CMOS
103 5 3 CO2 BL3
inverter.
104 What is PAL? 2 3 CO2 BL3
105 Design Full Adder and full Subtractor using PLD. 10 3 CO2 BL3
Design the following expressions using PLA .
Y1 = AB + A’C + ABC’
106 5 3 CO2 BL3
Y2 = AB’C
Y3 = BC + ABC’
What do you mean by ‘Lambda Rule’ and ‘Micron
107 5 1 CO2 BL3
Rule’?
Explain Dynamic logic circuit and what is its
108 10 3 CO2 BL3
[Link] this drawback is overcome?

13
 A CMOS inverter is Ratioless, but a pseudo NMOS
109 10 3 CO2 BL3
inverter is Ratioed-Explain.
110 Design NOR based Clocked S-R F-F using CMOS. 5 3 CO2 BL3
Design negative edge triggered D Flip-flop using
111 10 3 CO2 BL3
Transmission gate and CMOS.
Draw the circuit of PLA, where, F1=xy+x’z ; F2=
112 5 3 CO2 BL3
y’+x’z and F3= xy+y’z.
Explain Resistive load, NMOS load and CMOS inverter
113 10 1 CO2 BL3
circuits.
Draw and explain the Dynamic CMOS based NAND
114 5 3 CO2 BL2
Gate
Draw and explain the Dynamic CMOS based
115 NOR Gate and also draw the layout diagram of static 10 3 CO2 BL2
CMOS.
116 Design 6 transistor EX-OR circuit. 5 3 CO2 BL2
117 Draw and explain NORA logic. 5 3 CO2 BL2
118 Design F= A+B’C using Dynamic CMOS style. 5 3 CO2 BL2
Derive the expression of ON resistance RON for a MOS
119 5 1 CO2 BL2
operating as a switch. Is it dependent on W/L ratio?
Derive the threshold voltage Vth for Resistive Load
120 Inverter. Mention the advantages and disadvantages of 10 1 CO2 BL2
Resistive Load Inverter.
121 Draw the stick diagram for 2 input NAND gate. 5 4 CO2 BL2
Write short notes on :(4 x 2.5 )
a. MOS diode
b. CMOS Differential amplifier
122 c. Current Mirror and its implementation using 10 4 CO2 BL2
MOSFETs
d. Importance and applications of analog VLSI
circuits and systems, based on MOSFET
Why is reference voltage required in Integrated
123 Circuits? What are the criteria for a good reference 5 2 CO2 BL2
voltage source in VLSI circuit?
Write down the basic current equation of MOSFET in
124 2 1 CO1 BL2
saturation.
How the threshold of CMOS inverter is dependent on
125 5 1 CO2 BL2
W/L ratio of both the transistors.
126 What is transmission Gate? 2 3 CO2 BL2
127 Design Full Adder circuit using static CMOS. 10 3 CO2 BL3
128 Draw J-K flipflop circuit using NAND gate. 2 3 CO2 BL3
129 Write down truth table of J-K flip flop. 2 3 CO2 BL3
130 Design A'+B'C' using dynamic CMOS. 5 3 CO3 BL3
131 What do you mean by Dynamic design style. 2 3 CO3 BL3
132 What are the drawbacks of Static design? 2 3 CO2 BL3
How the power consumption is related with capacitive
133 2 3 CO2 BL3
load?
Why transmission gate is better than normal CMOS
134 2 3 CO2 BL3
design.
135 Design NAND gate using transmission gate. 2 3 CO2 BL3
13
136 Design NOR gate using pseudo NMOS logic. 2 3 CO2 BL3
137 What are the drawbacks of Pseudo NMOS logic? 2 3 CO2 BL3
Why transmission gate is known as bidirectional
138 5 3 CO2 BL1
switch?Explain.
What are the differences between a BJT and a
139 2 1 CO1 BL1
MOSFET ?
Draw the cross-section view of a N-channel MOSFET
140 2 1 CO1 BL1
fabricated in a N-well process.
141 What is constant field scaling ? 2 1 CO1 BL1
142 What is constant voltage scaling ? 2 1 CO1 BL1
143 What is the unit of mobility and body bias coefficient ? 2 1 CO1 BL1
What is the unit of channel length modulation
144 coefficient and µCOX of a MOSFET ? 2 1 CO1 BL1

145 What is channel length modulation effect ? 2 1 CO1 BL1

146 What is work function and electron affinity ? 2 1 CO1 BL1
Define Fermi potential and write down its expression in
147 2 1 CO1 BL1
terms of device parameters.
148 Give the saturation and triode conditions for a PMOS. 2 1 CO1 BL2
What is the advantage of EKV model over other
149 2 1 CO1 BL2
models ?
150 What do you mean by a model parameter ? 2 1 CO1 BL2
When is a MOSFET called short and when it is called
151 2 1 CO1 BL2
narrow ?
What is meant by aspect ratio of a MOSFET ? What is
152 2 1 CO1 BL1
meant by overdrive voltage ?
Draw the capacitance versus voltage curve for a
153 2 1 CO1 BL1
MOSFET.
Define effective channel length. What is the preferred
154 choice for the gate material (on top of the oxide) 2 1 CO1 BL2
nowadays ?
Why is the small signal model for PMOS exactly same
155 2 1 CO1 BL4
as that of NMOS ?
Why in an N-well process the bulk of PMOS can be
156 2 1 CO1 BL4
shorted with the source but for an NMOS it cannot be ?
157 What is the full-form of PDK ? Explain it briefly. 2 1 CO1 BL2
158 Give names of some IC packages. 2 1 CO1 BL3
Draw the non-ideal model of a MOS switch and explain
159 10 1 CO1 BL1
the different parameters involved.
Derive the expression for threshold voltage of a
160 10 1 CO1 BL1
MOSFET from device physics.
Derive the expression for drain current of a MOSFET
161 10 1 CO1 BL1
using the gradual channel approximation.
Draw the equivalent circuit of the Level-1 MOSFET
model and explain different parameters involved. Give
162 10 1 CO1 BL2
the drain current equation of the Level-1 model in both
saturation and triode regions.

13
 Find an expression for the on-resistance of a switch
which consists of an NMOS and PMOS connected in
163 parallel and the gate of NMOS tied to VDD and the gate 10 1 CO1 BL4
of PMOS tied to 0V. One end of the switch is
connected to VDD and the other end to 0V.
A PMOS transistor was fabricated on an n-type
substrate with a bulk doping density of ND = 1016cm-3,
gate doping density (n-type poly) of ND = 1020 cm-3,
164 Qox/q = 4x1010 cm-2, and gate oxide thickness of tox,= 10 1 CO1 BL4
0.1 µm. Calculate the threshold voltage at room
temperature for VSB= 0. Use ε Si = 11.7 ε 0
Explain why several versions of nMOS transistor
models and pMOS transistor models coexist despite
165 10 1 CO1 BL4
the fact that some models are more accurate than
others.
Plot ID versus VGS for a MOS transistor (a) with VDS as a
166 parameter, and (b) with VBS as a parameter. 10 1 CO1 BL4

Consider a diffusion area which has the dimensions 10

µm x 5 µm, and the abrupt junction depth is 0.5 µm. Its
n-type impurity doping level is ND= 1020 cm-3 and the
surrounding p-type substrate doping level is NA=1016
167 10 1 CO1 BL4
cm-3. Determine the capacitance when the diffusion
area is biased at 5V and the substrate is biased at 0V.
In this problem, assume that there is no channel-stop
implant.
Derive the analytical expressions for the junction
168 10 1 CO1 BL1
capacitances of a MOSFET.
Explain why the threshold voltage reduces as the
169 5 1 CO1 BL2
channel length is scaled down.
Explain why the threshold voltage increases as the
170 5 1 CO1 BL2
channel width is scaled down.
Explain the experimental setup which you will use to
171 find the value of µCOX and threshold voltage of a 5 1 CO1 BL2
MOSFET.

13
 Sketch IX as a function of VX when VX varies from 0 to
VDD for the circuit shown below :

172 5 1 CO1 BL4

13
 Using the parameters given below, calculate the
current through two nMOS transistors in series (see
below figure), when the drain of the top transistor is
tied to VDD, the source of the bottom transistor is tied to
Vss=0V and their gates are tied to VDD. The substrate
is also tied to VSS=0V. Assume that W/L = 10 for both
transistors and body bias effect is absent.
k’ = 25 µA/V2
VT0 = 1.0V

174 5 1 CO1 BL4

If W/L ratio is 50/.5 for a PMOS, µpCox = 50 µA/V2, VGS

175 = -2V, VDS = -1V, |Vthp| = 0.7V, find the value of drain 5 1 CO1 BL4
current.
What is meant by VLSI circuit layout ? Explain why a
176 diode connected transistor will always be in saturation 5 1 CO1 BL2
region? How will its drain characteristics look like?
Explain with equations the subthreshold mode of
177 5 1 CO1 BL2
conduction of a MOSFET.
Give the energy band diagram of a MOSFET in
178 5 1 CO1 BL1
accumulation condition and explain it briefly.
Explain briefly with equations mobility degradation in
179 5 1 CO1 BL1
presence of vertical and horizontal field.
Explain the concept of DIBL, punch-through and hot
180 5 1 CO1 BL1
carriers.
What happens to the doping densities in constant
181 voltage and constant field scaling? Explain 5 1 CO1 BL4
quantitatively.
Draw the energy band diagram of a MOSFET under no
182 5 1 CO1 BL2
bias and explain the concept of flat band voltage.
Give the current equations and saturation, triode
183 conditions of a depletion type PMOS transistor. Explain 5 1 CO1 BL4
the concept of CMOS. Give the full form of HBT.

13