Low Power VLSI Design

Dr. J. SUDHAKAR
Professor (ECE) & Principal
 Course Outcomes

• Examine the sources of power dissipation and learn methods to reduce

power dissipation
• Analyze different low power design approaches and learn to estimate
power dissipation
• Assess different low voltage low power adders and multipliers
• Design Low voltage low power memories and compare the performance
between different memories
 Text Books

• Low voltage Low power VLSI Subsystems – Kiat Seng Yeo, Kaushik Roy,
TMH
• Low power CMOS VLSI Circuit design – Kaushik Roy, Sharat C Prasad,
John Wiley & Sons
• Practical low power Digital VLSI Design – Gary K. Yeap, Kluwer Academic
Press
 Unit-I
Fundamentals of Low Power
VLSI Design
Need for Low Power Circuit Design, Sources of Power Dissipation –Switching
Power Dissipation, Short Circuit Power Dissipation, Leakage Power
Dissipation, Glitching Power Dissipation, Short Channel Effects –Drain
Induced Barrier Lowering and Punch Through, Surface Scattering, Velocity
Saturation, Impact Ionization, Hot Electron Effect.
 Introduction

• Battery powered applications drove low power electronics- Pocket

calculators, hearing aids, implantable pacemakers, portable military
equipment, wrist watches etc.

• To improve the circuit performance and to integrate more functions into

each chip, feature size had to shrink more and more.

• Magnitude of power per unit area is kept growing and the heat removal
and cooling has kept getting worse.

• The power efficiency is another important design criteria along with

miniaturization and speed
Vacuum Tubes Transistor First Integrated Circuit
First Microprocessor Handheld ECG

7
Pacemakers to synchronize the heart rhythm

8
 Need for Low power Circuit Design

• Why low power design?

Increasing demand on performance and integrity of VLSI circuits
Popularity of portable devices
Energy consumption in huge number of electronic devices and
datacenters
• Low power design at higher levels of abstraction
Faster design space exploration
Wider view
Higher power reduction
Less cost increase
9
 Sources of Power Dissipation

• Dynamic Power:
When the circuits are under working
condition or active mode. There are
changes in the output and input
conditions with the time (Switching,
Short Circuit & Glitching)
• Static Power:
When the device is powered up but no
signals are changing value. It is due to
leakage mechanisms

10
 Switching Power Dissipation

• Switching power dissipation in VLSI is

the power consumed when a CMOS
logic gate's output node voltage
transitions. It's a significant factor in
the overall energy consumption of
CMOS digital VLSI design circuits.

11
 Switching Power Dissipation

Instantaneous power

Energy

Average Power

12
 Switching Power Dissipation

2
𝑃𝑎𝑣𝑔 = 𝛼 𝑇 𝐶𝐿 𝑉𝐷𝐷 𝑓𝑠𝑤
Where T = Node Transition factor
If the gate directly drives the clock T =1
If the gate output switches once per cycle T = ½
CMOS dynamic gates T = ½
CMOS Static gates T = 0.1
13
 Short Circuit Power Dissipation

• Both the nMOS and pMOS transistors in

the circuit may conduct simultaneously
for a short amount of time during
switching, forming a direct path
between the power supply and the
ground

14
Short Circuit Power Dissipation

15
 Glitch Power Dissipation

In a digital circuit signals before to reach steady state, gates can have multiple
transitions. These undesired transitions power dissipation are called glitch power
or hazards. Glitches are produced in a digital CMOS circuit due to the difference in
signal arrival times at the inputs of the gates. Power dissipated by glitches is
called glitch power and it typically about 20% of the overall power consumption of
the chip and even 70% in some typical cases as the combinational adder

16
 Static Power Dissipation

• Transistor delay time have

decreased by more than 30 %
every technology generation.
• Supply voltage has been scaling
down at the rate of 30% for
every technology, the Threshold
voltage is to be scaled down
accordingly
• The threshold voltage scaling
results in the substantial increase
of the subthreshold current.

17
 Transistor Leakage Mechanisms

Six Short channel leakage mechanisms:

I1 : Reverse bias PN junction leakage

I2 : Subthreshold leakage

I3 : Gate oxide leakage

I4 : Gate current due to hot carrier injection

I5 : Gate Induced Drain Leakage (GIDL)

I6 : Channel Punch through current

I1, I2, I5, I6 are OFF state leakage mechanisms

I3 occurs on both ON and OFF states

I4 occur in ON State

18
 I1 : Reverse bias PN junction leakage

Two main components

• Minority carrier diffusion / drift near the edge of
the depletion region
• Electronic hole pair generation in the depletion
region of the reverse bias junction
For heavily doped PN junctions
• Zener and Band to Band Tunneling also be
present
PN Junction Reverse Leakage (IRev ) is a function
of junction area and doping concentration,
temperature. Jb-b = Current density in Band to
Band Tunne;ing

19
 I2 : Subthreshold leakage

• Occurs when gate voltage is below the

transistor Threshold Voltage Vth .
• In weak inversion, Vds drops almost entirely
across the reverse biased substrate drain pn
junction.
Where
Vth = Threshold voltage
vT = KT/q
Cox = Gate oxide capacitance
0 = Zero bias mobility
m = subthreshold swing coefficient
Wdm = maximum depletion layer width
tox = gate oxide thickness; Cdm = capacitance of depletion layer
20
 I2 : Subthreshold leakage

• The inverse of the slope of the log10 (Ids ) versus Vgs characteristic is called
the subthreshold slope (St )
• Subthreshold slope indicates how effectively the flow of the drain current of a
device can be stopped when Vgs decreased below Vth.

21
 Short Channel Effects

A MOSFET device is considered to be short when the channel length is the same
order of magnitude as the depletion-layer widths (xdD, xdS) of the source and
drain junction.
Short-Channel Effects:
1. The limitation imposed on electron drift characteristics in the channel,
2. The modification of the threshold voltage due to the shortening channel
length.
In particular five different short-channel effects can be distinguished:
1. Drain-induced barrier lowering and punch through
2. Surface scattering
3. Velocity saturation
4. Impact ionization
5. Hot electron effect
22
 Drain Induced Barrier Lowering (DIBL)

• In long channel devices the source and

drain are separated far enough that their
depletion regions have no effect on their
potential, hence the threshold voltage is
virtually independent of the channel length
and drain bias.
• In a short channel device, the source and
drain depletion width and the source drain
potential have a strong effect on the band
bending.
• The threshold voltage and subthreshold
current of a short channel devices vary
with the drain bias.
23
 Drain Induced Barrier Lowering (DIBL)

• DIBL occurs when the depletion region of

the drain interacts with the source near
the channel surface to lower the surface
potential barrier.
• It happens when a high drain voltage is
applied to a short channel device, lowering
the barrier height and resulting in further
decrease of Threshold voltage

24
 Body Effect

• Reverse biasing well to source junction of a MOSFET widens the bulk depletion
region and increase the threshold voltage

Substrate sensitivity

25
 Body Effect
• Subthreshold leakage of MOS including weak inversion, DIBL and body effect
can be modelled as

26
 Punch Through

• Increase in VDS makes depletion width more and more to increase and there
is occurrence of punchthrough once these depletion regions of source and
drain touches. It can be decreased by having higher doping levels either in
substrate or near source and drain

27
 Surface Scattering

• As the channel length becomes smaller due to the lateral extension of the
depletion layer into the channel region, the longitudinal electric field component
εy increases, and the surface mobility becomes field-dependent.

28
 Velocity Saturation

The electron velocity is related to the electron mobility V=E

For higher fields, the velocity does not increase with electric field due to mobility
degradation because of scattering by vertical field. This leads to earlier saturation
of current. i.e. VGS – VTH . Net result is reduction in drain current. The velocity
saturation reduces the transconductance of short channel devices in the saturation
condition.

29
 Impact Ionization

Another undesirable short-channel effect, especially in NMOS, occurs due to the high velocity of
electrons in presence of high longitudinal fields that can generate electron-hole pairs by impact
ionization, that is, by impacting on silicon atoms and ionizing them. Most of the electrons are
attracted by the drain, while the holes enter the substrate to form part of the parasitic substrate
current.
Moreover, the region between the source and the drain can act like the base of an npn
transistor, with the source playing the role of the emitter and the drain that of the collector.
If holes are collected by the source, and the corresponding hole current creates a voltage drop
in the substrate material of the order of 0.6V, the normally reversed-biased substrate-source pn
junction will conduct appreciably. Which lead to
e- may be injected from source to substrate
e- travel toward the drain, increasing their energy and create new e-h pairs
e- may escape the drain fields and affect other devices

30
Impact Ionization

31
 Hot Electron Effect

The channel Hot Electrons effect is caused by electrons flowing in the channel for large VDS. e-
arriving at the Si-SiO2 interface with enough kinetic energy >3.1ev can surmount the surface
potential barrier and injected into the oxide.
These high energy electrons enter the oxide layer, where they can be trapped, giving rise to
oxide charging that can accumulate with time and degrade the device performance by
increasing VT and affect adversely the gate’s control on the drain current.

32
 Unit-II
Low Power Design Approaches
Low Power Design through Voltage Scaling: VTCMOS Circuits, MTCMOS
Circuits, Architectural Approaches: Pipelining and Parallel Processing
Approaches. Switched Capacitance Minimization Approaches- System Level
measures, Circuit level measures, Mask level Measures
 Low Power Design through Voltage Scaling

• The switching power dissipation in CMOS digital circuit is a strong function of

the power supply voltage.
• Although the reduction of power supply voltage significantly reduces the
dynamic power dissipation, the inevitable design trade off is the increase of
the delay.

34
 Low Power Design through Voltage Scaling

• The propagation delay expressions show

that the negative effect of reducing the
power supply voltage upon delay can be
compensated for, if the threshold
voltage (VT ) is scaled down accordingly
• The threshold voltage may not be scaled
to the same extent of the supply voltage
• The reduction of threshold voltage from
0.8V to 0.2 V can improve the delay at
VDD = 2 V by a factor of 2
• Low VT transistors raises significant concerns about noise margins and sub
threshold conduction. → VTCMOS or MTCMOS

35
 Variable Threshold CMOS (VTCMOS)

• Active Mode → Low VT gates

• Stand by Mode → High VT gates
• Adjust the threshold voltages of the transistors by changing the substrate bias

• Conventionally – The
substrate terminals of
nMOS are connected to
ground potential and
substrate terminals of
pMOS are connected to
VDD

36
 Variable Threshold CMOS (VTCMOS)
• In VTCMOS, the transistors are designed inherently with low threshold voltage ,
and the substrate bias voltages of nMOS and pMOS are generated by a variable
substrate bias control circuit.
• VTCMOS technique also can be used to automatically control the threshold
voltages of the transistors in order to reduce leakage currents, and to
compensate for process related fluctuations of the threshold voltages → Self
Adjusting Threshold Voltage Scheme (SATS)

37
 Multi Threshold CMOS (MTCMOS)
• Low VT Transistors → design the logic gates
• High VT Transistors → isolate the logic gates in stand by mode

38
 Multi Threshold CMOS (MTCMOS)
• Advantages:
1. Requires sophisticated substrate bias control mechanism
2. Does not require a twin well or triple well CMOS process

• Disadvantages:
1. Series connected standby transistors → Increases Area
2. Extra Parasitic Capacitances

• VTCMOS and MTCMOS are not possible in some applications where mutli-
threshold voltages are infeasible due to technological limitations.

39
 Pipelining Approach

• System level architectural

measures such as pipelining and
hardware replication techniques
offer feasible alternatives for
better system performance
• Logic functional block f(INPUT)
of the input vector INPUT
• Input and output vectors are
triggered by clock signal CLK.
• A new input vector is latched
into the register array at each
clock cycle , and the output is
valid with a latency of one cycle
40
 Pipelining Approach

• Dynamic power consumption is given by

C Total consists of
capacitance switched in the
input register array,
implement function and
output registry
• The logic function may be
N successive stages and
total of (N-1) register
arrays

41
Pipelining Approach

42
Pipelining Approach

43
 Parallel Processing Approach (H/w Replication)

• This approach is useful

when the logic function to
be implemented is not
suitable for pipelining
• Assume that the
consecutive input vectors
arrive at the same rate as
in the single stage case

44
Parallel Processing Approach (H/w Replication)

45
 Reduction of switched capacitance

• System level measures

If single shared bus is
connected to all modules,
the structure results in large
bus capacitance due to
1. The large number of
drivers and receivers are
sharing the same Tx
medium
2. The parasitic capacitance
of long bus line

46
Reduction of switched capacitance

47
 Unit-II
Low Voltage Low Power Adders
Introduction, Standard Adder cells, CMOS Adders Architectures-Ripple Carry
Adders, Carry Look – Ahead Adders, Carry Save Adders, Low Voltage Low
Power Design Techniques Trends of Technology and Power Supply voltage, Low
voltage Low power Logic styles
 Standard Adder Cells

Introduction:
• Addition is an obligatory operation that is crucial for processing the
fundamental arithmetic operations.
• Most frequently used in many VLSI design paradigms and is by far the
most frequent operations in a general purpose system and in application
specific processors
Standard Cells:
• Basic building blocks used in designing and fabricating different kinds of
adder architectures
• Half Adders: simplest and most fundamental kind of adders

49
Standard Cells – Half Adders

50
Standard Cells – Full Adders

51
Standard Cells – Full Adders- Transistor level

52
Full Adders- Alternative Implementation

53
Full Adders- Transmission Function Theory

54
 CMOS Adders Architectures

Ripple Carry Adders (RCA)

Carry Look Ahead Adders (CLA)
Carry Select Adders (CSL)
Carry Save Adders (CSA)
Carry Skip Adders (CSK)
Conditional Sum Adders (COS)

55
 Ripple Carry Adders

• The basic unit is a Full Adder

• Of all the architectures, the RCA occupies smallest area and offers good
performance
• Depends heavily on the length of carry propagation path

56
Ripple Carry Adders

57
 Carry Look Ahead Adders

• Carry ripple delays grow linearly with the size of the input operand for RCA,
but these delays can be shortened by generating carries of each stage in
parallel
• A carry explicitly does not depend on the preceding one. It can be expressed
as a function of relevant propagate and generate signals. Pi and Gi
• CLA is for better delay reduction performance. CLA consumes more area and
power because of its large number of logic gates.

58
Carry Look Ahead Adder

59
Carry Look Ahead Adder

60
Carry Look Ahead Adder

61
Variation of basic CLA – ELM Adder

62
Manchester Carry Chain Adder

63
 Carry Select Adders

• Substantial compromise between RCA and CLA

• In the CSL both the n-bit operand, Ai and Bi are divided into k blocks possibly
different sizes

64
Performance Evaluation

65
Hybrid Carry look ahead / Carry Select Adder

66
 Carry Save Adders

• CSA for the addition of four 4-bit binary numbers A,B,C,D with an initial with an initial
carry in C0

67
Performance Evaluation

68
Low Voltage Low Power Design Techniques

69
 Low Voltage Low Power Logic styles

• Various design levels

• Architecture level
• Circuit level
• Layout level
• Device level
• Process technology level
• Static and dynamic logic styles
• Static logic families: Evaluate the output whenever there is variation in
input
• Dynamic logic families: Evaluates the output only once for each clock
pulse
70
 XOR/XNOR Gate Implementation

• Full static CMOS logic

• Complementary Pass Transistor Logic
• Double Pass Transistor Logic
• Dual rail Domino dynamic logic

71
XOR/XNOR Gate Implementation

72
XOR/XNOR Gate Implementation

73
XOR/XNOR Gate Implementation

74
 Unit-IV
Low Voltage Low Power Multipliers

Introduction, Overview of Multipliers, Types of Multiplier Architectures, Braun

Multiplier, Baugh Wooley Multiplier, Booth Multiplier, Introduction to Wallace
Tree Multiplier
 Introduction

• A multiplier is one of the most important building block that is widely used in
processor, embedded, VLSI applications, Application specific integrated
circuits and most of the DSP applications.

• The three main thrust parameters of any VLSI design lies in speed, area and
power.

• Low power is an emerging trend which intern can maximize the lifespan of
battery operating time.

• A binary multiplier is an electronic circuit used in digital electronics, such as a

computer, to multiply two binary numbers.

76
 Overview of Multipliers

• As the common digital signal processing algorithms spend most of their time
multiplying, the processors spend a lot of chip area in order to make the
multiplication as fast as possible.

• A typical processor central processing unit devotes a considerable amount of

processing time in performing arithmetic operations, particularly multiplication
operations.

• Multiplication is one of the basic arithmetic operations and it requires

substantially more hardware resources and processing time than addition and
subtraction.

77
 Types of Multiplier Architectures

• MULTIPLIERS can be designed by using any of the following methods. The

main objective is to design low power consumption, consuming less area and
a high speed multiplier.
• There are several types of multipliers in VLSI, including:
• Array multiplier
• Braun multiplier
• Baugh wooley multiplier
• Booth multiplier
• Vedic multiplier
• Wallace tree multiplier
• Serial multiplier
• Serial parallel multiplier
78
 Array Multiplier

• Array multiplier is
similar to how we
perform multiplication
with pen and paper i.e.
finding a partial
product and adding
them together. It is
simple architecture for
implementation.

79
 Braun Multiplier

• A Braun multiplier is a parallel

multiplier used in VLSI that is
also known as a carry save
array multiplier. It's made up
of an array of AND gates and
adders, and is used to perform
signed bit multiplication.

• An n*n bit Braun multiplier

requires n(n-1) adders and n2
AND gates.
80
 Braun Multiplier

• Each of the 𝑋𝑖𝑌𝑗product bits is generated in parallel with the AND gates. Each
partial product can be added to the previous sum of partial products by using
a row of adders.
• The carry out signals are shifted one bit to the left and are then added to the
sums of the first adder and the new partial product.
• The shifting of the carry out bits to the left is done by a carry save adder
(CSA). As the carry bits are passed diagonally downward to the next adder
stage, there is no horizontal carry propagation for the first four rows. Instead,
the respective carry bit is “saved” for the subsequent adder stage.
• Ripple carry adders (RCA) are used at the final stage of the array to output of
the final result.

81
 Baugh Wooley Multiplier

• It is enhanced version of Braun Multiplier and can multiply both unsigned

and signed operands
• A Baugh Wooley multiplication algorithm is an efficient way to handle the
sign bits. This technique has been developed in order to design regular
multipliers suited for 2s compliment numbers.
• For signed multiplication it converts negative operands to 2’s complement
form and performs multiplication. The architecture is based on the carry
save algorithm
• It is one amongst the cost effective ways to handle the sign bits addition
• For n-bit multiplier n(n-1)+3 adders are required

82
Baugh Wooley Multiplier

83
Baugh Wooley Multiplier

84
 Booth Multiplier

• Booth algorithm gives a procedure for multiplying binary integers in

signed 2’s complement representation in efficient way, i.e., less number

of additions/subtractions required.

• It operates on the fact that strings of 0’s in the multiplier require no

addition but just shifting and a string of 1’s in the multiplier from bit

weight 2^k to weight 2^m can be treated as 2^(k+1 ) to 2^m.

• As in all multiplication schemes, booth algorithm requires examination

of the multiplier bits and shifting of the partial product.

85
Booth Multiplier

86
Booth Multiplier

87
Modified Booth Multiplier

88
Modified Booth Multiplier

89
Modified Booth Multiplier

90
Wallace Tree Multiplier

91
 Unit-V
Low Voltage Low Power Memories

Basics of ROM, Low Power ROM Technology, Future Trend and Development
of ROMs, Basics of SRAM, Memory Cell, Precharge and Equalization circuit,
Low Power SRAM Technologies, Basics of DRAM, Self Refresh Circuit, Future
trend and development of DRAM
 Basics of Memory

• Memory refers to the storage units for data and instructions in a chip,

such as Random Access Memory (RAM) and Read-Only Memory (ROM).

• Memory is a very important component in the VLSI Semiconductor

industry. In VLSI Circuits’ memories play a key role in storing huge

data.

• Memory testing in VLSI using Algorithms and Patterns efficiently is

important. Built-in self test, self diagnosis, redundancy analysis and

self repair.

93
Memory Technologies

94
 Basics of ROM: Architecture

• The row and column address decoders

are incorporated to select one out of 2n
word by decoding the n-bit address.

• Conditioning circuit is for pre-charging

the bit lines and the information is
retrieved or read from the bit lines using
the sense amplifiers.

95
1024 bit ROM Architecture

96
 Low Power ROM Technology

• Sources of Power Dissipation

• Low Power Techniques at Architecture Level
1. Divided hierarchical word line structure
2. Selective precharge
3. Difference encoding
• Low Power Techniques at Circuit Level
1. nMOS precharge
2. Voltage scaling
3. On chip high voltage generator

97
Future Trend and Development of ROMs

98
 Basics of SRAM

• RAM is a Read/ Write memory that

each bit stored in its memory cells
may altered to a different bit value
easily and quickly

• RAM can classified into two

categories: SRAM and DRAM

• SRAM utilizes flip flop mechanism

• DRAM stores in the form of charge on

a capacitor

99
Basics of SRAM

100
Basics of SRAM

101