CSCE 3301: COMPUTER ARCHITECTURE
Lecture 1: Introduction
Dr. Cherif Salama
THE LECTURER
• B.Sc. andM.Sc. from Ain Shams University, Egypt
• Ph.D. from Rice University, TX, USA
• Collaborated with Intel Strategic CAD Labs, OR, USA
• Worked in IBM Austin Research Labs, TX, USA
• Lectured at the EELU, MIU, GUC, and ASU
• Served as unit head of the Computer Engineering and
Software Systems (CESS) Program at ASU
• Currently Associate Professor here in the AUC
• Other Research Interests
• Computer-Aided Design
• Hardware Description Languages
• Programming Languages
• GPU Computing
• Arti cial Intelligence and its applications
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CONTACT INFO
A 1% participation bonus will
be assigned for the top 3
participants on Canvas
• Canvas Discussion Discussions
• Email: [email protected]
• Of ce hours (SSE 2149):
• MR 8 to 10 am, or
• + By Email Appointment
• Graduate TAs:
• TBA
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COURSE INFO
• Lectures
• Sec1: MR from 11:30 am to 12:45 pm (SSE CP36)
• Sec2: MR from 2:00 to 3:15 pm (SSE CP21)
• Lecture attendance is of crucial importance
• More than 6 absences = F
• Attendance recorded at the beginning of each
lecture
• Lateness (arriving after attendance is called) is
counted as half an absence Please watch out for
Canvas
• All course material will posted on Canvas Announcements!
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COURSE INFO
• Main Textbook:
• David Patterson and John L. Hennessy, “Computer
Organization and Design RISC-V Edition: The
Hardware/Software Interface, 2nd Edition”, Morgan
Kaufmann, 2021, ISBN 978-0128203316
• Other Textbooks:
• John L. Hennessy and David Patterson, “Computer
Architecture: A Quantitative Approach”, Sixth
Edition, Morgan Kaufmann, 2018, ISBN:
978-0128119051
• David Patterson and Andrew Waterman, “The
RISC-V Reader: An Open Architecture Atlas,”
Strawberry Canyon, 2017, ISBN: 0999249118
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COURSE INFO
• Course Prerequisites:
• CSCE 230/2301 - Digital Design I (or ECNG 2101 Digital Logic Design)
• CSCE 231/2303 - Computer Organization and Assembly Language Programming
• Enthusiasm!
• Course Co-requisites:
• CSCE 339L/3302 Computer Architecture Lab
• Grading:
• Assignments (between 3 & 4): 20%
• Lateness Penalty: 10% per 12 hours (max 24 hours)
• Exams (best 2 out of 3): 40%
• Closed Book
• No Comprehensive Final Exam
• Project1: 25%
• Project2: 15%
• Note: To pass the course, you have to pass (get 50% or more in) each of the assessment
components: assignments, projects, exams
• Check the Syllabus for more details
• Plagiarism = Cheating = Reported Academic Violation
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WHY STUDY COMPUTER
ARCHITECTURE ?
• You (hopefully) know about: Transistors, Logic Gates, Digital Building
Blocks, Synchronous Digital Systems Design, ISA and Assembly
Programming
• It’s time to learn how to put these things together to build fully
functional and ef cient computers
• Get a even deeper understanding of
• Computers inner workings
• Factors affecting computer
performance & performance metrics
• Become an even better programmer
• Microprocessors architecture is simply beautiful!
• You are a CS/CE/EE student
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MOORE’S LAW
60 years ago (in 1965) Gordon Moore Intel co-founder observed
that the number of transistors on a chip was roughly doubling
every 2 years and predicted that this trend was going to continue
for the 10 following years. His prediction now known as Moore’s
law is still valid nowadays (to a certain extent).
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By Max Roser, Hannah Ritchie - https://ourworldindata.org/uploads/2020/11/Transistor-Count-
CSCE 3301 Computer Architecture
over-time.png, CC BY 4.0, https://commons.wikimedia.org/w/index.php?curid=98219918
SYSTEM PRICE VS. PERFORMANCE
1965 1977 1998 2009 2016
IBM System DEC Dell Dimension Intel Core i7
Computer PS3
360/50 VAX11/780 XPS-300 6950X
Image
Memory Size 64 KB 1 MB 64 MB 512 MB up to 128 GB
Performance 0.15 MIPS 1 MIPS 725 MIPS 50,000 MIPS 317,900 MIPS
Price $1M $200K $2412 $500 $1700
Cost per MIPS $6.6M $200K $3.3 $0.01 $0.005
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SO WHAT?
• Making use of the large number of available transistors and the impressive
technological advances is crucial
• Computer Architecture is amazing!
• In this course you will learn how to design modern computer systems
• RISC-V (RV32I) ISA Review
• Single Cycle Processor Design
• ISA Design
• Pipelined Processor Design
• Pipelining Hazards, Exceptions, and Interrupts
• Instruction Level Parallelism
• Superscalar Processor Design
• Advanced Memory Caching and Virtual Memory
• I/O and Buses
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PREVIOUSLY (IN CSCE 2303)
CSCE 2303 Comp. Organization & Assembly Lang. Prog. 12
NOW IN (CSCE 3301)
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FIRST TASK
• Project 1 Milestone 1
• Pick a partner for lab and project (must be from the same lab
section)
• 5% of project1 marks
• Deadline: Thursday Sep 18, 11:59 pm
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THE FIVE CLASSIC COMPONENTS OF A COMPUTER
• Five classic components:
– Memory: where instructions and
data are kept
– Input: writes data to memory
– Output: reads data from memory
– Datapath: performs arithmetic
operations
– Control: sends the signals that
determine the operations of the
datapath, memory, input, and
output according to instructions
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FROM A HIGH-LEVEL LANGUAGE TO THE HARDWARE LANGUAGE
• Instructions and data are just
collection of binary digits (bits)
• Instructions are individual commands
that computers understand and obey
• Hardware executes machine
instructions
• Machine language is the binary
representation of machine
instructions
• Assembly language symbolically
represents machine instructions
• An assembler translates a symbolic
version of a machine instruction
into its binary version
• A high-level programming language
is composed of words and algebraic
notation that can be translated by
a compiler into assembly language
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RISC-V
ISA REVIEW
CSCE 3303 Fundamental Microelectronics
THE RISC-V INSTRUCTION SET
• Used as the example throughout the rest of the course (focus on RV32I)
• Pronounced “RISC Five”. It is an Open and Free ISA developed for educational, research,
and industrial use.
• Krste Asanovi , Andrew Waterman, and Yunsup Lee developed the RISC-V architecture at
UC Berkeley, with input from David Patterson
• Originally developed in UC Berkley in 2010. It is Berkley’s 5th major RISC ISA design (after
RISC-I, RISC-II, SOAR, and SPUR )
• Currently maintained by the RISC-V Foundation: A non-pro t corporation (http://riscv.org).
• Typical of many modern ISAs: e.g., MIPS, ARM, Alpha
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ARITHMETIC OPERATIONS
• Add and subtract, three operands
• Two sources and one destination
add a, b, c # a gets b + c
• All arithmetic operations have this form
• Design Principle 1: Simplicity favors regularity
• Regularity makes implementation simpler
• Simplicity enables higher performance at lower
cost
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ARITHMETIC EXAMPLE
•C code:
f = (g + h) - (i + j);
• Compiled RISC-V code:
add t0, g, h # temp t0 = g + h
add t1, i, j # temp t1 = i + j
sub f, t0, t1 # f = t0 - t1
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REGISTER OPERANDS
• Arithmetic instructions use register operands
• RV32I has a 32 × 32-bit register le
• Used for frequently accessed data
• Numbered 0 to 31
• Named x0, x1, …, x31
• 32-bit data called a “word”
• Design Principle 2: Smaller is faster
• c.f. main memory: millions of locations
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RISC-V REGISTERS
• x0: the constant value 0
• x1: return address
• x2: stack pointer
• x3: global pointer
• x4: thread pointer
• x5 – x7, x28 – x31: temporaries
• x8: frame pointer
• x9, x18 – x27: saved registers
• x10 – x11: function arguments/results
• x12 – x17: function arguments
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REGISTER OPERAND EXAMPLE
•C code:
f = (g + h) - (i + j);
• f, …, j in x19, x20, …, x23
• Compiled RISC-V code:
add x5, x20, x21
add x6, x22, x23
sub x19, x5, x6
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MEMORY OPERANDS
• Main memory used for composite data
• Arrays, structures, dynamic data
• To apply arithmetic operations
• Load values from memory into registers
• Store result from register to memory
• Memory is byte addressed
• Each address identi es an 8-bit byte
• RISC-V is Little Endian (like x86)
• Least-signi cant byte at least address of a word
• Alternative is Big Endian: Most-signi cant byte at least address of a word (e.g.
MIPS)
• RISC-V does NOT require words to be aligned in memory
• Unlike MIPS for example
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MEMORY OPERAND EXAMPLE 1
•C code:
g = h + A[8];
• g in x20, h in x21, base address of A in x22
• Compiled RISC-V code:
• Index 8 requires offset of 32
• 4 bytes per word
lw x9, 32(x22) # load word
add x20, x9, x21
offset base register
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MEMORY OPERAND EXAMPLE 2
•C code:
A[12] = h + A[8];
• h in x21, base address of A in x22
• Compiled RISC-V code:
• Index 8 requires offset of 32
lw x9, 32(x22) # load word
add x9, x21, x9
sw x9, 48(x22) # store word
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REGISTERS VS. MEMORY
• Registersare faster to access than memory
• Operating on memory data requires loads and stores
• More instructions to be executed
• Compiler must use registers for variables as much as possible
• Only spill to memory for less frequently used variables
• Register optimization is important!
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IMMEDIATE OPERANDS
• Constant data speci ed in an instruction
addi x22, x22, 4
• No subtract immediate instruction
• Just use a negative constant
addi x22, x22, -1
• Design Principle 3: Make the common case fast
• Small constants are common
• Immediate operand avoids a load instruction
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THE CONSTANT ZERO
• RISC-V register 0 (x0) is the constant 0
• Cannot be overwritten
• Useful for common operations
• E.g., move between registers
add x21, x20, x0
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REPRESENTING INSTRUCTIONS
• Instructionsare encoded in binary
• Called machine code
• RISC-V instructions
• Encoded as 32-bit instruction words
• Small number of formats encoding
operation code (opcode), register
numbers, …
• Regularity!
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RISC-V R-FORMAT INSTRUCTIONS
funct7 rs2 rs1 funct3 rd opcode
7 bits 5 bits 5 bits 3 bits 5 bits 7 bits
• Instruction elds
• opcode: operation code
• rd: destination register number
• funct3: 3-bit function code (additional opcode)
• rs1: the rst source register number
• rs2: the second source register number
• funct7: 7-bit function code (additional opcode)
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R-FORMAT EXAMPLE
funct7 rs2 rs1 funct3 rd opcode
7 bits 5 bits 5 bits 3 bits 5 bits 7 bits
add x9, x20, x21
0 21 20 0 9 51
0000000 10101 10100 000 01001 0110011
0000 0001 0101 1010 0000 0100 1011 00112 = 015A04B316
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RISC-V I-FORMAT INSTRUCTIONS
immediate rs1 funct3 rd opcode
12 bits 5 bits 3 bits 5 bits 7 bits
• Immediate arithmetic and load instructions
• rs1: source or base register number
• immediate: constant operand, or offset added to base
address
• 2s-complement, sign extended
• Design Principle 4: Good design demands good compromises
• Different formats complicate decoding, but allow 32-bit
instructions uniformly
• Keep formats as similar as possible
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RISC-V S-FORMAT INSTRUCTIONS
imm[11:5] rs2 rs1 funct3 imm[4:0] opcode
7 bits 5 bits 5 bits 3 bits 5 bits 7 bits
• Different immediate format for store instructions
• rs1: base address register number
• rs2: source operand register number
• immediate: offset added to base address
• Split so that rs1 and rs2 elds always in the same place
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REFERENCES
• DavidPatterson and John L. Hennessy, Computer Organization and
Design: RISC-V Edition, Morgan Kaufmann, 2nd Edition, 2021
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